1 // $Id$ 2 //*************************************************************************** 3 // File: 4 // MachineInstr.cpp 5 // 6 // Purpose: 7 // 8 // 9 // Strategy: 10 // 11 // History: 12 // 7/2/01 - Vikram Adve - Created 13 //**************************************************************************/ 14 15 16 #include "llvm/CodeGen/MachineInstr.h" 17 #include "llvm/Method.h" 18 #include "llvm/ConstPoolVals.h" 19 #include "llvm/Instruction.h" 20 21 22 //************************ Class Implementations **************************/ 23 24 // Constructor for instructions with fixed #operands (nearly all) 25 MachineInstr::MachineInstr(MachineOpCode _opCode, 26 OpCodeMask _opCodeMask) 27 : opCode(_opCode), 28 opCodeMask(_opCodeMask), 29 operands(TargetInstrDescriptors[_opCode].numOperands) 30 { 31 assert(TargetInstrDescriptors[_opCode].numOperands >= 0); 32 } 33 34 // Constructor for instructions with variable #operands 35 MachineInstr::MachineInstr(MachineOpCode _opCode, 36 unsigned numOperands, 37 OpCodeMask _opCodeMask) 38 : opCode(_opCode), 39 opCodeMask(_opCodeMask), 40 operands(numOperands) 41 { 42 } 43 44 void 45 MachineInstr::SetMachineOperand(unsigned int i, 46 MachineOperand::MachineOperandType operandType, 47 Value* _val, bool isdef=false) 48 { 49 assert(i < operands.size()); 50 operands[i].Initialize(operandType, _val); 51 operands[i].isDef = isdef || 52 TargetInstrDescriptors[opCode].resultPos == (int) i; 53 } 54 55 void 56 MachineInstr::SetMachineOperand(unsigned int i, 57 MachineOperand::MachineOperandType operandType, 58 int64_t intValue, bool isdef=false) 59 { 60 assert(i < operands.size()); 61 operands[i].InitializeConst(operandType, intValue); 62 operands[i].isDef = isdef || 63 TargetInstrDescriptors[opCode].resultPos == (int) i; 64 } 65 66 void 67 MachineInstr::SetMachineOperand(unsigned int i, 68 unsigned int regNum, bool isdef=false) 69 { 70 assert(i < operands.size()); 71 operands[i].InitializeReg(regNum); 72 operands[i].isDef = isdef || 73 TargetInstrDescriptors[opCode].resultPos == (int) i; 74 } 75 76 void 77 MachineInstr::dump(unsigned int indent) const 78 { 79 for (unsigned i=0; i < indent; i++) 80 cout << " "; 81 82 cout << *this; 83 } 84 85 ostream& 86 operator<< (ostream& os, const MachineInstr& minstr) 87 { 88 os << TargetInstrDescriptors[minstr.opCode].opCodeString; 89 90 for (unsigned i=0, N=minstr.getNumOperands(); i < N; i++) 91 os << "\t" << minstr.getOperand(i); 92 93 #undef DEBUG_VAL_OP_ITERATOR 94 #ifdef DEBUG_VAL_OP_ITERATOR 95 os << endl << "\tValue operands are: "; 96 for (MachineInstr::val_op_const_iterator vo(&minstr); ! vo.done(); ++vo) 97 { 98 const Value* val = *vo; 99 os << val << (vo.isDef()? "(def), " : ", "); 100 } 101 os << endl; 102 #endif 103 104 return os; 105 } 106 107 static inline ostream &OutputOperand(ostream &os, const MachineOperand &mop) { 108 switch (mop.getOperandType()) { 109 case MachineOperand::MO_CCRegister: 110 case MachineOperand::MO_VirtualRegister: 111 return os << "(val " << mop.getVRegValue() << ")"; 112 case MachineOperand::MO_MachineRegister: 113 return os << "(" << mop.getMachineRegNum() << ")"; 114 default: 115 assert(0 && "Unknown operand type"); 116 return os; 117 } 118 } 119 120 121 ostream &operator<<(ostream &os, const MachineOperand &mop) { 122 switch(mop.opType) { 123 case MachineOperand::MO_VirtualRegister: 124 case MachineOperand::MO_MachineRegister: 125 os << "%reg"; 126 return OutputOperand(os, mop); 127 case MachineOperand::MO_CCRegister: 128 os << "%ccreg"; 129 return OutputOperand(os, mop); 130 131 case MachineOperand::MO_SignExtendedImmed: 132 return os << mop.immedVal; 133 134 case MachineOperand::MO_UnextendedImmed: 135 return os << mop.immedVal; 136 137 case MachineOperand::MO_PCRelativeDisp: 138 os << "%disp(label "; 139 return OutputOperand(os, mop) << ")"; 140 141 default: 142 assert(0 && "Unrecognized operand type"); 143 break; 144 } 145 146 return os; 147 } 148 149 150 //--------------------------------------------------------------------------- 151 // Target-independent utility routines for creating machine instructions 152 //--------------------------------------------------------------------------- 153 154 155 //------------------------------------------------------------------------ 156 // Function Set2OperandsFromInstr 157 // Function Set3OperandsFromInstr 158 // 159 // For the common case of 2- and 3-operand arithmetic/logical instructions, 160 // set the m/c instr. operands directly from the VM instruction's operands. 161 // Check whether the first or second operand is 0 and can use a dedicated "0" register. 162 // Check whether the second operand should use an immediate field or register. 163 // (First and third operands are never immediates for such instructions.) 164 // 165 // Arguments: 166 // canDiscardResult: Specifies that the result operand can be discarded 167 // by using the dedicated "0" 168 // 169 // op1position, op2position and resultPosition: Specify in which position 170 // in the machine instruction the 3 operands (arg1, arg2 171 // and result) should go. 172 // 173 // RETURN VALUE: unsigned int flags, where 174 // flags & 0x01 => operand 1 is constant and needs a register 175 // flags & 0x02 => operand 2 is constant and needs a register 176 //------------------------------------------------------------------------ 177 178 void 179 Set2OperandsFromInstr(MachineInstr* minstr, 180 InstructionNode* vmInstrNode, 181 const TargetMachine& target, 182 bool canDiscardResult, 183 int op1Position, 184 int resultPosition) 185 { 186 Set3OperandsFromInstr(minstr, vmInstrNode, target, 187 canDiscardResult, op1Position, 188 /*op2Position*/ -1, resultPosition); 189 } 190 191 #undef REVERT_TO_EXPLICIT_CONSTANT_CHECKS 192 #ifdef REVERT_TO_EXPLICIT_CONSTANT_CHECKS 193 unsigned 194 Set3OperandsFromInstrJUNK(MachineInstr* minstr, 195 InstructionNode* vmInstrNode, 196 const TargetMachine& target, 197 bool canDiscardResult, 198 int op1Position, 199 int op2Position, 200 int resultPosition) 201 { 202 assert(op1Position >= 0); 203 assert(resultPosition >= 0); 204 205 unsigned returnFlags = 0x0; 206 207 // Check if operand 1 is 0. If so, try to use a hardwired 0 register. 208 Value* op1Value = vmInstrNode->leftChild()->getValue(); 209 bool isValidConstant; 210 int64_t intValue = GetConstantValueAsSignedInt(op1Value, isValidConstant); 211 if (isValidConstant && intValue == 0 && target.zeroRegNum >= 0) 212 minstr->SetMachineOperand(op1Position, /*regNum*/ target.zeroRegNum); 213 else 214 { 215 if (op1Value->getValueType() == Value::ConstantVal) 216 {// value is constant and must be loaded from constant pool 217 returnFlags = returnFlags | (1 << op1Position); 218 } 219 minstr->SetMachineOperand(op1Position,MachineOperand::MO_VirtualRegister, 220 op1Value); 221 } 222 223 // Check if operand 2 (if any) fits in the immed. field of the instruction, 224 // or if it is 0 and can use a dedicated machine register 225 if (op2Position >= 0) 226 { 227 Value* op2Value = vmInstrNode->rightChild()->getValue(); 228 int64_t immedValue; 229 unsigned int machineRegNum; 230 231 MachineOperand::MachineOperandType 232 op2type = ChooseRegOrImmed(op2Value, minstr->getOpCode(), target, 233 /*canUseImmed*/ true, 234 machineRegNum, immedValue); 235 236 if (op2type == MachineOperand::MO_MachineRegister) 237 minstr->SetMachineOperand(op2Position, machineRegNum); 238 else if (op2type == MachineOperand::MO_VirtualRegister) 239 { 240 if (op2Value->getValueType() == Value::ConstantVal) 241 {// value is constant and must be loaded from constant pool 242 returnFlags = returnFlags | (1 << op2Position); 243 } 244 minstr->SetMachineOperand(op2Position, op2type, op2Value); 245 } 246 else 247 { 248 assert(op2type != MO_CCRegister); 249 minstr->SetMachineOperand(op2Position, op2type, immedValue); 250 } 251 } 252 253 // If operand 3 (result) can be discarded, use a dead register if one exists 254 if (canDiscardResult && target.zeroRegNum >= 0) 255 minstr->SetMachineOperand(resultPosition, target.zeroRegNum); 256 else 257 minstr->SetMachineOperand(resultPosition, MachineOperand::MO_VirtualRegister, vmInstrNode->getValue()); 258 259 return returnFlags; 260 } 261 #endif 262 263 264 void 265 Set3OperandsFromInstr(MachineInstr* minstr, 266 InstructionNode* vmInstrNode, 267 const TargetMachine& target, 268 bool canDiscardResult, 269 int op1Position, 270 int op2Position, 271 int resultPosition) 272 { 273 assert(op1Position >= 0); 274 assert(resultPosition >= 0); 275 276 // operand 1 277 minstr->SetMachineOperand(op1Position, MachineOperand::MO_VirtualRegister, 278 vmInstrNode->leftChild()->getValue()); 279 280 // operand 2 (if any) 281 if (op2Position >= 0) 282 minstr->SetMachineOperand(op2Position, MachineOperand::MO_VirtualRegister, 283 vmInstrNode->rightChild()->getValue()); 284 285 // result operand: if it can be discarded, use a dead register if one exists 286 if (canDiscardResult && target.zeroRegNum >= 0) 287 minstr->SetMachineOperand(resultPosition, target.zeroRegNum); 288 else 289 minstr->SetMachineOperand(resultPosition, MachineOperand::MO_VirtualRegister, vmInstrNode->getValue()); 290 } 291 292 293 MachineOperand::MachineOperandType 294 ChooseRegOrImmed(Value* val, 295 MachineOpCode opCode, 296 const TargetMachine& target, 297 bool canUseImmed, 298 unsigned int& getMachineRegNum, 299 int64_t& getImmedValue) 300 { 301 MachineOperand::MachineOperandType opType = 302 MachineOperand::MO_VirtualRegister; 303 getMachineRegNum = 0; 304 getImmedValue = 0; 305 306 // Check for the common case first: argument is not constant 307 // 308 if (val->getValueType() != Value::ConstantVal) 309 return opType; 310 311 // Now get the constant value and check if it fits in the IMMED field. 312 // Take advantage of the fact that the max unsigned value will rarely 313 // fit into any IMMED field and ignore that case (i.e., cast smaller 314 // unsigned constants to signed). 315 // 316 bool isValidConstant; 317 int64_t intValue = GetConstantValueAsSignedInt(val, isValidConstant); 318 319 if (isValidConstant) 320 { 321 if (intValue == 0 && target.zeroRegNum >= 0) 322 { 323 opType = MachineOperand::MO_MachineRegister; 324 getMachineRegNum = target.zeroRegNum; 325 } 326 else if (canUseImmed && 327 target.getInstrInfo().constantFitsInImmedField(opCode,intValue)) 328 { 329 opType = MachineOperand::MO_SignExtendedImmed; 330 getImmedValue = intValue; 331 } 332 } 333 334 return opType; 335 } 336 337 338 void 339 PrintMachineInstructions(const Method* method) 340 { 341 cout << "\n" << method->getReturnType() 342 << " \"" << method->getName() << "\"" << endl; 343 344 for (Method::const_iterator BI = method->begin(); BI != method->end(); ++BI) 345 { 346 const BasicBlock* bb = *BI; 347 cout << "\n" 348 << (bb->hasName()? bb->getName() : "Label") 349 << " (" << bb << ")" << ":" 350 << endl; 351 352 const MachineCodeForBasicBlock& mvec = bb->getMachineInstrVec(); 353 for (unsigned i=0; i < mvec.size(); i++) 354 cout << "\t" << *mvec[i] << endl; 355 } 356 cout << endl << "End method \"" << method->getName() << "\"" 357 << endl << endl; 358 } 359