1 // $Id$ 2 //*************************************************************************** 3 // File: 4 // MachineInstr.cpp 5 // 6 // Purpose: 7 // 8 // 9 // Strategy: 10 // 11 // History: 12 // 7/2/01 - Vikram Adve - Created 13 //**************************************************************************/ 14 15 16 #include "llvm/CodeGen/MachineInstr.h" 17 #include "llvm/Method.h" 18 #include "llvm/ConstPoolVals.h" 19 #include "llvm/Instruction.h" 20 21 22 //************************ Class Implementations **************************/ 23 24 // Constructor for instructions with fixed #operands (nearly all) 25 MachineInstr::MachineInstr(MachineOpCode _opCode, 26 OpCodeMask _opCodeMask) 27 : opCode(_opCode), 28 opCodeMask(_opCodeMask), 29 operands(TargetInstrDescriptors[_opCode].numOperands) 30 { 31 assert(TargetInstrDescriptors[_opCode].numOperands >= 0); 32 } 33 34 // Constructor for instructions with variable #operands 35 MachineInstr::MachineInstr(MachineOpCode _opCode, 36 unsigned numOperands, 37 OpCodeMask _opCodeMask) 38 : opCode(_opCode), 39 opCodeMask(_opCodeMask), 40 operands(numOperands) 41 { 42 } 43 44 void 45 MachineInstr::SetMachineOperand(unsigned int i, 46 MachineOperand::MachineOperandType operandType, 47 Value* _val, bool isdef=false) 48 { 49 assert(i < operands.size()); 50 operands[i].Initialize(operandType, _val); 51 operands[i].isDef = isdef || 52 TargetInstrDescriptors[opCode].resultPos == (int) i; 53 } 54 55 void 56 MachineInstr::SetMachineOperand(unsigned int i, 57 MachineOperand::MachineOperandType operandType, 58 int64_t intValue, bool isdef=false) 59 { 60 assert(i < operands.size()); 61 operands[i].InitializeConst(operandType, intValue); 62 operands[i].isDef = isdef || 63 TargetInstrDescriptors[opCode].resultPos == (int) i; 64 } 65 66 void 67 MachineInstr::SetMachineOperand(unsigned int i, 68 unsigned int regNum, bool isdef=false) 69 { 70 assert(i < operands.size()); 71 operands[i].InitializeReg(regNum); 72 operands[i].isDef = isdef || 73 TargetInstrDescriptors[opCode].resultPos == (int) i; 74 } 75 76 void 77 MachineInstr::dump(unsigned int indent) const 78 { 79 for (unsigned i=0; i < indent; i++) 80 cout << " "; 81 82 cout << *this; 83 } 84 85 ostream& 86 operator<< (ostream& os, const MachineInstr& minstr) 87 { 88 os << TargetInstrDescriptors[minstr.opCode].opCodeString; 89 90 for (unsigned i=0, N=minstr.getNumOperands(); i < N; i++) 91 os << "\t" << minstr.getOperand(i); 92 93 #undef DEBUG_VAL_OP_ITERATOR 94 #ifdef DEBUG_VAL_OP_ITERATOR 95 os << endl << "\tValue operands are: "; 96 for (MachineInstr::val_op_const_iterator vo(&minstr); ! vo.done(); ++vo) 97 { 98 const Value* val = *vo; 99 os << val << (vo.isDef()? "(def), " : ", "); 100 } 101 os << endl; 102 #endif 103 104 return os; 105 } 106 107 static inline ostream &OutputOperand(ostream &os, const MachineOperand &mop) { 108 switch (mop.getOperandType()) { 109 case MachineOperand::MO_CCRegister: 110 case MachineOperand::MO_VirtualRegister: 111 return os << "(val " << mop.getVRegValue() << ")"; 112 case MachineOperand::MO_MachineRegister: 113 return os << "(" << mop.getMachineRegNum() << ")"; 114 default: 115 assert(0 && "Unknown operand type"); 116 return os; 117 } 118 } 119 120 121 ostream &operator<<(ostream &os, const MachineOperand &mop) { 122 switch(mop.opType) { 123 case MachineOperand::MO_VirtualRegister: 124 case MachineOperand::MO_MachineRegister: 125 os << "%reg"; 126 return OutputOperand(os, mop); 127 case MachineOperand::MO_CCRegister: 128 os << "%ccreg"; 129 return OutputOperand(os, mop); 130 case MachineOperand::MO_SignExtendedImmed: 131 return os << mop.immedVal; 132 case MachineOperand::MO_UnextendedImmed: 133 return os << mop.immedVal; 134 case MachineOperand::MO_PCRelativeDisp: 135 return os << "%disp(label " << mop.getVRegValue() << ")"; 136 default: 137 assert(0 && "Unrecognized operand type"); 138 break; 139 } 140 141 return os; 142 } 143 144 145 //--------------------------------------------------------------------------- 146 // Target-independent utility routines for creating machine instructions 147 //--------------------------------------------------------------------------- 148 149 150 //------------------------------------------------------------------------ 151 // Function Set2OperandsFromInstr 152 // Function Set3OperandsFromInstr 153 // 154 // For the common case of 2- and 3-operand arithmetic/logical instructions, 155 // set the m/c instr. operands directly from the VM instruction's operands. 156 // Check whether the first or second operand is 0 and can use a dedicated "0" register. 157 // Check whether the second operand should use an immediate field or register. 158 // (First and third operands are never immediates for such instructions.) 159 // 160 // Arguments: 161 // canDiscardResult: Specifies that the result operand can be discarded 162 // by using the dedicated "0" 163 // 164 // op1position, op2position and resultPosition: Specify in which position 165 // in the machine instruction the 3 operands (arg1, arg2 166 // and result) should go. 167 // 168 // RETURN VALUE: unsigned int flags, where 169 // flags & 0x01 => operand 1 is constant and needs a register 170 // flags & 0x02 => operand 2 is constant and needs a register 171 //------------------------------------------------------------------------ 172 173 void 174 Set2OperandsFromInstr(MachineInstr* minstr, 175 InstructionNode* vmInstrNode, 176 const TargetMachine& target, 177 bool canDiscardResult, 178 int op1Position, 179 int resultPosition) 180 { 181 Set3OperandsFromInstr(minstr, vmInstrNode, target, 182 canDiscardResult, op1Position, 183 /*op2Position*/ -1, resultPosition); 184 } 185 186 #undef REVERT_TO_EXPLICIT_CONSTANT_CHECKS 187 #ifdef REVERT_TO_EXPLICIT_CONSTANT_CHECKS 188 unsigned 189 Set3OperandsFromInstrJUNK(MachineInstr* minstr, 190 InstructionNode* vmInstrNode, 191 const TargetMachine& target, 192 bool canDiscardResult, 193 int op1Position, 194 int op2Position, 195 int resultPosition) 196 { 197 assert(op1Position >= 0); 198 assert(resultPosition >= 0); 199 200 unsigned returnFlags = 0x0; 201 202 // Check if operand 1 is 0. If so, try to use a hardwired 0 register. 203 Value* op1Value = vmInstrNode->leftChild()->getValue(); 204 bool isValidConstant; 205 int64_t intValue = GetConstantValueAsSignedInt(op1Value, isValidConstant); 206 if (isValidConstant && intValue == 0 && target.zeroRegNum >= 0) 207 minstr->SetMachineOperand(op1Position, /*regNum*/ target.zeroRegNum); 208 else 209 { 210 if (op1Value->isConstant()) { 211 // value is constant and must be loaded from constant pool 212 returnFlags = returnFlags | (1 << op1Position); 213 } 214 minstr->SetMachineOperand(op1Position, MachineOperand::MO_VirtualRegister, 215 op1Value); 216 } 217 218 // Check if operand 2 (if any) fits in the immed. field of the instruction, 219 // or if it is 0 and can use a dedicated machine register 220 if (op2Position >= 0) 221 { 222 Value* op2Value = vmInstrNode->rightChild()->getValue(); 223 int64_t immedValue; 224 unsigned int machineRegNum; 225 226 MachineOperand::MachineOperandType 227 op2type = ChooseRegOrImmed(op2Value, minstr->getOpCode(), target, 228 /*canUseImmed*/ true, 229 machineRegNum, immedValue); 230 231 if (op2type == MachineOperand::MO_MachineRegister) 232 minstr->SetMachineOperand(op2Position, machineRegNum); 233 else if (op2type == MachineOperand::MO_VirtualRegister) 234 { 235 if (op2Value->isConstant()) { 236 // value is constant and must be loaded from constant pool 237 returnFlags = returnFlags | (1 << op2Position); 238 } 239 minstr->SetMachineOperand(op2Position, op2type, op2Value); 240 } 241 else 242 { 243 assert(op2type != MO_CCRegister); 244 minstr->SetMachineOperand(op2Position, op2type, immedValue); 245 } 246 } 247 248 // If operand 3 (result) can be discarded, use a dead register if one exists 249 if (canDiscardResult && target.zeroRegNum >= 0) 250 minstr->SetMachineOperand(resultPosition, target.zeroRegNum); 251 else 252 minstr->SetMachineOperand(resultPosition, MachineOperand::MO_VirtualRegister, vmInstrNode->getValue()); 253 254 return returnFlags; 255 } 256 #endif 257 258 259 void 260 Set3OperandsFromInstr(MachineInstr* minstr, 261 InstructionNode* vmInstrNode, 262 const TargetMachine& target, 263 bool canDiscardResult, 264 int op1Position, 265 int op2Position, 266 int resultPosition) 267 { 268 assert(op1Position >= 0); 269 assert(resultPosition >= 0); 270 271 // operand 1 272 minstr->SetMachineOperand(op1Position, MachineOperand::MO_VirtualRegister, 273 vmInstrNode->leftChild()->getValue()); 274 275 // operand 2 (if any) 276 if (op2Position >= 0) 277 minstr->SetMachineOperand(op2Position, MachineOperand::MO_VirtualRegister, 278 vmInstrNode->rightChild()->getValue()); 279 280 // result operand: if it can be discarded, use a dead register if one exists 281 if (canDiscardResult && target.zeroRegNum >= 0) 282 minstr->SetMachineOperand(resultPosition, target.zeroRegNum); 283 else 284 minstr->SetMachineOperand(resultPosition, MachineOperand::MO_VirtualRegister, vmInstrNode->getValue()); 285 } 286 287 288 MachineOperand::MachineOperandType 289 ChooseRegOrImmed(Value* val, 290 MachineOpCode opCode, 291 const TargetMachine& target, 292 bool canUseImmed, 293 unsigned int& getMachineRegNum, 294 int64_t& getImmedValue) 295 { 296 MachineOperand::MachineOperandType opType = 297 MachineOperand::MO_VirtualRegister; 298 getMachineRegNum = 0; 299 getImmedValue = 0; 300 301 // Check for the common case first: argument is not constant 302 // 303 ConstPoolVal *CPV = val->castConstant(); 304 if (!CPV) return opType; 305 306 if (CPV->getType() == Type::BoolTy) { 307 ConstPoolBool *CPB = (ConstPoolBool*)CPV; 308 if (!CPB->getValue() && target.zeroRegNum >= 0) { 309 getMachineRegNum = target.zeroRegNum; 310 return MachineOperand::MO_MachineRegister; 311 } 312 313 getImmedValue = 1; 314 return MachineOperand::MO_SignExtendedImmed; 315 } 316 317 if (!CPV->getType()->isIntegral()) return opType; 318 319 // Now get the constant value and check if it fits in the IMMED field. 320 // Take advantage of the fact that the max unsigned value will rarely 321 // fit into any IMMED field and ignore that case (i.e., cast smaller 322 // unsigned constants to signed). 323 // 324 int64_t intValue; 325 if (CPV->getType()->isSigned()) { 326 intValue = ((ConstPoolSInt*)CPV)->getValue(); 327 } else { 328 uint64_t V = ((ConstPoolUInt*)CPV)->getValue(); 329 if (V >= INT64_MAX) return opType; 330 intValue = (int64_t)V; 331 } 332 333 if (intValue == 0 && target.zeroRegNum >= 0){ 334 opType = MachineOperand::MO_MachineRegister; 335 getMachineRegNum = target.zeroRegNum; 336 } else if (canUseImmed && 337 target.getInstrInfo().constantFitsInImmedField(opCode, intValue)) { 338 opType = MachineOperand::MO_SignExtendedImmed; 339 getImmedValue = intValue; 340 } 341 342 return opType; 343 } 344 345 346 void 347 PrintMachineInstructions(const Method* method) 348 { 349 cout << "\n" << method->getReturnType() 350 << " \"" << method->getName() << "\"" << endl; 351 352 for (Method::const_iterator BI = method->begin(); BI != method->end(); ++BI) 353 { 354 const BasicBlock* bb = *BI; 355 cout << "\n" 356 << (bb->hasName()? bb->getName() : "Label") 357 << " (" << bb << ")" << ":" 358 << endl; 359 360 const MachineCodeForBasicBlock& mvec = bb->getMachineInstrVec(); 361 for (unsigned i=0; i < mvec.size(); i++) 362 cout << "\t" << *mvec[i] << endl; 363 } 364 cout << endl << "End method \"" << method->getName() << "\"" 365 << endl << endl; 366 } 367