1 //===-- MachineInstr.cpp --------------------------------------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file was developed by the LLVM research group and is distributed under 6 // the University of Illinois Open Source License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // Methods common to all machine instructions. 11 // 12 // FIXME: Now that MachineInstrs have parent pointers, they should always 13 // print themselves using their MachineFunction's TargetMachine. 14 // 15 //===----------------------------------------------------------------------===// 16 17 #include "llvm/CodeGen/MachineInstr.h" 18 #include "llvm/CodeGen/MachineFunction.h" 19 #include "llvm/Value.h" 20 #include "llvm/Target/TargetMachine.h" 21 #include "llvm/Target/TargetInstrInfo.h" 22 #include "llvm/Target/MRegisterInfo.h" 23 #include "Support/LeakDetector.h" 24 using namespace llvm; 25 26 // Global variable holding an array of descriptors for machine instructions. 27 // The actual object needs to be created separately for each target machine. 28 // This variable is initialized and reset by class TargetInstrInfo. 29 // 30 // FIXME: This should be a property of the target so that more than one target 31 // at a time can be active... 32 // 33 namespace llvm { 34 extern const TargetInstrDescriptor *TargetInstrDescriptors; 35 } 36 37 // Constructor for instructions with variable #operands 38 MachineInstr::MachineInstr(short opcode, unsigned numOperands) 39 : Opcode(opcode), 40 numImplicitRefs(0), 41 operands(numOperands, MachineOperand()), 42 parent(0) { 43 // Make sure that we get added to a machine basicblock 44 LeakDetector::addGarbageObject(this); 45 } 46 47 /// MachineInstr ctor - This constructor only does a _reserve_ of the operands, 48 /// not a resize for them. It is expected that if you use this that you call 49 /// add* methods below to fill up the operands, instead of the Set methods. 50 /// Eventually, the "resizing" ctors will be phased out. 51 /// 52 MachineInstr::MachineInstr(short opcode, unsigned numOperands, bool XX, bool YY) 53 : Opcode(opcode), numImplicitRefs(0), parent(0) { 54 operands.reserve(numOperands); 55 // Make sure that we get added to a machine basicblock 56 LeakDetector::addGarbageObject(this); 57 } 58 59 /// MachineInstr ctor - Work exactly the same as the ctor above, except that the 60 /// MachineInstr is created and added to the end of the specified basic block. 61 /// 62 MachineInstr::MachineInstr(MachineBasicBlock *MBB, short opcode, 63 unsigned numOperands) 64 : Opcode(opcode), numImplicitRefs(0), parent(0) { 65 assert(MBB && "Cannot use inserting ctor with null basic block!"); 66 operands.reserve(numOperands); 67 // Make sure that we get added to a machine basicblock 68 LeakDetector::addGarbageObject(this); 69 MBB->push_back(this); // Add instruction to end of basic block! 70 } 71 72 ///MachineInstr ctor - Copies MachineInstr arg exactly 73 MachineInstr::MachineInstr(const MachineInstr &MI) { 74 Opcode = MI.getOpcode(); 75 numImplicitRefs = MI.getNumImplicitRefs(); 76 operands.reserve(MI.getNumOperands()); 77 78 //Add operands 79 for(unsigned i=0; i < MI.getNumOperands(); ++i) 80 operands.push_back(MachineOperand(MI.getOperand(i))); 81 } 82 83 84 MachineInstr::~MachineInstr() 85 { 86 LeakDetector::removeGarbageObject(this); 87 } 88 89 ///clone - Create a copy of 'this' instruction that is identical in 90 ///all ways except the following: The instruction has no parent The 91 ///instruction has no name 92 MachineInstr* MachineInstr::clone() { 93 return new MachineInstr(*this); 94 } 95 96 /// OperandComplete - Return true if it's illegal to add a new operand 97 /// 98 bool MachineInstr::OperandsComplete() const { 99 int NumOperands = TargetInstrDescriptors[Opcode].numOperands; 100 if (NumOperands >= 0 && getNumOperands() >= (unsigned)NumOperands) 101 return true; // Broken: we have all the operands of this instruction! 102 return false; 103 } 104 105 /// replace - Support for replacing opcode and operands of a MachineInstr in 106 /// place. This only resets the size of the operand vector and initializes it. 107 /// The new operands must be set explicitly later. 108 /// 109 void MachineInstr::replace(short opcode, unsigned numOperands) { 110 assert(getNumImplicitRefs() == 0 && 111 "This is probably broken because implicit refs are going to be lost."); 112 Opcode = opcode; 113 operands.clear(); 114 operands.resize(numOperands, MachineOperand()); 115 116 } 117 118 void MachineInstr::SetMachineOperandVal(unsigned i, 119 MachineOperand::MachineOperandType opTy, 120 Value* V) { 121 assert(i < operands.size()); // may be explicit or implicit op 122 operands[i].opType = opTy; 123 operands[i].contents.value = V; 124 operands[i].regNum = -1; 125 } 126 127 void 128 MachineInstr::SetMachineOperandConst(unsigned i, 129 MachineOperand::MachineOperandType opTy, 130 int intValue) { 131 assert(i < getNumOperands()); // must be explicit op 132 assert(TargetInstrDescriptors[Opcode].resultPos != (int) i && 133 "immed. constant cannot be defined"); 134 135 operands[i].opType = opTy; 136 operands[i].contents.value = NULL; 137 operands[i].contents.immedVal = intValue; 138 operands[i].regNum = -1; 139 operands[i].flags = 0; 140 } 141 142 void MachineInstr::SetMachineOperandReg(unsigned i, int regNum) { 143 assert(i < getNumOperands()); // must be explicit op 144 145 operands[i].opType = MachineOperand::MO_MachineRegister; 146 operands[i].contents.value = NULL; 147 operands[i].regNum = regNum; 148 } 149 150 // Used only by the SPARC back-end. 151 void MachineInstr::SetRegForOperand(unsigned i, int regNum) { 152 assert(i < getNumOperands()); // must be explicit op 153 operands[i].setRegForValue(regNum); 154 } 155 156 // Used only by the SPARC back-end. 157 void MachineInstr::SetRegForImplicitRef(unsigned i, int regNum) { 158 getImplicitOp(i).setRegForValue(regNum); 159 } 160 161 /// substituteValue - Substitute all occurrences of Value* oldVal with newVal 162 /// in all operands and all implicit refs. If defsOnly == true, substitute defs 163 /// only. 164 /// 165 /// FIXME: Fold this into its single caller, at SparcInstrSelection.cpp:2865, 166 /// or make it a static function in that file. 167 /// 168 unsigned 169 MachineInstr::substituteValue(const Value* oldVal, Value* newVal, 170 bool defsOnly, bool notDefsAndUses, 171 bool& someArgsWereIgnored) 172 { 173 assert((!defsOnly || !notDefsAndUses) && 174 "notDefsAndUses is irrelevant if defsOnly == true."); 175 176 unsigned numSubst = 0; 177 178 // Substitute operands 179 for (MachineInstr::val_op_iterator O = begin(), E = end(); O != E; ++O) 180 if (*O == oldVal) 181 if (!defsOnly || 182 notDefsAndUses && (O.isDef() && !O.isUse()) || 183 !notDefsAndUses && O.isDef()) 184 { 185 O.getMachineOperand().contents.value = newVal; 186 ++numSubst; 187 } 188 else 189 someArgsWereIgnored = true; 190 191 // Substitute implicit refs 192 for (unsigned i=0, N=getNumImplicitRefs(); i < N; ++i) 193 if (getImplicitRef(i) == oldVal) 194 if (!defsOnly || 195 notDefsAndUses && (getImplicitOp(i).isDef() && !getImplicitOp(i).isUse()) || 196 !notDefsAndUses && getImplicitOp(i).isDef()) 197 { 198 getImplicitOp(i).contents.value = newVal; 199 ++numSubst; 200 } 201 else 202 someArgsWereIgnored = true; 203 204 return numSubst; 205 } 206 207 void MachineInstr::dump() const { 208 std::cerr << " " << *this; 209 } 210 211 static inline std::ostream& OutputValue(std::ostream &os, const Value* val) { 212 os << "(val "; 213 os << (void*) val; // print address always 214 if (val && val->hasName()) 215 os << " " << val->getName(); // print name also, if available 216 os << ")"; 217 return os; 218 } 219 220 static inline void OutputReg(std::ostream &os, unsigned RegNo, 221 const MRegisterInfo *MRI = 0) { 222 if (!RegNo || MRegisterInfo::isPhysicalRegister(RegNo)) { 223 if (MRI) 224 os << "%" << MRI->get(RegNo).Name; 225 else 226 os << "%mreg(" << RegNo << ")"; 227 } else 228 os << "%reg" << RegNo; 229 } 230 231 static void print(const MachineOperand &MO, std::ostream &OS, 232 const TargetMachine &TM) { 233 const MRegisterInfo *MRI = TM.getRegisterInfo(); 234 bool CloseParen = true; 235 if (MO.isHiBits32()) 236 OS << "%lm("; 237 else if (MO.isLoBits32()) 238 OS << "%lo("; 239 else if (MO.isHiBits64()) 240 OS << "%hh("; 241 else if (MO.isLoBits64()) 242 OS << "%hm("; 243 else 244 CloseParen = false; 245 246 switch (MO.getType()) { 247 case MachineOperand::MO_VirtualRegister: 248 if (MO.getVRegValue()) { 249 OS << "%reg"; 250 OutputValue(OS, MO.getVRegValue()); 251 if (MO.hasAllocatedReg()) 252 OS << "=="; 253 } 254 if (MO.hasAllocatedReg()) 255 OutputReg(OS, MO.getReg(), MRI); 256 break; 257 case MachineOperand::MO_CCRegister: 258 OS << "%ccreg"; 259 OutputValue(OS, MO.getVRegValue()); 260 if (MO.hasAllocatedReg()) { 261 OS << "=="; 262 OutputReg(OS, MO.getReg(), MRI); 263 } 264 break; 265 case MachineOperand::MO_MachineRegister: 266 OutputReg(OS, MO.getMachineRegNum(), MRI); 267 break; 268 case MachineOperand::MO_SignExtendedImmed: 269 OS << (long)MO.getImmedValue(); 270 break; 271 case MachineOperand::MO_UnextendedImmed: 272 OS << (long)MO.getImmedValue(); 273 break; 274 case MachineOperand::MO_PCRelativeDisp: { 275 const Value* opVal = MO.getVRegValue(); 276 bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal); 277 OS << "%disp(" << (isLabel? "label " : "addr-of-val "); 278 if (opVal->hasName()) 279 OS << opVal->getName(); 280 else 281 OS << (const void*) opVal; 282 OS << ")"; 283 break; 284 } 285 case MachineOperand::MO_MachineBasicBlock: 286 OS << "bb<" 287 << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName() 288 << "," << (void*)MO.getMachineBasicBlock()->getBasicBlock() << ">"; 289 break; 290 case MachineOperand::MO_FrameIndex: 291 OS << "<fi#" << MO.getFrameIndex() << ">"; 292 break; 293 case MachineOperand::MO_ConstantPoolIndex: 294 OS << "<cp#" << MO.getConstantPoolIndex() << ">"; 295 break; 296 case MachineOperand::MO_GlobalAddress: 297 OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">"; 298 break; 299 case MachineOperand::MO_ExternalSymbol: 300 OS << "<es:" << MO.getSymbolName() << ">"; 301 break; 302 default: 303 assert(0 && "Unrecognized operand type"); 304 } 305 306 if (CloseParen) 307 OS << ")"; 308 } 309 310 void MachineInstr::print(std::ostream &OS, const TargetMachine &TM) const { 311 unsigned StartOp = 0; 312 313 // Specialize printing if op#0 is definition 314 if (getNumOperands() && getOperand(0).isDef() && !getOperand(0).isUse()) { 315 ::print(getOperand(0), OS, TM); 316 OS << " = "; 317 ++StartOp; // Don't print this operand again! 318 } 319 OS << TM.getInstrInfo().getName(getOpcode()); 320 321 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) { 322 const MachineOperand& mop = getOperand(i); 323 if (i != StartOp) 324 OS << ","; 325 OS << " "; 326 ::print(mop, OS, TM); 327 328 if (mop.isDef()) 329 if (mop.isUse()) 330 OS << "<def&use>"; 331 else 332 OS << "<def>"; 333 } 334 335 // code for printing implicit references 336 if (getNumImplicitRefs()) { 337 OS << "\tImplicitRefs: "; 338 for(unsigned i = 0, e = getNumImplicitRefs(); i != e; ++i) { 339 OS << "\t"; 340 OutputValue(OS, getImplicitRef(i)); 341 if (getImplicitOp(i).isDef()) 342 if (getImplicitOp(i).isUse()) 343 OS << "<def&use>"; 344 else 345 OS << "<def>"; 346 } 347 } 348 349 OS << "\n"; 350 } 351 352 namespace llvm { 353 std::ostream &operator<<(std::ostream &os, const MachineInstr &MI) { 354 // If the instruction is embedded into a basic block, we can find the target 355 // info for the instruction. 356 if (const MachineBasicBlock *MBB = MI.getParent()) { 357 const MachineFunction *MF = MBB->getParent(); 358 MI.print(os, MF->getTarget()); 359 return os; 360 } 361 362 // Otherwise, print it out in the "raw" format without symbolic register names 363 // and such. 364 os << TargetInstrDescriptors[MI.getOpcode()].Name; 365 366 for (unsigned i=0, N=MI.getNumOperands(); i < N; i++) { 367 os << "\t" << MI.getOperand(i); 368 if (MI.getOperand(i).isDef()) 369 if (MI.getOperand(i).isUse()) 370 os << "<d&u>"; 371 else 372 os << "<d>"; 373 } 374 375 // code for printing implicit references 376 unsigned NumOfImpRefs = MI.getNumImplicitRefs(); 377 if (NumOfImpRefs > 0) { 378 os << "\tImplicit: "; 379 for (unsigned z=0; z < NumOfImpRefs; z++) { 380 OutputValue(os, MI.getImplicitRef(z)); 381 if (MI.getImplicitOp(z).isDef()) 382 if (MI.getImplicitOp(z).isUse()) 383 os << "<d&u>"; 384 else 385 os << "<d>"; 386 os << "\t"; 387 } 388 } 389 390 return os << "\n"; 391 } 392 393 std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO) { 394 if (MO.isHiBits32()) 395 OS << "%lm("; 396 else if (MO.isLoBits32()) 397 OS << "%lo("; 398 else if (MO.isHiBits64()) 399 OS << "%hh("; 400 else if (MO.isLoBits64()) 401 OS << "%hm("; 402 403 switch (MO.getType()) 404 { 405 case MachineOperand::MO_VirtualRegister: 406 if (MO.hasAllocatedReg()) 407 OutputReg(OS, MO.getReg()); 408 409 if (MO.getVRegValue()) { 410 if (MO.hasAllocatedReg()) OS << "=="; 411 OS << "%vreg"; 412 OutputValue(OS, MO.getVRegValue()); 413 } 414 break; 415 case MachineOperand::MO_CCRegister: 416 OS << "%ccreg"; 417 OutputValue(OS, MO.getVRegValue()); 418 if (MO.hasAllocatedReg()) { 419 OS << "=="; 420 OutputReg(OS, MO.getReg()); 421 } 422 break; 423 case MachineOperand::MO_MachineRegister: 424 OutputReg(OS, MO.getMachineRegNum()); 425 break; 426 case MachineOperand::MO_SignExtendedImmed: 427 OS << (long)MO.getImmedValue(); 428 break; 429 case MachineOperand::MO_UnextendedImmed: 430 OS << (long)MO.getImmedValue(); 431 break; 432 case MachineOperand::MO_PCRelativeDisp: 433 { 434 const Value* opVal = MO.getVRegValue(); 435 bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal); 436 OS << "%disp(" << (isLabel? "label " : "addr-of-val "); 437 if (opVal->hasName()) 438 OS << opVal->getName(); 439 else 440 OS << (const void*) opVal; 441 OS << ")"; 442 break; 443 } 444 case MachineOperand::MO_MachineBasicBlock: 445 OS << "bb<" 446 << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName() 447 << "," << (void*)MO.getMachineBasicBlock()->getBasicBlock() << ">"; 448 break; 449 case MachineOperand::MO_FrameIndex: 450 OS << "<fi#" << MO.getFrameIndex() << ">"; 451 break; 452 case MachineOperand::MO_ConstantPoolIndex: 453 OS << "<cp#" << MO.getConstantPoolIndex() << ">"; 454 break; 455 case MachineOperand::MO_GlobalAddress: 456 OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">"; 457 break; 458 case MachineOperand::MO_ExternalSymbol: 459 OS << "<es:" << MO.getSymbolName() << ">"; 460 break; 461 default: 462 assert(0 && "Unrecognized operand type"); 463 break; 464 } 465 466 if (MO.isHiBits32() || MO.isLoBits32() || MO.isHiBits64() || MO.isLoBits64()) 467 OS << ")"; 468 469 return OS; 470 } 471 472 } 473