1 //===-- MachineInstr.cpp --------------------------------------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file was developed by the LLVM research group and is distributed under 6 // the University of Illinois Open Source License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // Methods common to all machine instructions. 11 // 12 // FIXME: Now that MachineInstrs have parent pointers, they should always 13 // print themselves using their MachineFunction's TargetMachine. 14 // 15 //===----------------------------------------------------------------------===// 16 17 #include "llvm/CodeGen/MachineInstr.h" 18 #include "llvm/CodeGen/MachineFunction.h" 19 #include "llvm/Value.h" 20 #include "llvm/Target/TargetMachine.h" 21 #include "llvm/Target/TargetInstrInfo.h" 22 #include "llvm/Target/MRegisterInfo.h" 23 #include "llvm/Support/LeakDetector.h" 24 #include <iostream> 25 26 using namespace llvm; 27 28 // Global variable holding an array of descriptors for machine instructions. 29 // The actual object needs to be created separately for each target machine. 30 // This variable is initialized and reset by class TargetInstrInfo. 31 // 32 // FIXME: This should be a property of the target so that more than one target 33 // at a time can be active... 34 // 35 namespace llvm { 36 extern const TargetInstrDescriptor *TargetInstrDescriptors; 37 } 38 39 // Constructor for instructions with variable #operands 40 MachineInstr::MachineInstr(short opcode, unsigned numOperands) 41 : Opcode(opcode), 42 operands(numOperands, MachineOperand()), 43 parent(0) { 44 // Make sure that we get added to a machine basicblock 45 LeakDetector::addGarbageObject(this); 46 } 47 48 /// MachineInstr ctor - This constructor only does a _reserve_ of the operands, 49 /// not a resize for them. It is expected that if you use this that you call 50 /// add* methods below to fill up the operands, instead of the Set methods. 51 /// Eventually, the "resizing" ctors will be phased out. 52 /// 53 MachineInstr::MachineInstr(short opcode, unsigned numOperands, bool XX, bool YY) 54 : Opcode(opcode), parent(0) { 55 operands.reserve(numOperands); 56 // Make sure that we get added to a machine basicblock 57 LeakDetector::addGarbageObject(this); 58 } 59 60 /// MachineInstr ctor - Work exactly the same as the ctor above, except that the 61 /// MachineInstr is created and added to the end of the specified basic block. 62 /// 63 MachineInstr::MachineInstr(MachineBasicBlock *MBB, short opcode, 64 unsigned numOperands) 65 : Opcode(opcode), parent(0) { 66 assert(MBB && "Cannot use inserting ctor with null basic block!"); 67 operands.reserve(numOperands); 68 // Make sure that we get added to a machine basicblock 69 LeakDetector::addGarbageObject(this); 70 MBB->push_back(this); // Add instruction to end of basic block! 71 } 72 73 /// MachineInstr ctor - Copies MachineInstr arg exactly 74 /// 75 MachineInstr::MachineInstr(const MachineInstr &MI) { 76 Opcode = MI.getOpcode(); 77 operands.reserve(MI.getNumOperands()); 78 79 // Add operands 80 for (unsigned i = 0; i < MI.getNumOperands(); ++i) 81 operands.push_back(MachineOperand(MI.getOperand(i))); 82 83 // Set parent, next, and prev to null 84 parent = 0; 85 prev = 0; 86 next = 0; 87 } 88 89 90 MachineInstr::~MachineInstr() { 91 LeakDetector::removeGarbageObject(this); 92 } 93 94 /// clone - Create a copy of 'this' instruction that is identical in all ways 95 /// except the following: the new instruction has no parent and it has no name 96 /// 97 MachineInstr* MachineInstr::clone() const { 98 return new MachineInstr(*this); 99 } 100 101 /// removeFromParent - This method unlinks 'this' from the containing basic 102 /// block, and returns it, but does not delete it. 103 MachineInstr *MachineInstr::removeFromParent() { 104 assert(getParent() && "Not embedded in a basic block!"); 105 getParent()->remove(this); 106 return this; 107 } 108 109 110 /// OperandComplete - Return true if it's illegal to add a new operand 111 /// 112 bool MachineInstr::OperandsComplete() const { 113 int NumOperands = TargetInstrDescriptors[Opcode].numOperands; 114 if (NumOperands >= 0 && getNumOperands() >= (unsigned)NumOperands) 115 return true; // Broken: we have all the operands of this instruction! 116 return false; 117 } 118 119 void MachineInstr::SetMachineOperandVal(unsigned i, 120 MachineOperand::MachineOperandType opTy, 121 Value* V) { 122 assert(i < operands.size()); // may be explicit or implicit op 123 operands[i].opType = opTy; 124 operands[i].contents.value = V; 125 operands[i].extra.regNum = -1; 126 } 127 128 void 129 MachineInstr::SetMachineOperandConst(unsigned i, 130 MachineOperand::MachineOperandType opTy, 131 int intValue) { 132 assert(i < getNumOperands()); // must be explicit op 133 134 operands[i].opType = opTy; 135 operands[i].contents.value = NULL; 136 operands[i].contents.immedVal = intValue; 137 operands[i].extra.regNum = -1; 138 operands[i].flags = 0; 139 } 140 141 void MachineInstr::SetMachineOperandReg(unsigned i, int regNum) { 142 assert(i < getNumOperands()); // must be explicit op 143 144 operands[i].opType = MachineOperand::MO_VirtualRegister; 145 operands[i].contents.value = NULL; 146 operands[i].extra.regNum = regNum; 147 } 148 149 void MachineInstr::dump() const { 150 std::cerr << " " << *this; 151 } 152 153 static inline std::ostream& OutputValue(std::ostream &os, const Value* val) { 154 os << "(val "; 155 os << (void*) val; // print address always 156 if (val && val->hasName()) 157 os << " " << val->getName(); // print name also, if available 158 os << ")"; 159 return os; 160 } 161 162 static inline void OutputReg(std::ostream &os, unsigned RegNo, 163 const MRegisterInfo *MRI = 0) { 164 if (!RegNo || MRegisterInfo::isPhysicalRegister(RegNo)) { 165 if (MRI) 166 os << "%" << MRI->get(RegNo).Name; 167 else 168 os << "%mreg(" << RegNo << ")"; 169 } else 170 os << "%reg" << RegNo; 171 } 172 173 static void print(const MachineOperand &MO, std::ostream &OS, 174 const TargetMachine *TM) { 175 const MRegisterInfo *MRI = 0; 176 177 if (TM) MRI = TM->getRegisterInfo(); 178 179 switch (MO.getType()) { 180 case MachineOperand::MO_VirtualRegister: 181 if (MO.getVRegValue()) { 182 OS << "%reg"; 183 OutputValue(OS, MO.getVRegValue()); 184 if (MO.hasAllocatedReg()) 185 OS << "=="; 186 } 187 if (MO.hasAllocatedReg()) 188 OutputReg(OS, MO.getReg(), MRI); 189 break; 190 case MachineOperand::MO_SignExtendedImmed: 191 OS << (long)MO.getImmedValue(); 192 break; 193 case MachineOperand::MO_UnextendedImmed: 194 OS << (long)MO.getImmedValue(); 195 break; 196 case MachineOperand::MO_MachineBasicBlock: 197 OS << "mbb<" 198 << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName() 199 << "," << (void*)MO.getMachineBasicBlock() << ">"; 200 break; 201 case MachineOperand::MO_FrameIndex: 202 OS << "<fi#" << MO.getFrameIndex() << ">"; 203 break; 204 case MachineOperand::MO_ConstantPoolIndex: 205 OS << "<cp#" << MO.getConstantPoolIndex() << ">"; 206 break; 207 case MachineOperand::MO_JumpTableIndex: 208 OS << "<jt#" << MO.getJumpTableIndex() << ">"; 209 break; 210 case MachineOperand::MO_GlobalAddress: 211 OS << "<ga:" << ((Value*)MO.getGlobal())->getName(); 212 if (MO.getOffset()) OS << "+" << MO.getOffset(); 213 OS << ">"; 214 break; 215 case MachineOperand::MO_ExternalSymbol: 216 OS << "<es:" << MO.getSymbolName(); 217 if (MO.getOffset()) OS << "+" << MO.getOffset(); 218 OS << ">"; 219 break; 220 default: 221 assert(0 && "Unrecognized operand type"); 222 } 223 } 224 225 void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const { 226 unsigned StartOp = 0; 227 228 // Specialize printing if op#0 is definition 229 if (getNumOperands() && getOperand(0).isDef() && !getOperand(0).isUse()) { 230 ::print(getOperand(0), OS, TM); 231 OS << " = "; 232 ++StartOp; // Don't print this operand again! 233 } 234 235 // Must check if Target machine is not null because machine BB could not 236 // be attached to a Machine function yet 237 if (TM) 238 OS << TM->getInstrInfo()->getName(getOpcode()); 239 240 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) { 241 const MachineOperand& mop = getOperand(i); 242 if (i != StartOp) 243 OS << ","; 244 OS << " "; 245 ::print(mop, OS, TM); 246 247 if (mop.isDef()) 248 if (mop.isUse()) 249 OS << "<def&use>"; 250 else 251 OS << "<def>"; 252 } 253 254 OS << "\n"; 255 } 256 257 std::ostream &llvm::operator<<(std::ostream &os, const MachineInstr &MI) { 258 // If the instruction is embedded into a basic block, we can find the target 259 // info for the instruction. 260 if (const MachineBasicBlock *MBB = MI.getParent()) { 261 const MachineFunction *MF = MBB->getParent(); 262 if (MF) 263 MI.print(os, &MF->getTarget()); 264 else 265 MI.print(os, 0); 266 return os; 267 } 268 269 // Otherwise, print it out in the "raw" format without symbolic register names 270 // and such. 271 os << TargetInstrDescriptors[MI.getOpcode()].Name; 272 273 for (unsigned i = 0, N = MI.getNumOperands(); i < N; i++) { 274 os << "\t" << MI.getOperand(i); 275 if (MI.getOperand(i).isDef()) 276 if (MI.getOperand(i).isUse()) 277 os << "<d&u>"; 278 else 279 os << "<d>"; 280 } 281 282 return os << "\n"; 283 } 284 285 std::ostream &llvm::operator<<(std::ostream &OS, const MachineOperand &MO) { 286 switch (MO.getType()) { 287 case MachineOperand::MO_VirtualRegister: 288 if (MO.hasAllocatedReg()) 289 OutputReg(OS, MO.getReg()); 290 291 if (MO.getVRegValue()) { 292 if (MO.hasAllocatedReg()) OS << "=="; 293 OS << "%vreg"; 294 OutputValue(OS, MO.getVRegValue()); 295 } 296 break; 297 case MachineOperand::MO_SignExtendedImmed: 298 OS << (long)MO.getImmedValue(); 299 break; 300 case MachineOperand::MO_UnextendedImmed: 301 OS << (long)MO.getImmedValue(); 302 break; 303 case MachineOperand::MO_MachineBasicBlock: 304 OS << "<mbb:" 305 << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName() 306 << "@" << (void*)MO.getMachineBasicBlock() << ">"; 307 break; 308 case MachineOperand::MO_FrameIndex: 309 OS << "<fi#" << MO.getFrameIndex() << ">"; 310 break; 311 case MachineOperand::MO_ConstantPoolIndex: 312 OS << "<cp#" << MO.getConstantPoolIndex() << ">"; 313 break; 314 case MachineOperand::MO_JumpTableIndex: 315 OS << "<jt#" << MO.getJumpTableIndex() << ">"; 316 break; 317 case MachineOperand::MO_GlobalAddress: 318 OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">"; 319 break; 320 case MachineOperand::MO_ExternalSymbol: 321 OS << "<es:" << MO.getSymbolName() << ">"; 322 break; 323 default: 324 assert(0 && "Unrecognized operand type"); 325 break; 326 } 327 328 return OS; 329 } 330