1 //===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // Methods common to all machine instructions. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "llvm/CodeGen/MachineInstr.h" 15 #include "llvm/Constants.h" 16 #include "llvm/Function.h" 17 #include "llvm/InlineAsm.h" 18 #include "llvm/LLVMContext.h" 19 #include "llvm/Metadata.h" 20 #include "llvm/Module.h" 21 #include "llvm/Type.h" 22 #include "llvm/Value.h" 23 #include "llvm/Assembly/Writer.h" 24 #include "llvm/CodeGen/MachineConstantPool.h" 25 #include "llvm/CodeGen/MachineFunction.h" 26 #include "llvm/CodeGen/MachineMemOperand.h" 27 #include "llvm/CodeGen/MachineModuleInfo.h" 28 #include "llvm/CodeGen/MachineRegisterInfo.h" 29 #include "llvm/CodeGen/PseudoSourceValue.h" 30 #include "llvm/MC/MCInstrDesc.h" 31 #include "llvm/MC/MCSymbol.h" 32 #include "llvm/Target/TargetMachine.h" 33 #include "llvm/Target/TargetInstrInfo.h" 34 #include "llvm/Target/TargetRegisterInfo.h" 35 #include "llvm/Analysis/AliasAnalysis.h" 36 #include "llvm/Analysis/DebugInfo.h" 37 #include "llvm/Support/Debug.h" 38 #include "llvm/Support/ErrorHandling.h" 39 #include "llvm/Support/LeakDetector.h" 40 #include "llvm/Support/MathExtras.h" 41 #include "llvm/Support/raw_ostream.h" 42 #include "llvm/ADT/FoldingSet.h" 43 using namespace llvm; 44 45 //===----------------------------------------------------------------------===// 46 // MachineOperand Implementation 47 //===----------------------------------------------------------------------===// 48 49 /// AddRegOperandToRegInfo - Add this register operand to the specified 50 /// MachineRegisterInfo. If it is null, then the next/prev fields should be 51 /// explicitly nulled out. 52 void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) { 53 assert(isReg() && "Can only add reg operand to use lists"); 54 55 // If the reginfo pointer is null, just explicitly null out or next/prev 56 // pointers, to ensure they are not garbage. 57 if (RegInfo == 0) { 58 Contents.Reg.Prev = 0; 59 Contents.Reg.Next = 0; 60 return; 61 } 62 63 // Otherwise, add this operand to the head of the registers use/def list. 64 MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg()); 65 66 // For SSA values, we prefer to keep the definition at the start of the list. 67 // we do this by skipping over the definition if it is at the head of the 68 // list. 69 if (*Head && (*Head)->isDef()) 70 Head = &(*Head)->Contents.Reg.Next; 71 72 Contents.Reg.Next = *Head; 73 if (Contents.Reg.Next) { 74 assert(getReg() == Contents.Reg.Next->getReg() && 75 "Different regs on the same list!"); 76 Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next; 77 } 78 79 Contents.Reg.Prev = Head; 80 *Head = this; 81 } 82 83 /// RemoveRegOperandFromRegInfo - Remove this register operand from the 84 /// MachineRegisterInfo it is linked with. 85 void MachineOperand::RemoveRegOperandFromRegInfo() { 86 assert(isOnRegUseList() && "Reg operand is not on a use list"); 87 // Unlink this from the doubly linked list of operands. 88 MachineOperand *NextOp = Contents.Reg.Next; 89 *Contents.Reg.Prev = NextOp; 90 if (NextOp) { 91 assert(NextOp->getReg() == getReg() && "Corrupt reg use/def chain!"); 92 NextOp->Contents.Reg.Prev = Contents.Reg.Prev; 93 } 94 Contents.Reg.Prev = 0; 95 Contents.Reg.Next = 0; 96 } 97 98 void MachineOperand::setReg(unsigned Reg) { 99 if (getReg() == Reg) return; // No change. 100 101 // Otherwise, we have to change the register. If this operand is embedded 102 // into a machine function, we need to update the old and new register's 103 // use/def lists. 104 if (MachineInstr *MI = getParent()) 105 if (MachineBasicBlock *MBB = MI->getParent()) 106 if (MachineFunction *MF = MBB->getParent()) { 107 RemoveRegOperandFromRegInfo(); 108 SmallContents.RegNo = Reg; 109 AddRegOperandToRegInfo(&MF->getRegInfo()); 110 return; 111 } 112 113 // Otherwise, just change the register, no problem. :) 114 SmallContents.RegNo = Reg; 115 } 116 117 void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx, 118 const TargetRegisterInfo &TRI) { 119 assert(TargetRegisterInfo::isVirtualRegister(Reg)); 120 if (SubIdx && getSubReg()) 121 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg()); 122 setReg(Reg); 123 if (SubIdx) 124 setSubReg(SubIdx); 125 } 126 127 void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) { 128 assert(TargetRegisterInfo::isPhysicalRegister(Reg)); 129 if (getSubReg()) { 130 Reg = TRI.getSubReg(Reg, getSubReg()); 131 // Note that getSubReg() may return 0 if the sub-register doesn't exist. 132 // That won't happen in legal code. 133 setSubReg(0); 134 } 135 setReg(Reg); 136 } 137 138 /// ChangeToImmediate - Replace this operand with a new immediate operand of 139 /// the specified value. If an operand is known to be an immediate already, 140 /// the setImm method should be used. 141 void MachineOperand::ChangeToImmediate(int64_t ImmVal) { 142 // If this operand is currently a register operand, and if this is in a 143 // function, deregister the operand from the register's use/def list. 144 if (isReg() && getParent() && getParent()->getParent() && 145 getParent()->getParent()->getParent()) 146 RemoveRegOperandFromRegInfo(); 147 148 OpKind = MO_Immediate; 149 Contents.ImmVal = ImmVal; 150 } 151 152 /// ChangeToRegister - Replace this operand with a new register operand of 153 /// the specified value. If an operand is known to be an register already, 154 /// the setReg method should be used. 155 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp, 156 bool isKill, bool isDead, bool isUndef, 157 bool isDebug) { 158 // If this operand is already a register operand, use setReg to update the 159 // register's use/def lists. 160 if (isReg()) { 161 assert(!isEarlyClobber()); 162 setReg(Reg); 163 } else { 164 // Otherwise, change this to a register and set the reg#. 165 OpKind = MO_Register; 166 SmallContents.RegNo = Reg; 167 168 // If this operand is embedded in a function, add the operand to the 169 // register's use/def list. 170 if (MachineInstr *MI = getParent()) 171 if (MachineBasicBlock *MBB = MI->getParent()) 172 if (MachineFunction *MF = MBB->getParent()) 173 AddRegOperandToRegInfo(&MF->getRegInfo()); 174 } 175 176 IsDef = isDef; 177 IsImp = isImp; 178 IsKill = isKill; 179 IsDead = isDead; 180 IsUndef = isUndef; 181 IsInternalRead = false; 182 IsEarlyClobber = false; 183 IsDebug = isDebug; 184 SubReg = 0; 185 } 186 187 /// isIdenticalTo - Return true if this operand is identical to the specified 188 /// operand. 189 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const { 190 if (getType() != Other.getType() || 191 getTargetFlags() != Other.getTargetFlags()) 192 return false; 193 194 switch (getType()) { 195 default: llvm_unreachable("Unrecognized operand type"); 196 case MachineOperand::MO_Register: 197 return getReg() == Other.getReg() && isDef() == Other.isDef() && 198 getSubReg() == Other.getSubReg(); 199 case MachineOperand::MO_Immediate: 200 return getImm() == Other.getImm(); 201 case MachineOperand::MO_CImmediate: 202 return getCImm() == Other.getCImm(); 203 case MachineOperand::MO_FPImmediate: 204 return getFPImm() == Other.getFPImm(); 205 case MachineOperand::MO_MachineBasicBlock: 206 return getMBB() == Other.getMBB(); 207 case MachineOperand::MO_FrameIndex: 208 return getIndex() == Other.getIndex(); 209 case MachineOperand::MO_ConstantPoolIndex: 210 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset(); 211 case MachineOperand::MO_JumpTableIndex: 212 return getIndex() == Other.getIndex(); 213 case MachineOperand::MO_GlobalAddress: 214 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset(); 215 case MachineOperand::MO_ExternalSymbol: 216 return !strcmp(getSymbolName(), Other.getSymbolName()) && 217 getOffset() == Other.getOffset(); 218 case MachineOperand::MO_BlockAddress: 219 return getBlockAddress() == Other.getBlockAddress(); 220 case MachineOperand::MO_MCSymbol: 221 return getMCSymbol() == Other.getMCSymbol(); 222 case MachineOperand::MO_Metadata: 223 return getMetadata() == Other.getMetadata(); 224 } 225 } 226 227 /// print - Print the specified machine operand. 228 /// 229 void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const { 230 // If the instruction is embedded into a basic block, we can find the 231 // target info for the instruction. 232 if (!TM) 233 if (const MachineInstr *MI = getParent()) 234 if (const MachineBasicBlock *MBB = MI->getParent()) 235 if (const MachineFunction *MF = MBB->getParent()) 236 TM = &MF->getTarget(); 237 const TargetRegisterInfo *TRI = TM ? TM->getRegisterInfo() : 0; 238 239 switch (getType()) { 240 case MachineOperand::MO_Register: 241 OS << PrintReg(getReg(), TRI, getSubReg()); 242 243 if (isDef() || isKill() || isDead() || isImplicit() || isUndef() || 244 isInternalRead() || isEarlyClobber()) { 245 OS << '<'; 246 bool NeedComma = false; 247 if (isDef()) { 248 if (NeedComma) OS << ','; 249 if (isEarlyClobber()) 250 OS << "earlyclobber,"; 251 if (isImplicit()) 252 OS << "imp-"; 253 OS << "def"; 254 NeedComma = true; 255 } else if (isImplicit()) { 256 OS << "imp-use"; 257 NeedComma = true; 258 } 259 260 if (isKill() || isDead() || isUndef() || isInternalRead()) { 261 if (NeedComma) OS << ','; 262 NeedComma = false; 263 if (isKill()) { 264 OS << "kill"; 265 NeedComma = true; 266 } 267 if (isDead()) { 268 OS << "dead"; 269 NeedComma = true; 270 } 271 if (isUndef()) { 272 if (NeedComma) OS << ','; 273 OS << "undef"; 274 NeedComma = true; 275 } 276 if (isInternalRead()) { 277 if (NeedComma) OS << ','; 278 OS << "internal"; 279 NeedComma = true; 280 } 281 } 282 OS << '>'; 283 } 284 break; 285 case MachineOperand::MO_Immediate: 286 OS << getImm(); 287 break; 288 case MachineOperand::MO_CImmediate: 289 getCImm()->getValue().print(OS, false); 290 break; 291 case MachineOperand::MO_FPImmediate: 292 if (getFPImm()->getType()->isFloatTy()) 293 OS << getFPImm()->getValueAPF().convertToFloat(); 294 else 295 OS << getFPImm()->getValueAPF().convertToDouble(); 296 break; 297 case MachineOperand::MO_MachineBasicBlock: 298 OS << "<BB#" << getMBB()->getNumber() << ">"; 299 break; 300 case MachineOperand::MO_FrameIndex: 301 OS << "<fi#" << getIndex() << '>'; 302 break; 303 case MachineOperand::MO_ConstantPoolIndex: 304 OS << "<cp#" << getIndex(); 305 if (getOffset()) OS << "+" << getOffset(); 306 OS << '>'; 307 break; 308 case MachineOperand::MO_JumpTableIndex: 309 OS << "<jt#" << getIndex() << '>'; 310 break; 311 case MachineOperand::MO_GlobalAddress: 312 OS << "<ga:"; 313 WriteAsOperand(OS, getGlobal(), /*PrintType=*/false); 314 if (getOffset()) OS << "+" << getOffset(); 315 OS << '>'; 316 break; 317 case MachineOperand::MO_ExternalSymbol: 318 OS << "<es:" << getSymbolName(); 319 if (getOffset()) OS << "+" << getOffset(); 320 OS << '>'; 321 break; 322 case MachineOperand::MO_BlockAddress: 323 OS << '<'; 324 WriteAsOperand(OS, getBlockAddress(), /*PrintType=*/false); 325 OS << '>'; 326 break; 327 case MachineOperand::MO_Metadata: 328 OS << '<'; 329 WriteAsOperand(OS, getMetadata(), /*PrintType=*/false); 330 OS << '>'; 331 break; 332 case MachineOperand::MO_MCSymbol: 333 OS << "<MCSym=" << *getMCSymbol() << '>'; 334 break; 335 default: 336 llvm_unreachable("Unrecognized operand type"); 337 } 338 339 if (unsigned TF = getTargetFlags()) 340 OS << "[TF=" << TF << ']'; 341 } 342 343 //===----------------------------------------------------------------------===// 344 // MachineMemOperand Implementation 345 //===----------------------------------------------------------------------===// 346 347 /// getAddrSpace - Return the LLVM IR address space number that this pointer 348 /// points into. 349 unsigned MachinePointerInfo::getAddrSpace() const { 350 if (V == 0) return 0; 351 return cast<PointerType>(V->getType())->getAddressSpace(); 352 } 353 354 /// getConstantPool - Return a MachinePointerInfo record that refers to the 355 /// constant pool. 356 MachinePointerInfo MachinePointerInfo::getConstantPool() { 357 return MachinePointerInfo(PseudoSourceValue::getConstantPool()); 358 } 359 360 /// getFixedStack - Return a MachinePointerInfo record that refers to the 361 /// the specified FrameIndex. 362 MachinePointerInfo MachinePointerInfo::getFixedStack(int FI, int64_t offset) { 363 return MachinePointerInfo(PseudoSourceValue::getFixedStack(FI), offset); 364 } 365 366 MachinePointerInfo MachinePointerInfo::getJumpTable() { 367 return MachinePointerInfo(PseudoSourceValue::getJumpTable()); 368 } 369 370 MachinePointerInfo MachinePointerInfo::getGOT() { 371 return MachinePointerInfo(PseudoSourceValue::getGOT()); 372 } 373 374 MachinePointerInfo MachinePointerInfo::getStack(int64_t Offset) { 375 return MachinePointerInfo(PseudoSourceValue::getStack(), Offset); 376 } 377 378 MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, unsigned f, 379 uint64_t s, unsigned int a, 380 const MDNode *TBAAInfo) 381 : PtrInfo(ptrinfo), Size(s), 382 Flags((f & ((1 << MOMaxBits) - 1)) | ((Log2_32(a) + 1) << MOMaxBits)), 383 TBAAInfo(TBAAInfo) { 384 assert((PtrInfo.V == 0 || isa<PointerType>(PtrInfo.V->getType())) && 385 "invalid pointer value"); 386 assert(getBaseAlignment() == a && "Alignment is not a power of 2!"); 387 assert((isLoad() || isStore()) && "Not a load/store!"); 388 } 389 390 /// Profile - Gather unique data for the object. 391 /// 392 void MachineMemOperand::Profile(FoldingSetNodeID &ID) const { 393 ID.AddInteger(getOffset()); 394 ID.AddInteger(Size); 395 ID.AddPointer(getValue()); 396 ID.AddInteger(Flags); 397 } 398 399 void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) { 400 // The Value and Offset may differ due to CSE. But the flags and size 401 // should be the same. 402 assert(MMO->getFlags() == getFlags() && "Flags mismatch!"); 403 assert(MMO->getSize() == getSize() && "Size mismatch!"); 404 405 if (MMO->getBaseAlignment() >= getBaseAlignment()) { 406 // Update the alignment value. 407 Flags = (Flags & ((1 << MOMaxBits) - 1)) | 408 ((Log2_32(MMO->getBaseAlignment()) + 1) << MOMaxBits); 409 // Also update the base and offset, because the new alignment may 410 // not be applicable with the old ones. 411 PtrInfo = MMO->PtrInfo; 412 } 413 } 414 415 /// getAlignment - Return the minimum known alignment in bytes of the 416 /// actual memory reference. 417 uint64_t MachineMemOperand::getAlignment() const { 418 return MinAlign(getBaseAlignment(), getOffset()); 419 } 420 421 raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineMemOperand &MMO) { 422 assert((MMO.isLoad() || MMO.isStore()) && 423 "SV has to be a load, store or both."); 424 425 if (MMO.isVolatile()) 426 OS << "Volatile "; 427 428 if (MMO.isLoad()) 429 OS << "LD"; 430 if (MMO.isStore()) 431 OS << "ST"; 432 OS << MMO.getSize(); 433 434 // Print the address information. 435 OS << "["; 436 if (!MMO.getValue()) 437 OS << "<unknown>"; 438 else 439 WriteAsOperand(OS, MMO.getValue(), /*PrintType=*/false); 440 441 // If the alignment of the memory reference itself differs from the alignment 442 // of the base pointer, print the base alignment explicitly, next to the base 443 // pointer. 444 if (MMO.getBaseAlignment() != MMO.getAlignment()) 445 OS << "(align=" << MMO.getBaseAlignment() << ")"; 446 447 if (MMO.getOffset() != 0) 448 OS << "+" << MMO.getOffset(); 449 OS << "]"; 450 451 // Print the alignment of the reference. 452 if (MMO.getBaseAlignment() != MMO.getAlignment() || 453 MMO.getBaseAlignment() != MMO.getSize()) 454 OS << "(align=" << MMO.getAlignment() << ")"; 455 456 // Print TBAA info. 457 if (const MDNode *TBAAInfo = MMO.getTBAAInfo()) { 458 OS << "(tbaa="; 459 if (TBAAInfo->getNumOperands() > 0) 460 WriteAsOperand(OS, TBAAInfo->getOperand(0), /*PrintType=*/false); 461 else 462 OS << "<unknown>"; 463 OS << ")"; 464 } 465 466 // Print nontemporal info. 467 if (MMO.isNonTemporal()) 468 OS << "(nontemporal)"; 469 470 return OS; 471 } 472 473 //===----------------------------------------------------------------------===// 474 // MachineInstr Implementation 475 //===----------------------------------------------------------------------===// 476 477 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with 478 /// MCID NULL and no operands. 479 MachineInstr::MachineInstr() 480 : MCID(0), Flags(0), AsmPrinterFlags(0), 481 MemRefs(0), MemRefsEnd(0), 482 Parent(0) { 483 // Make sure that we get added to a machine basicblock 484 LeakDetector::addGarbageObject(this); 485 } 486 487 void MachineInstr::addImplicitDefUseOperands() { 488 if (MCID->ImplicitDefs) 489 for (const unsigned *ImpDefs = MCID->ImplicitDefs; *ImpDefs; ++ImpDefs) 490 addOperand(MachineOperand::CreateReg(*ImpDefs, true, true)); 491 if (MCID->ImplicitUses) 492 for (const unsigned *ImpUses = MCID->ImplicitUses; *ImpUses; ++ImpUses) 493 addOperand(MachineOperand::CreateReg(*ImpUses, false, true)); 494 } 495 496 /// MachineInstr ctor - This constructor creates a MachineInstr and adds the 497 /// implicit operands. It reserves space for the number of operands specified by 498 /// the MCInstrDesc. 499 MachineInstr::MachineInstr(const MCInstrDesc &tid, bool NoImp) 500 : MCID(&tid), Flags(0), AsmPrinterFlags(0), 501 MemRefs(0), MemRefsEnd(0), Parent(0) { 502 unsigned NumImplicitOps = 0; 503 if (!NoImp) 504 NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses(); 505 Operands.reserve(NumImplicitOps + MCID->getNumOperands()); 506 if (!NoImp) 507 addImplicitDefUseOperands(); 508 // Make sure that we get added to a machine basicblock 509 LeakDetector::addGarbageObject(this); 510 } 511 512 /// MachineInstr ctor - As above, but with a DebugLoc. 513 MachineInstr::MachineInstr(const MCInstrDesc &tid, const DebugLoc dl, 514 bool NoImp) 515 : MCID(&tid), Flags(0), AsmPrinterFlags(0), 516 MemRefs(0), MemRefsEnd(0), Parent(0), debugLoc(dl) { 517 unsigned NumImplicitOps = 0; 518 if (!NoImp) 519 NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses(); 520 Operands.reserve(NumImplicitOps + MCID->getNumOperands()); 521 if (!NoImp) 522 addImplicitDefUseOperands(); 523 // Make sure that we get added to a machine basicblock 524 LeakDetector::addGarbageObject(this); 525 } 526 527 /// MachineInstr ctor - Work exactly the same as the ctor two above, except 528 /// that the MachineInstr is created and added to the end of the specified 529 /// basic block. 530 MachineInstr::MachineInstr(MachineBasicBlock *MBB, const MCInstrDesc &tid) 531 : MCID(&tid), Flags(0), AsmPrinterFlags(0), 532 MemRefs(0), MemRefsEnd(0), Parent(0) { 533 assert(MBB && "Cannot use inserting ctor with null basic block!"); 534 unsigned NumImplicitOps = 535 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses(); 536 Operands.reserve(NumImplicitOps + MCID->getNumOperands()); 537 addImplicitDefUseOperands(); 538 // Make sure that we get added to a machine basicblock 539 LeakDetector::addGarbageObject(this); 540 MBB->push_back(this); // Add instruction to end of basic block! 541 } 542 543 /// MachineInstr ctor - As above, but with a DebugLoc. 544 /// 545 MachineInstr::MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl, 546 const MCInstrDesc &tid) 547 : MCID(&tid), Flags(0), AsmPrinterFlags(0), 548 MemRefs(0), MemRefsEnd(0), Parent(0), debugLoc(dl) { 549 assert(MBB && "Cannot use inserting ctor with null basic block!"); 550 unsigned NumImplicitOps = 551 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses(); 552 Operands.reserve(NumImplicitOps + MCID->getNumOperands()); 553 addImplicitDefUseOperands(); 554 // Make sure that we get added to a machine basicblock 555 LeakDetector::addGarbageObject(this); 556 MBB->push_back(this); // Add instruction to end of basic block! 557 } 558 559 /// MachineInstr ctor - Copies MachineInstr arg exactly 560 /// 561 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI) 562 : MCID(&MI.getDesc()), Flags(0), AsmPrinterFlags(0), 563 MemRefs(MI.MemRefs), MemRefsEnd(MI.MemRefsEnd), 564 Parent(0), debugLoc(MI.getDebugLoc()) { 565 Operands.reserve(MI.getNumOperands()); 566 567 // Add operands 568 for (unsigned i = 0; i != MI.getNumOperands(); ++i) 569 addOperand(MI.getOperand(i)); 570 571 // Copy all the flags. 572 Flags = MI.Flags; 573 574 // Set parent to null. 575 Parent = 0; 576 577 LeakDetector::addGarbageObject(this); 578 } 579 580 MachineInstr::~MachineInstr() { 581 LeakDetector::removeGarbageObject(this); 582 #ifndef NDEBUG 583 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 584 assert(Operands[i].ParentMI == this && "ParentMI mismatch!"); 585 assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) && 586 "Reg operand def/use list corrupted"); 587 } 588 #endif 589 } 590 591 /// getRegInfo - If this instruction is embedded into a MachineFunction, 592 /// return the MachineRegisterInfo object for the current function, otherwise 593 /// return null. 594 MachineRegisterInfo *MachineInstr::getRegInfo() { 595 if (MachineBasicBlock *MBB = getParent()) 596 return &MBB->getParent()->getRegInfo(); 597 return 0; 598 } 599 600 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in 601 /// this instruction from their respective use lists. This requires that the 602 /// operands already be on their use lists. 603 void MachineInstr::RemoveRegOperandsFromUseLists() { 604 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 605 if (Operands[i].isReg()) 606 Operands[i].RemoveRegOperandFromRegInfo(); 607 } 608 } 609 610 /// AddRegOperandsToUseLists - Add all of the register operands in 611 /// this instruction from their respective use lists. This requires that the 612 /// operands not be on their use lists yet. 613 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) { 614 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 615 if (Operands[i].isReg()) 616 Operands[i].AddRegOperandToRegInfo(&RegInfo); 617 } 618 } 619 620 621 /// addOperand - Add the specified operand to the instruction. If it is an 622 /// implicit operand, it is added to the end of the operand list. If it is 623 /// an explicit operand it is added at the end of the explicit operand list 624 /// (before the first implicit operand). 625 void MachineInstr::addOperand(const MachineOperand &Op) { 626 assert(MCID && "Cannot add operands before providing an instr descriptor"); 627 bool isImpReg = Op.isReg() && Op.isImplicit(); 628 MachineRegisterInfo *RegInfo = getRegInfo(); 629 630 // If the Operands backing store is reallocated, all register operands must 631 // be removed and re-added to RegInfo. It is storing pointers to operands. 632 bool Reallocate = RegInfo && 633 !Operands.empty() && Operands.size() == Operands.capacity(); 634 635 // Find the insert location for the new operand. Implicit registers go at 636 // the end, everything goes before the implicit regs. 637 unsigned OpNo = Operands.size(); 638 639 // Remove all the implicit operands from RegInfo if they need to be shifted. 640 // FIXME: Allow mixed explicit and implicit operands on inline asm. 641 // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as 642 // implicit-defs, but they must not be moved around. See the FIXME in 643 // InstrEmitter.cpp. 644 if (!isImpReg && !isInlineAsm()) { 645 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) { 646 --OpNo; 647 if (RegInfo) 648 Operands[OpNo].RemoveRegOperandFromRegInfo(); 649 } 650 } 651 652 // OpNo now points as the desired insertion point. Unless this is a variadic 653 // instruction, only implicit regs are allowed beyond MCID->getNumOperands(). 654 assert((isImpReg || MCID->isVariadic() || OpNo < MCID->getNumOperands()) && 655 "Trying to add an operand to a machine instr that is already done!"); 656 657 // All operands from OpNo have been removed from RegInfo. If the Operands 658 // backing store needs to be reallocated, we also need to remove any other 659 // register operands. 660 if (Reallocate) 661 for (unsigned i = 0; i != OpNo; ++i) 662 if (Operands[i].isReg()) 663 Operands[i].RemoveRegOperandFromRegInfo(); 664 665 // Insert the new operand at OpNo. 666 Operands.insert(Operands.begin() + OpNo, Op); 667 Operands[OpNo].ParentMI = this; 668 669 // The Operands backing store has now been reallocated, so we can re-add the 670 // operands before OpNo. 671 if (Reallocate) 672 for (unsigned i = 0; i != OpNo; ++i) 673 if (Operands[i].isReg()) 674 Operands[i].AddRegOperandToRegInfo(RegInfo); 675 676 // When adding a register operand, tell RegInfo about it. 677 if (Operands[OpNo].isReg()) { 678 // Add the new operand to RegInfo, even when RegInfo is NULL. 679 // This will initialize the linked list pointers. 680 Operands[OpNo].AddRegOperandToRegInfo(RegInfo); 681 // If the register operand is flagged as early, mark the operand as such. 682 if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1) 683 Operands[OpNo].setIsEarlyClobber(true); 684 } 685 686 // Re-add all the implicit ops. 687 if (RegInfo) { 688 for (unsigned i = OpNo + 1, e = Operands.size(); i != e; ++i) { 689 assert(Operands[i].isReg() && "Should only be an implicit reg!"); 690 Operands[i].AddRegOperandToRegInfo(RegInfo); 691 } 692 } 693 } 694 695 /// RemoveOperand - Erase an operand from an instruction, leaving it with one 696 /// fewer operand than it started with. 697 /// 698 void MachineInstr::RemoveOperand(unsigned OpNo) { 699 assert(OpNo < Operands.size() && "Invalid operand number"); 700 701 // Special case removing the last one. 702 if (OpNo == Operands.size()-1) { 703 // If needed, remove from the reg def/use list. 704 if (Operands.back().isReg() && Operands.back().isOnRegUseList()) 705 Operands.back().RemoveRegOperandFromRegInfo(); 706 707 Operands.pop_back(); 708 return; 709 } 710 711 // Otherwise, we are removing an interior operand. If we have reginfo to 712 // update, remove all operands that will be shifted down from their reg lists, 713 // move everything down, then re-add them. 714 MachineRegisterInfo *RegInfo = getRegInfo(); 715 if (RegInfo) { 716 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) { 717 if (Operands[i].isReg()) 718 Operands[i].RemoveRegOperandFromRegInfo(); 719 } 720 } 721 722 Operands.erase(Operands.begin()+OpNo); 723 724 if (RegInfo) { 725 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) { 726 if (Operands[i].isReg()) 727 Operands[i].AddRegOperandToRegInfo(RegInfo); 728 } 729 } 730 } 731 732 /// addMemOperand - Add a MachineMemOperand to the machine instruction. 733 /// This function should be used only occasionally. The setMemRefs function 734 /// is the primary method for setting up a MachineInstr's MemRefs list. 735 void MachineInstr::addMemOperand(MachineFunction &MF, 736 MachineMemOperand *MO) { 737 mmo_iterator OldMemRefs = MemRefs; 738 mmo_iterator OldMemRefsEnd = MemRefsEnd; 739 740 size_t NewNum = (MemRefsEnd - MemRefs) + 1; 741 mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum); 742 mmo_iterator NewMemRefsEnd = NewMemRefs + NewNum; 743 744 std::copy(OldMemRefs, OldMemRefsEnd, NewMemRefs); 745 NewMemRefs[NewNum - 1] = MO; 746 747 MemRefs = NewMemRefs; 748 MemRefsEnd = NewMemRefsEnd; 749 } 750 751 bool MachineInstr::hasProperty(unsigned short MCFlag) const { 752 if (getOpcode() != TargetOpcode::BUNDLE) 753 return getDesc().getFlags() & (1 << MCFlag); 754 755 const MachineBasicBlock *MBB = getParent(); 756 MachineBasicBlock::const_insn_iterator MII = *this; ++MII; 757 while (MII != MBB->end() && MII->isInsideBundle()) { 758 if (MII->getDesc().getFlags() & (1 << MCFlag)) 759 return true; 760 ++MII; 761 } 762 return false; 763 } 764 765 bool MachineInstr::isIdenticalTo(const MachineInstr *Other, 766 MICheckType Check) const { 767 // If opcodes or number of operands are not the same then the two 768 // instructions are obviously not identical. 769 if (Other->getOpcode() != getOpcode() || 770 Other->getNumOperands() != getNumOperands()) 771 return false; 772 773 // Check operands to make sure they match. 774 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 775 const MachineOperand &MO = getOperand(i); 776 const MachineOperand &OMO = Other->getOperand(i); 777 if (!MO.isReg()) { 778 if (!MO.isIdenticalTo(OMO)) 779 return false; 780 continue; 781 } 782 783 // Clients may or may not want to ignore defs when testing for equality. 784 // For example, machine CSE pass only cares about finding common 785 // subexpressions, so it's safe to ignore virtual register defs. 786 if (MO.isDef()) { 787 if (Check == IgnoreDefs) 788 continue; 789 else if (Check == IgnoreVRegDefs) { 790 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) || 791 TargetRegisterInfo::isPhysicalRegister(OMO.getReg())) 792 if (MO.getReg() != OMO.getReg()) 793 return false; 794 } else { 795 if (!MO.isIdenticalTo(OMO)) 796 return false; 797 if (Check == CheckKillDead && MO.isDead() != OMO.isDead()) 798 return false; 799 } 800 } else { 801 if (!MO.isIdenticalTo(OMO)) 802 return false; 803 if (Check == CheckKillDead && MO.isKill() != OMO.isKill()) 804 return false; 805 } 806 } 807 // If DebugLoc does not match then two dbg.values are not identical. 808 if (isDebugValue()) 809 if (!getDebugLoc().isUnknown() && !Other->getDebugLoc().isUnknown() 810 && getDebugLoc() != Other->getDebugLoc()) 811 return false; 812 return true; 813 } 814 815 /// removeFromParent - This method unlinks 'this' from the containing basic 816 /// block, and returns it, but does not delete it. 817 MachineInstr *MachineInstr::removeFromParent() { 818 assert(getParent() && "Not embedded in a basic block!"); 819 820 // If it's a bundle then remove the MIs inside the bundle as well. 821 if (getOpcode() == TargetOpcode::BUNDLE) { 822 MachineBasicBlock *MBB = getParent(); 823 MachineBasicBlock::insn_iterator MII = *this; ++MII; 824 while (MII != MBB->end() && MII->isInsideBundle()) { 825 MachineInstr *MI = &*MII; 826 ++MII; 827 MBB->remove(MI); 828 } 829 } 830 getParent()->remove(this); 831 return this; 832 } 833 834 835 /// eraseFromParent - This method unlinks 'this' from the containing basic 836 /// block, and deletes it. 837 void MachineInstr::eraseFromParent() { 838 assert(getParent() && "Not embedded in a basic block!"); 839 // If it's a bundle then remove the MIs inside the bundle as well. 840 if (getOpcode() == TargetOpcode::BUNDLE) { 841 MachineBasicBlock *MBB = getParent(); 842 MachineBasicBlock::insn_iterator MII = *this; ++MII; 843 while (MII != MBB->end() && MII->isInsideBundle()) { 844 MachineInstr *MI = &*MII; 845 ++MII; 846 MBB->erase(MI); 847 } 848 } 849 getParent()->erase(this); 850 } 851 852 853 /// getNumExplicitOperands - Returns the number of non-implicit operands. 854 /// 855 unsigned MachineInstr::getNumExplicitOperands() const { 856 unsigned NumOperands = MCID->getNumOperands(); 857 if (!MCID->isVariadic()) 858 return NumOperands; 859 860 for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) { 861 const MachineOperand &MO = getOperand(i); 862 if (!MO.isReg() || !MO.isImplicit()) 863 NumOperands++; 864 } 865 return NumOperands; 866 } 867 868 bool MachineInstr::isStackAligningInlineAsm() const { 869 if (isInlineAsm()) { 870 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm(); 871 if (ExtraInfo & InlineAsm::Extra_IsAlignStack) 872 return true; 873 } 874 return false; 875 } 876 877 int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx, 878 unsigned *GroupNo) const { 879 assert(isInlineAsm() && "Expected an inline asm instruction"); 880 assert(OpIdx < getNumOperands() && "OpIdx out of range"); 881 882 // Ignore queries about the initial operands. 883 if (OpIdx < InlineAsm::MIOp_FirstOperand) 884 return -1; 885 886 unsigned Group = 0; 887 unsigned NumOps; 888 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e; 889 i += NumOps) { 890 const MachineOperand &FlagMO = getOperand(i); 891 // If we reach the implicit register operands, stop looking. 892 if (!FlagMO.isImm()) 893 return -1; 894 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm()); 895 if (i + NumOps > OpIdx) { 896 if (GroupNo) 897 *GroupNo = Group; 898 return i; 899 } 900 ++Group; 901 } 902 return -1; 903 } 904 905 const TargetRegisterClass* 906 MachineInstr::getRegClassConstraint(unsigned OpIdx, 907 const TargetInstrInfo *TII, 908 const TargetRegisterInfo *TRI) const { 909 // Most opcodes have fixed constraints in their MCInstrDesc. 910 if (!isInlineAsm()) 911 return TII->getRegClass(getDesc(), OpIdx, TRI); 912 913 if (!getOperand(OpIdx).isReg()) 914 return NULL; 915 916 // For tied uses on inline asm, get the constraint from the def. 917 unsigned DefIdx; 918 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx)) 919 OpIdx = DefIdx; 920 921 // Inline asm stores register class constraints in the flag word. 922 int FlagIdx = findInlineAsmFlagIdx(OpIdx); 923 if (FlagIdx < 0) 924 return NULL; 925 926 unsigned Flag = getOperand(FlagIdx).getImm(); 927 unsigned RCID; 928 if (InlineAsm::hasRegClassConstraint(Flag, RCID)) 929 return TRI->getRegClass(RCID); 930 931 // Assume that all registers in a memory operand are pointers. 932 if (InlineAsm::getKind(Flag) == InlineAsm::Kind_Mem) 933 return TRI->getPointerRegClass(); 934 935 return NULL; 936 } 937 938 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of 939 /// the specific register or -1 if it is not found. It further tightens 940 /// the search criteria to a use that kills the register if isKill is true. 941 int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill, 942 const TargetRegisterInfo *TRI) const { 943 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 944 const MachineOperand &MO = getOperand(i); 945 if (!MO.isReg() || !MO.isUse()) 946 continue; 947 unsigned MOReg = MO.getReg(); 948 if (!MOReg) 949 continue; 950 if (MOReg == Reg || 951 (TRI && 952 TargetRegisterInfo::isPhysicalRegister(MOReg) && 953 TargetRegisterInfo::isPhysicalRegister(Reg) && 954 TRI->isSubRegister(MOReg, Reg))) 955 if (!isKill || MO.isKill()) 956 return i; 957 } 958 return -1; 959 } 960 961 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes) 962 /// indicating if this instruction reads or writes Reg. This also considers 963 /// partial defines. 964 std::pair<bool,bool> 965 MachineInstr::readsWritesVirtualRegister(unsigned Reg, 966 SmallVectorImpl<unsigned> *Ops) const { 967 bool PartDef = false; // Partial redefine. 968 bool FullDef = false; // Full define. 969 bool Use = false; 970 971 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 972 const MachineOperand &MO = getOperand(i); 973 if (!MO.isReg() || MO.getReg() != Reg) 974 continue; 975 if (Ops) 976 Ops->push_back(i); 977 if (MO.isUse()) 978 Use |= !MO.isUndef(); 979 else if (MO.getSubReg() && !MO.isUndef()) 980 // A partial <def,undef> doesn't count as reading the register. 981 PartDef = true; 982 else 983 FullDef = true; 984 } 985 // A partial redefine uses Reg unless there is also a full define. 986 return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef); 987 } 988 989 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of 990 /// the specified register or -1 if it is not found. If isDead is true, defs 991 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it 992 /// also checks if there is a def of a super-register. 993 int 994 MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap, 995 const TargetRegisterInfo *TRI) const { 996 bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg); 997 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 998 const MachineOperand &MO = getOperand(i); 999 if (!MO.isReg() || !MO.isDef()) 1000 continue; 1001 unsigned MOReg = MO.getReg(); 1002 bool Found = (MOReg == Reg); 1003 if (!Found && TRI && isPhys && 1004 TargetRegisterInfo::isPhysicalRegister(MOReg)) { 1005 if (Overlap) 1006 Found = TRI->regsOverlap(MOReg, Reg); 1007 else 1008 Found = TRI->isSubRegister(MOReg, Reg); 1009 } 1010 if (Found && (!isDead || MO.isDead())) 1011 return i; 1012 } 1013 return -1; 1014 } 1015 1016 /// findFirstPredOperandIdx() - Find the index of the first operand in the 1017 /// operand list that is used to represent the predicate. It returns -1 if 1018 /// none is found. 1019 int MachineInstr::findFirstPredOperandIdx() const { 1020 // Don't call MCID.findFirstPredOperandIdx() because this variant 1021 // is sometimes called on an instruction that's not yet complete, and 1022 // so the number of operands is less than the MCID indicates. In 1023 // particular, the PTX target does this. 1024 const MCInstrDesc &MCID = getDesc(); 1025 if (MCID.isPredicable()) { 1026 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) 1027 if (MCID.OpInfo[i].isPredicate()) 1028 return i; 1029 } 1030 1031 return -1; 1032 } 1033 1034 /// isRegTiedToUseOperand - Given the index of a register def operand, 1035 /// check if the register def is tied to a source operand, due to either 1036 /// two-address elimination or inline assembly constraints. Returns the 1037 /// first tied use operand index by reference is UseOpIdx is not null. 1038 bool MachineInstr:: 1039 isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx) const { 1040 if (isInlineAsm()) { 1041 assert(DefOpIdx > InlineAsm::MIOp_FirstOperand); 1042 const MachineOperand &MO = getOperand(DefOpIdx); 1043 if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0) 1044 return false; 1045 // Determine the actual operand index that corresponds to this index. 1046 unsigned DefNo = 0; 1047 int FlagIdx = findInlineAsmFlagIdx(DefOpIdx, &DefNo); 1048 if (FlagIdx < 0) 1049 return false; 1050 1051 // Which part of the group is DefOpIdx? 1052 unsigned DefPart = DefOpIdx - (FlagIdx + 1); 1053 1054 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); 1055 i != e; ++i) { 1056 const MachineOperand &FMO = getOperand(i); 1057 if (!FMO.isImm()) 1058 continue; 1059 if (i+1 >= e || !getOperand(i+1).isReg() || !getOperand(i+1).isUse()) 1060 continue; 1061 unsigned Idx; 1062 if (InlineAsm::isUseOperandTiedToDef(FMO.getImm(), Idx) && 1063 Idx == DefNo) { 1064 if (UseOpIdx) 1065 *UseOpIdx = (unsigned)i + 1 + DefPart; 1066 return true; 1067 } 1068 } 1069 return false; 1070 } 1071 1072 assert(getOperand(DefOpIdx).isDef() && "DefOpIdx is not a def!"); 1073 const MCInstrDesc &MCID = getDesc(); 1074 for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i) { 1075 const MachineOperand &MO = getOperand(i); 1076 if (MO.isReg() && MO.isUse() && 1077 MCID.getOperandConstraint(i, MCOI::TIED_TO) == (int)DefOpIdx) { 1078 if (UseOpIdx) 1079 *UseOpIdx = (unsigned)i; 1080 return true; 1081 } 1082 } 1083 return false; 1084 } 1085 1086 /// isRegTiedToDefOperand - Return true if the operand of the specified index 1087 /// is a register use and it is tied to an def operand. It also returns the def 1088 /// operand index by reference. 1089 bool MachineInstr:: 1090 isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx) const { 1091 if (isInlineAsm()) { 1092 const MachineOperand &MO = getOperand(UseOpIdx); 1093 if (!MO.isReg() || !MO.isUse() || MO.getReg() == 0) 1094 return false; 1095 1096 // Find the flag operand corresponding to UseOpIdx 1097 int FlagIdx = findInlineAsmFlagIdx(UseOpIdx); 1098 if (FlagIdx < 0) 1099 return false; 1100 1101 const MachineOperand &UFMO = getOperand(FlagIdx); 1102 unsigned DefNo; 1103 if (InlineAsm::isUseOperandTiedToDef(UFMO.getImm(), DefNo)) { 1104 if (!DefOpIdx) 1105 return true; 1106 1107 unsigned DefIdx = InlineAsm::MIOp_FirstOperand; 1108 // Remember to adjust the index. First operand is asm string, second is 1109 // the HasSideEffects and AlignStack bits, then there is a flag for each. 1110 while (DefNo) { 1111 const MachineOperand &FMO = getOperand(DefIdx); 1112 assert(FMO.isImm()); 1113 // Skip over this def. 1114 DefIdx += InlineAsm::getNumOperandRegisters(FMO.getImm()) + 1; 1115 --DefNo; 1116 } 1117 *DefOpIdx = DefIdx + UseOpIdx - FlagIdx; 1118 return true; 1119 } 1120 return false; 1121 } 1122 1123 const MCInstrDesc &MCID = getDesc(); 1124 if (UseOpIdx >= MCID.getNumOperands()) 1125 return false; 1126 const MachineOperand &MO = getOperand(UseOpIdx); 1127 if (!MO.isReg() || !MO.isUse()) 1128 return false; 1129 int DefIdx = MCID.getOperandConstraint(UseOpIdx, MCOI::TIED_TO); 1130 if (DefIdx == -1) 1131 return false; 1132 if (DefOpIdx) 1133 *DefOpIdx = (unsigned)DefIdx; 1134 return true; 1135 } 1136 1137 /// clearKillInfo - Clears kill flags on all operands. 1138 /// 1139 void MachineInstr::clearKillInfo() { 1140 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1141 MachineOperand &MO = getOperand(i); 1142 if (MO.isReg() && MO.isUse()) 1143 MO.setIsKill(false); 1144 } 1145 } 1146 1147 /// copyKillDeadInfo - Copies kill / dead operand properties from MI. 1148 /// 1149 void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) { 1150 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 1151 const MachineOperand &MO = MI->getOperand(i); 1152 if (!MO.isReg() || (!MO.isKill() && !MO.isDead())) 1153 continue; 1154 for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) { 1155 MachineOperand &MOp = getOperand(j); 1156 if (!MOp.isIdenticalTo(MO)) 1157 continue; 1158 if (MO.isKill()) 1159 MOp.setIsKill(); 1160 else 1161 MOp.setIsDead(); 1162 break; 1163 } 1164 } 1165 } 1166 1167 /// copyPredicates - Copies predicate operand(s) from MI. 1168 void MachineInstr::copyPredicates(const MachineInstr *MI) { 1169 const MCInstrDesc &MCID = MI->getDesc(); 1170 if (!MCID.isPredicable()) 1171 return; 1172 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 1173 if (MCID.OpInfo[i].isPredicate()) { 1174 // Predicated operands must be last operands. 1175 addOperand(MI->getOperand(i)); 1176 } 1177 } 1178 } 1179 1180 void MachineInstr::substituteRegister(unsigned FromReg, 1181 unsigned ToReg, 1182 unsigned SubIdx, 1183 const TargetRegisterInfo &RegInfo) { 1184 if (TargetRegisterInfo::isPhysicalRegister(ToReg)) { 1185 if (SubIdx) 1186 ToReg = RegInfo.getSubReg(ToReg, SubIdx); 1187 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1188 MachineOperand &MO = getOperand(i); 1189 if (!MO.isReg() || MO.getReg() != FromReg) 1190 continue; 1191 MO.substPhysReg(ToReg, RegInfo); 1192 } 1193 } else { 1194 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1195 MachineOperand &MO = getOperand(i); 1196 if (!MO.isReg() || MO.getReg() != FromReg) 1197 continue; 1198 MO.substVirtReg(ToReg, SubIdx, RegInfo); 1199 } 1200 } 1201 } 1202 1203 /// isSafeToMove - Return true if it is safe to move this instruction. If 1204 /// SawStore is set to true, it means that there is a store (or call) between 1205 /// the instruction's location and its intended destination. 1206 bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII, 1207 AliasAnalysis *AA, 1208 bool &SawStore) const { 1209 // Ignore stuff that we obviously can't move. 1210 if (MCID->mayStore() || MCID->isCall()) { 1211 SawStore = true; 1212 return false; 1213 } 1214 1215 if (isLabel() || isDebugValue() || 1216 MCID->isTerminator() || hasUnmodeledSideEffects()) 1217 return false; 1218 1219 // See if this instruction does a load. If so, we have to guarantee that the 1220 // loaded value doesn't change between the load and the its intended 1221 // destination. The check for isInvariantLoad gives the targe the chance to 1222 // classify the load as always returning a constant, e.g. a constant pool 1223 // load. 1224 if (MCID->mayLoad() && !isInvariantLoad(AA)) 1225 // Otherwise, this is a real load. If there is a store between the load and 1226 // end of block, or if the load is volatile, we can't move it. 1227 return !SawStore && !hasVolatileMemoryRef(); 1228 1229 return true; 1230 } 1231 1232 /// isSafeToReMat - Return true if it's safe to rematerialize the specified 1233 /// instruction which defined the specified register instead of copying it. 1234 bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII, 1235 AliasAnalysis *AA, 1236 unsigned DstReg) const { 1237 bool SawStore = false; 1238 if (!TII->isTriviallyReMaterializable(this, AA) || 1239 !isSafeToMove(TII, AA, SawStore)) 1240 return false; 1241 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1242 const MachineOperand &MO = getOperand(i); 1243 if (!MO.isReg()) 1244 continue; 1245 // FIXME: For now, do not remat any instruction with register operands. 1246 // Later on, we can loosen the restriction is the register operands have 1247 // not been modified between the def and use. Note, this is different from 1248 // MachineSink because the code is no longer in two-address form (at least 1249 // partially). 1250 if (MO.isUse()) 1251 return false; 1252 else if (!MO.isDead() && MO.getReg() != DstReg) 1253 return false; 1254 } 1255 return true; 1256 } 1257 1258 /// hasVolatileMemoryRef - Return true if this instruction may have a 1259 /// volatile memory reference, or if the information describing the 1260 /// memory reference is not available. Return false if it is known to 1261 /// have no volatile memory references. 1262 bool MachineInstr::hasVolatileMemoryRef() const { 1263 // An instruction known never to access memory won't have a volatile access. 1264 if (!MCID->mayStore() && 1265 !MCID->mayLoad() && 1266 !MCID->isCall() && 1267 !hasUnmodeledSideEffects()) 1268 return false; 1269 1270 // Otherwise, if the instruction has no memory reference information, 1271 // conservatively assume it wasn't preserved. 1272 if (memoperands_empty()) 1273 return true; 1274 1275 // Check the memory reference information for volatile references. 1276 for (mmo_iterator I = memoperands_begin(), E = memoperands_end(); I != E; ++I) 1277 if ((*I)->isVolatile()) 1278 return true; 1279 1280 return false; 1281 } 1282 1283 /// isInvariantLoad - Return true if this instruction is loading from a 1284 /// location whose value is invariant across the function. For example, 1285 /// loading a value from the constant pool or from the argument area 1286 /// of a function if it does not change. This should only return true of 1287 /// *all* loads the instruction does are invariant (if it does multiple loads). 1288 bool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const { 1289 // If the instruction doesn't load at all, it isn't an invariant load. 1290 if (!MCID->mayLoad()) 1291 return false; 1292 1293 // If the instruction has lost its memoperands, conservatively assume that 1294 // it may not be an invariant load. 1295 if (memoperands_empty()) 1296 return false; 1297 1298 const MachineFrameInfo *MFI = getParent()->getParent()->getFrameInfo(); 1299 1300 for (mmo_iterator I = memoperands_begin(), 1301 E = memoperands_end(); I != E; ++I) { 1302 if ((*I)->isVolatile()) return false; 1303 if ((*I)->isStore()) return false; 1304 if ((*I)->isInvariant()) return true; 1305 1306 if (const Value *V = (*I)->getValue()) { 1307 // A load from a constant PseudoSourceValue is invariant. 1308 if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V)) 1309 if (PSV->isConstant(MFI)) 1310 continue; 1311 // If we have an AliasAnalysis, ask it whether the memory is constant. 1312 if (AA && AA->pointsToConstantMemory( 1313 AliasAnalysis::Location(V, (*I)->getSize(), 1314 (*I)->getTBAAInfo()))) 1315 continue; 1316 } 1317 1318 // Otherwise assume conservatively. 1319 return false; 1320 } 1321 1322 // Everything checks out. 1323 return true; 1324 } 1325 1326 /// isConstantValuePHI - If the specified instruction is a PHI that always 1327 /// merges together the same virtual register, return the register, otherwise 1328 /// return 0. 1329 unsigned MachineInstr::isConstantValuePHI() const { 1330 if (!isPHI()) 1331 return 0; 1332 assert(getNumOperands() >= 3 && 1333 "It's illegal to have a PHI without source operands"); 1334 1335 unsigned Reg = getOperand(1).getReg(); 1336 for (unsigned i = 3, e = getNumOperands(); i < e; i += 2) 1337 if (getOperand(i).getReg() != Reg) 1338 return 0; 1339 return Reg; 1340 } 1341 1342 bool MachineInstr::hasUnmodeledSideEffects() const { 1343 if (getDesc().hasUnmodeledSideEffects()) 1344 return true; 1345 if (isInlineAsm()) { 1346 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm(); 1347 if (ExtraInfo & InlineAsm::Extra_HasSideEffects) 1348 return true; 1349 } 1350 1351 return false; 1352 } 1353 1354 /// allDefsAreDead - Return true if all the defs of this instruction are dead. 1355 /// 1356 bool MachineInstr::allDefsAreDead() const { 1357 for (unsigned i = 0, e = getNumOperands(); i < e; ++i) { 1358 const MachineOperand &MO = getOperand(i); 1359 if (!MO.isReg() || MO.isUse()) 1360 continue; 1361 if (!MO.isDead()) 1362 return false; 1363 } 1364 return true; 1365 } 1366 1367 /// copyImplicitOps - Copy implicit register operands from specified 1368 /// instruction to this instruction. 1369 void MachineInstr::copyImplicitOps(const MachineInstr *MI) { 1370 for (unsigned i = MI->getDesc().getNumOperands(), e = MI->getNumOperands(); 1371 i != e; ++i) { 1372 const MachineOperand &MO = MI->getOperand(i); 1373 if (MO.isReg() && MO.isImplicit()) 1374 addOperand(MO); 1375 } 1376 } 1377 1378 void MachineInstr::dump() const { 1379 dbgs() << " " << *this; 1380 } 1381 1382 static void printDebugLoc(DebugLoc DL, const MachineFunction *MF, 1383 raw_ostream &CommentOS) { 1384 const LLVMContext &Ctx = MF->getFunction()->getContext(); 1385 if (!DL.isUnknown()) { // Print source line info. 1386 DIScope Scope(DL.getScope(Ctx)); 1387 // Omit the directory, because it's likely to be long and uninteresting. 1388 if (Scope.Verify()) 1389 CommentOS << Scope.getFilename(); 1390 else 1391 CommentOS << "<unknown>"; 1392 CommentOS << ':' << DL.getLine(); 1393 if (DL.getCol() != 0) 1394 CommentOS << ':' << DL.getCol(); 1395 DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(DL.getInlinedAt(Ctx)); 1396 if (!InlinedAtDL.isUnknown()) { 1397 CommentOS << " @[ "; 1398 printDebugLoc(InlinedAtDL, MF, CommentOS); 1399 CommentOS << " ]"; 1400 } 1401 } 1402 } 1403 1404 void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const { 1405 // We can be a bit tidier if we know the TargetMachine and/or MachineFunction. 1406 const MachineFunction *MF = 0; 1407 const MachineRegisterInfo *MRI = 0; 1408 if (const MachineBasicBlock *MBB = getParent()) { 1409 MF = MBB->getParent(); 1410 if (!TM && MF) 1411 TM = &MF->getTarget(); 1412 if (MF) 1413 MRI = &MF->getRegInfo(); 1414 } 1415 1416 // Save a list of virtual registers. 1417 SmallVector<unsigned, 8> VirtRegs; 1418 1419 // Print explicitly defined operands on the left of an assignment syntax. 1420 unsigned StartOp = 0, e = getNumOperands(); 1421 for (; StartOp < e && getOperand(StartOp).isReg() && 1422 getOperand(StartOp).isDef() && 1423 !getOperand(StartOp).isImplicit(); 1424 ++StartOp) { 1425 if (StartOp != 0) OS << ", "; 1426 getOperand(StartOp).print(OS, TM); 1427 unsigned Reg = getOperand(StartOp).getReg(); 1428 if (TargetRegisterInfo::isVirtualRegister(Reg)) 1429 VirtRegs.push_back(Reg); 1430 } 1431 1432 if (StartOp != 0) 1433 OS << " = "; 1434 1435 // Print the opcode name. 1436 OS << getDesc().getName(); 1437 1438 // Print the rest of the operands. 1439 bool OmittedAnyCallClobbers = false; 1440 bool FirstOp = true; 1441 unsigned AsmDescOp = ~0u; 1442 unsigned AsmOpCount = 0; 1443 1444 if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) { 1445 // Print asm string. 1446 OS << " "; 1447 getOperand(InlineAsm::MIOp_AsmString).print(OS, TM); 1448 1449 // Print HasSideEffects, IsAlignStack 1450 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm(); 1451 if (ExtraInfo & InlineAsm::Extra_HasSideEffects) 1452 OS << " [sideeffect]"; 1453 if (ExtraInfo & InlineAsm::Extra_IsAlignStack) 1454 OS << " [alignstack]"; 1455 1456 StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand; 1457 FirstOp = false; 1458 } 1459 1460 1461 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) { 1462 const MachineOperand &MO = getOperand(i); 1463 1464 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) 1465 VirtRegs.push_back(MO.getReg()); 1466 1467 // Omit call-clobbered registers which aren't used anywhere. This makes 1468 // call instructions much less noisy on targets where calls clobber lots 1469 // of registers. Don't rely on MO.isDead() because we may be called before 1470 // LiveVariables is run, or we may be looking at a non-allocatable reg. 1471 if (MF && getDesc().isCall() && 1472 MO.isReg() && MO.isImplicit() && MO.isDef()) { 1473 unsigned Reg = MO.getReg(); 1474 if (TargetRegisterInfo::isPhysicalRegister(Reg)) { 1475 const MachineRegisterInfo &MRI = MF->getRegInfo(); 1476 if (MRI.use_empty(Reg) && !MRI.isLiveOut(Reg)) { 1477 bool HasAliasLive = false; 1478 for (const unsigned *Alias = TM->getRegisterInfo()->getAliasSet(Reg); 1479 unsigned AliasReg = *Alias; ++Alias) 1480 if (!MRI.use_empty(AliasReg) || MRI.isLiveOut(AliasReg)) { 1481 HasAliasLive = true; 1482 break; 1483 } 1484 if (!HasAliasLive) { 1485 OmittedAnyCallClobbers = true; 1486 continue; 1487 } 1488 } 1489 } 1490 } 1491 1492 if (FirstOp) FirstOp = false; else OS << ","; 1493 OS << " "; 1494 if (i < getDesc().NumOperands) { 1495 const MCOperandInfo &MCOI = getDesc().OpInfo[i]; 1496 if (MCOI.isPredicate()) 1497 OS << "pred:"; 1498 if (MCOI.isOptionalDef()) 1499 OS << "opt:"; 1500 } 1501 if (isDebugValue() && MO.isMetadata()) { 1502 // Pretty print DBG_VALUE instructions. 1503 const MDNode *MD = MO.getMetadata(); 1504 if (const MDString *MDS = dyn_cast<MDString>(MD->getOperand(2))) 1505 OS << "!\"" << MDS->getString() << '\"'; 1506 else 1507 MO.print(OS, TM); 1508 } else if (TM && (isInsertSubreg() || isRegSequence()) && MO.isImm()) { 1509 OS << TM->getRegisterInfo()->getSubRegIndexName(MO.getImm()); 1510 } else if (i == AsmDescOp && MO.isImm()) { 1511 // Pretty print the inline asm operand descriptor. 1512 OS << '$' << AsmOpCount++; 1513 unsigned Flag = MO.getImm(); 1514 switch (InlineAsm::getKind(Flag)) { 1515 case InlineAsm::Kind_RegUse: OS << ":[reguse"; break; 1516 case InlineAsm::Kind_RegDef: OS << ":[regdef"; break; 1517 case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec"; break; 1518 case InlineAsm::Kind_Clobber: OS << ":[clobber"; break; 1519 case InlineAsm::Kind_Imm: OS << ":[imm"; break; 1520 case InlineAsm::Kind_Mem: OS << ":[mem"; break; 1521 default: OS << ":[??" << InlineAsm::getKind(Flag); break; 1522 } 1523 1524 unsigned RCID = 0; 1525 if (InlineAsm::hasRegClassConstraint(Flag, RCID)) { 1526 if (TM) 1527 OS << ':' << TM->getRegisterInfo()->getRegClass(RCID)->getName(); 1528 else 1529 OS << ":RC" << RCID; 1530 } 1531 1532 unsigned TiedTo = 0; 1533 if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo)) 1534 OS << " tiedto:$" << TiedTo; 1535 1536 OS << ']'; 1537 1538 // Compute the index of the next operand descriptor. 1539 AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag); 1540 } else 1541 MO.print(OS, TM); 1542 } 1543 1544 // Briefly indicate whether any call clobbers were omitted. 1545 if (OmittedAnyCallClobbers) { 1546 if (!FirstOp) OS << ","; 1547 OS << " ..."; 1548 } 1549 1550 bool HaveSemi = false; 1551 if (Flags) { 1552 if (!HaveSemi) OS << ";"; HaveSemi = true; 1553 OS << " flags: "; 1554 1555 if (Flags & FrameSetup) 1556 OS << "FrameSetup"; 1557 } 1558 1559 if (!memoperands_empty()) { 1560 if (!HaveSemi) OS << ";"; HaveSemi = true; 1561 1562 OS << " mem:"; 1563 for (mmo_iterator i = memoperands_begin(), e = memoperands_end(); 1564 i != e; ++i) { 1565 OS << **i; 1566 if (llvm::next(i) != e) 1567 OS << " "; 1568 } 1569 } 1570 1571 // Print the regclass of any virtual registers encountered. 1572 if (MRI && !VirtRegs.empty()) { 1573 if (!HaveSemi) OS << ";"; HaveSemi = true; 1574 for (unsigned i = 0; i != VirtRegs.size(); ++i) { 1575 const TargetRegisterClass *RC = MRI->getRegClass(VirtRegs[i]); 1576 OS << " " << RC->getName() << ':' << PrintReg(VirtRegs[i]); 1577 for (unsigned j = i+1; j != VirtRegs.size();) { 1578 if (MRI->getRegClass(VirtRegs[j]) != RC) { 1579 ++j; 1580 continue; 1581 } 1582 if (VirtRegs[i] != VirtRegs[j]) 1583 OS << "," << PrintReg(VirtRegs[j]); 1584 VirtRegs.erase(VirtRegs.begin()+j); 1585 } 1586 } 1587 } 1588 1589 // Print debug location information. 1590 if (isDebugValue() && getOperand(e - 1).isMetadata()) { 1591 if (!HaveSemi) OS << ";"; HaveSemi = true; 1592 DIVariable DV(getOperand(e - 1).getMetadata()); 1593 OS << " line no:" << DV.getLineNumber(); 1594 if (MDNode *InlinedAt = DV.getInlinedAt()) { 1595 DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(InlinedAt); 1596 if (!InlinedAtDL.isUnknown()) { 1597 OS << " inlined @[ "; 1598 printDebugLoc(InlinedAtDL, MF, OS); 1599 OS << " ]"; 1600 } 1601 } 1602 } else if (!debugLoc.isUnknown() && MF) { 1603 if (!HaveSemi) OS << ";"; HaveSemi = true; 1604 OS << " dbg:"; 1605 printDebugLoc(debugLoc, MF, OS); 1606 } 1607 1608 OS << '\n'; 1609 } 1610 1611 bool MachineInstr::addRegisterKilled(unsigned IncomingReg, 1612 const TargetRegisterInfo *RegInfo, 1613 bool AddIfNotFound) { 1614 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg); 1615 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg); 1616 bool Found = false; 1617 SmallVector<unsigned,4> DeadOps; 1618 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1619 MachineOperand &MO = getOperand(i); 1620 if (!MO.isReg() || !MO.isUse() || MO.isUndef()) 1621 continue; 1622 unsigned Reg = MO.getReg(); 1623 if (!Reg) 1624 continue; 1625 1626 if (Reg == IncomingReg) { 1627 if (!Found) { 1628 if (MO.isKill()) 1629 // The register is already marked kill. 1630 return true; 1631 if (isPhysReg && isRegTiedToDefOperand(i)) 1632 // Two-address uses of physregs must not be marked kill. 1633 return true; 1634 MO.setIsKill(); 1635 Found = true; 1636 } 1637 } else if (hasAliases && MO.isKill() && 1638 TargetRegisterInfo::isPhysicalRegister(Reg)) { 1639 // A super-register kill already exists. 1640 if (RegInfo->isSuperRegister(IncomingReg, Reg)) 1641 return true; 1642 if (RegInfo->isSubRegister(IncomingReg, Reg)) 1643 DeadOps.push_back(i); 1644 } 1645 } 1646 1647 // Trim unneeded kill operands. 1648 while (!DeadOps.empty()) { 1649 unsigned OpIdx = DeadOps.back(); 1650 if (getOperand(OpIdx).isImplicit()) 1651 RemoveOperand(OpIdx); 1652 else 1653 getOperand(OpIdx).setIsKill(false); 1654 DeadOps.pop_back(); 1655 } 1656 1657 // If not found, this means an alias of one of the operands is killed. Add a 1658 // new implicit operand if required. 1659 if (!Found && AddIfNotFound) { 1660 addOperand(MachineOperand::CreateReg(IncomingReg, 1661 false /*IsDef*/, 1662 true /*IsImp*/, 1663 true /*IsKill*/)); 1664 return true; 1665 } 1666 return Found; 1667 } 1668 1669 bool MachineInstr::addRegisterDead(unsigned IncomingReg, 1670 const TargetRegisterInfo *RegInfo, 1671 bool AddIfNotFound) { 1672 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg); 1673 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg); 1674 bool Found = false; 1675 SmallVector<unsigned,4> DeadOps; 1676 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1677 MachineOperand &MO = getOperand(i); 1678 if (!MO.isReg() || !MO.isDef()) 1679 continue; 1680 unsigned Reg = MO.getReg(); 1681 if (!Reg) 1682 continue; 1683 1684 if (Reg == IncomingReg) { 1685 MO.setIsDead(); 1686 Found = true; 1687 } else if (hasAliases && MO.isDead() && 1688 TargetRegisterInfo::isPhysicalRegister(Reg)) { 1689 // There exists a super-register that's marked dead. 1690 if (RegInfo->isSuperRegister(IncomingReg, Reg)) 1691 return true; 1692 if (RegInfo->getSubRegisters(IncomingReg) && 1693 RegInfo->getSuperRegisters(Reg) && 1694 RegInfo->isSubRegister(IncomingReg, Reg)) 1695 DeadOps.push_back(i); 1696 } 1697 } 1698 1699 // Trim unneeded dead operands. 1700 while (!DeadOps.empty()) { 1701 unsigned OpIdx = DeadOps.back(); 1702 if (getOperand(OpIdx).isImplicit()) 1703 RemoveOperand(OpIdx); 1704 else 1705 getOperand(OpIdx).setIsDead(false); 1706 DeadOps.pop_back(); 1707 } 1708 1709 // If not found, this means an alias of one of the operands is dead. Add a 1710 // new implicit operand if required. 1711 if (Found || !AddIfNotFound) 1712 return Found; 1713 1714 addOperand(MachineOperand::CreateReg(IncomingReg, 1715 true /*IsDef*/, 1716 true /*IsImp*/, 1717 false /*IsKill*/, 1718 true /*IsDead*/)); 1719 return true; 1720 } 1721 1722 void MachineInstr::addRegisterDefined(unsigned IncomingReg, 1723 const TargetRegisterInfo *RegInfo) { 1724 if (TargetRegisterInfo::isPhysicalRegister(IncomingReg)) { 1725 MachineOperand *MO = findRegisterDefOperand(IncomingReg, false, RegInfo); 1726 if (MO) 1727 return; 1728 } else { 1729 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1730 const MachineOperand &MO = getOperand(i); 1731 if (MO.isReg() && MO.getReg() == IncomingReg && MO.isDef() && 1732 MO.getSubReg() == 0) 1733 return; 1734 } 1735 } 1736 addOperand(MachineOperand::CreateReg(IncomingReg, 1737 true /*IsDef*/, 1738 true /*IsImp*/)); 1739 } 1740 1741 void MachineInstr::setPhysRegsDeadExcept(const SmallVectorImpl<unsigned> &UsedRegs, 1742 const TargetRegisterInfo &TRI) { 1743 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1744 MachineOperand &MO = getOperand(i); 1745 if (!MO.isReg() || !MO.isDef()) continue; 1746 unsigned Reg = MO.getReg(); 1747 if (Reg == 0) continue; 1748 bool Dead = true; 1749 for (SmallVectorImpl<unsigned>::const_iterator I = UsedRegs.begin(), 1750 E = UsedRegs.end(); I != E; ++I) 1751 if (TRI.regsOverlap(*I, Reg)) { 1752 Dead = false; 1753 break; 1754 } 1755 // If there are no uses, including partial uses, the def is dead. 1756 if (Dead) MO.setIsDead(); 1757 } 1758 } 1759 1760 unsigned 1761 MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) { 1762 unsigned Hash = MI->getOpcode() * 37; 1763 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 1764 const MachineOperand &MO = MI->getOperand(i); 1765 uint64_t Key = (uint64_t)MO.getType() << 32; 1766 switch (MO.getType()) { 1767 default: break; 1768 case MachineOperand::MO_Register: 1769 if (MO.isDef() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) 1770 continue; // Skip virtual register defs. 1771 Key |= MO.getReg(); 1772 break; 1773 case MachineOperand::MO_Immediate: 1774 Key |= MO.getImm(); 1775 break; 1776 case MachineOperand::MO_FrameIndex: 1777 case MachineOperand::MO_ConstantPoolIndex: 1778 case MachineOperand::MO_JumpTableIndex: 1779 Key |= MO.getIndex(); 1780 break; 1781 case MachineOperand::MO_MachineBasicBlock: 1782 Key |= DenseMapInfo<void*>::getHashValue(MO.getMBB()); 1783 break; 1784 case MachineOperand::MO_GlobalAddress: 1785 Key |= DenseMapInfo<void*>::getHashValue(MO.getGlobal()); 1786 break; 1787 case MachineOperand::MO_BlockAddress: 1788 Key |= DenseMapInfo<void*>::getHashValue(MO.getBlockAddress()); 1789 break; 1790 case MachineOperand::MO_MCSymbol: 1791 Key |= DenseMapInfo<void*>::getHashValue(MO.getMCSymbol()); 1792 break; 1793 } 1794 Key += ~(Key << 32); 1795 Key ^= (Key >> 22); 1796 Key += ~(Key << 13); 1797 Key ^= (Key >> 8); 1798 Key += (Key << 3); 1799 Key ^= (Key >> 15); 1800 Key += ~(Key << 27); 1801 Key ^= (Key >> 31); 1802 Hash = (unsigned)Key + Hash * 37; 1803 } 1804 return Hash; 1805 } 1806 1807 void MachineInstr::emitError(StringRef Msg) const { 1808 // Find the source location cookie. 1809 unsigned LocCookie = 0; 1810 const MDNode *LocMD = 0; 1811 for (unsigned i = getNumOperands(); i != 0; --i) { 1812 if (getOperand(i-1).isMetadata() && 1813 (LocMD = getOperand(i-1).getMetadata()) && 1814 LocMD->getNumOperands() != 0) { 1815 if (const ConstantInt *CI = dyn_cast<ConstantInt>(LocMD->getOperand(0))) { 1816 LocCookie = CI->getZExtValue(); 1817 break; 1818 } 1819 } 1820 } 1821 1822 if (const MachineBasicBlock *MBB = getParent()) 1823 if (const MachineFunction *MF = MBB->getParent()) 1824 return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg); 1825 report_fatal_error(Msg); 1826 } 1827