1 // $Id$ 2 //*************************************************************************** 3 // File: 4 // MachineInstr.cpp 5 // 6 // Purpose: 7 // 8 // 9 // Strategy: 10 // 11 // History: 12 // 7/2/01 - Vikram Adve - Created 13 //**************************************************************************/ 14 15 #include "llvm/CodeGen/MachineInstr.h" 16 #include "llvm/ConstPoolVals.h" 17 #include "llvm/Instruction.h" 18 #include <strstream> 19 20 //************************ Class Implementations **************************/ 21 22 // Constructor for instructions with fixed #operands (nearly all) 23 MachineInstr::MachineInstr(MachineOpCode _opCode, 24 OpCodeMask _opCodeMask) 25 : opCode(_opCode), 26 opCodeMask(_opCodeMask), 27 operands(TargetInstrDescriptors[_opCode].numOperands) 28 { 29 assert(TargetInstrDescriptors[_opCode].numOperands >= 0); 30 } 31 32 // Constructor for instructions with variable #operands 33 MachineInstr::MachineInstr(MachineOpCode _opCode, 34 unsigned numOperands, 35 OpCodeMask _opCodeMask) 36 : opCode(_opCode), 37 opCodeMask(_opCodeMask), 38 operands(numOperands) 39 { 40 } 41 42 void 43 MachineInstr::SetMachineOperand(unsigned int i, 44 MachineOperand::MachineOperandType operandType, 45 Value* _val, bool isdef=false) 46 { 47 assert(i < operands.size()); 48 operands[i].Initialize(operandType, _val); 49 operands[i].isDef = isdef || 50 TargetInstrDescriptors[opCode].resultPos == (int) i; 51 } 52 53 void 54 MachineInstr::SetMachineOperand(unsigned int i, 55 MachineOperand::MachineOperandType operandType, 56 int64_t intValue, bool isdef=false) 57 { 58 assert(i < operands.size()); 59 operands[i].InitializeConst(operandType, intValue); 60 operands[i].isDef = isdef || 61 TargetInstrDescriptors[opCode].resultPos == (int) i; 62 } 63 64 void 65 MachineInstr::SetMachineOperand(unsigned int i, 66 unsigned int regNum, bool isdef=false) 67 { 68 assert(i < operands.size()); 69 operands[i].InitializeReg(regNum); 70 operands[i].isDef = isdef || 71 TargetInstrDescriptors[opCode].resultPos == (int) i; 72 } 73 74 void 75 MachineInstr::dump(unsigned int indent) const 76 { 77 for (unsigned i=0; i < indent; i++) 78 cout << " "; 79 80 cout << *this; 81 } 82 83 ostream& 84 operator<< (ostream& os, const MachineInstr& minstr) 85 { 86 os << TargetInstrDescriptors[minstr.opCode].opCodeString; 87 88 for (unsigned i=0, N=minstr.getNumOperands(); i < N; i++) 89 os << "\t" << minstr.getOperand(i); 90 91 #undef DEBUG_VAL_OP_ITERATOR 92 #ifdef DEBUG_VAL_OP_ITERATOR 93 os << endl << "\tValue operands are: "; 94 for (MachineInstr::val_op_const_iterator vo(&minstr); ! vo.done(); ++vo) 95 { 96 const Value* val = *vo; 97 os << val << (vo.isDef()? "(def), " : ", "); 98 } 99 os << endl; 100 #endif 101 102 return os; 103 } 104 105 ostream& 106 operator<< (ostream& os, const MachineOperand& mop) 107 { 108 strstream regInfo; 109 if (mop.opType == MachineOperand::MO_VirtualRegister) 110 regInfo << "(val " << mop.value << ")" << ends; 111 else if (mop.opType == MachineOperand::MO_MachineRegister) 112 regInfo << "(" << mop.regNum << ")" << ends; 113 else if (mop.opType == MachineOperand::MO_CCRegister) 114 regInfo << "(val " << mop.value << ")" << ends; 115 116 switch(mop.opType) 117 { 118 case MachineOperand::MO_VirtualRegister: 119 case MachineOperand::MO_MachineRegister: 120 os << "%reg" << regInfo.str(); 121 free(regInfo.str()); 122 break; 123 124 case MachineOperand::MO_CCRegister: 125 os << "%ccreg" << regInfo.str(); 126 free(regInfo.str()); 127 break; 128 129 case MachineOperand::MO_SignExtendedImmed: 130 os << mop.immedVal; 131 break; 132 133 case MachineOperand::MO_UnextendedImmed: 134 os << mop.immedVal; 135 break; 136 137 case MachineOperand::MO_PCRelativeDisp: 138 os << "%disp(label " << mop.value << ")"; 139 break; 140 141 default: 142 assert(0 && "Unrecognized operand type"); 143 break; 144 } 145 146 return os; 147 } 148 149 150 //--------------------------------------------------------------------------- 151 // Target-independent utility routines for creating machine instructions 152 //--------------------------------------------------------------------------- 153 154 155 //------------------------------------------------------------------------ 156 // Function Set2OperandsFromInstr 157 // Function Set3OperandsFromInstr 158 // 159 // For the common case of 2- and 3-operand arithmetic/logical instructions, 160 // set the m/c instr. operands directly from the VM instruction's operands. 161 // Check whether the first or second operand is 0 and can use a dedicated "0" register. 162 // Check whether the second operand should use an immediate field or register. 163 // (First and third operands are never immediates for such instructions.) 164 // 165 // Arguments: 166 // canDiscardResult: Specifies that the result operand can be discarded 167 // by using the dedicated "0" 168 // 169 // op1position, op2position and resultPosition: Specify in which position 170 // in the machine instruction the 3 operands (arg1, arg2 171 // and result) should go. 172 // 173 // RETURN VALUE: unsigned int flags, where 174 // flags & 0x01 => operand 1 is constant and needs a register 175 // flags & 0x02 => operand 2 is constant and needs a register 176 //------------------------------------------------------------------------ 177 178 void 179 Set2OperandsFromInstr(MachineInstr* minstr, 180 InstructionNode* vmInstrNode, 181 const TargetMachine& target, 182 bool canDiscardResult, 183 int op1Position, 184 int resultPosition) 185 { 186 Set3OperandsFromInstr(minstr, vmInstrNode, target, 187 canDiscardResult, op1Position, 188 /*op2Position*/ -1, resultPosition); 189 } 190 191 #undef REVERT_TO_EXPLICIT_CONSTANT_CHECKS 192 #ifdef REVERT_TO_EXPLICIT_CONSTANT_CHECKS 193 unsigned 194 Set3OperandsFromInstrJUNK(MachineInstr* minstr, 195 InstructionNode* vmInstrNode, 196 const TargetMachine& target, 197 bool canDiscardResult, 198 int op1Position, 199 int op2Position, 200 int resultPosition) 201 { 202 assert(op1Position >= 0); 203 assert(resultPosition >= 0); 204 205 unsigned returnFlags = 0x0; 206 207 // Check if operand 1 is 0 and if so, try to use the register that gives 0, if any. 208 Value* op1Value = vmInstrNode->leftChild()->getValue(); 209 bool isValidConstant; 210 int64_t intValue = GetConstantValueAsSignedInt(op1Value, isValidConstant); 211 if (isValidConstant && intValue == 0 && target.zeroRegNum >= 0) 212 minstr->SetMachineOperand(op1Position, /*regNum*/ target.zeroRegNum); 213 else 214 { 215 if (op1Value->getValueType() == Value::ConstantVal) 216 {// value is constant and must be loaded from constant pool 217 returnFlags = returnFlags | (1 << op1Position); 218 } 219 minstr->SetMachineOperand(op1Position,MachineOperand::MO_VirtualRegister, 220 op1Value); 221 } 222 223 // Check if operand 2 (if any) fits in the immediate field of the instruction, 224 // of if it is 0 and can use a dedicated machine register 225 if (op2Position >= 0) 226 { 227 Value* op2Value = vmInstrNode->rightChild()->getValue(); 228 int64_t immedValue; 229 unsigned int machineRegNum; 230 231 MachineOperand::MachineOperandType 232 op2type = ChooseRegOrImmed(op2Value, minstr->getOpCode(), target, 233 /*canUseImmed*/ true, 234 machineRegNum, immedValue); 235 236 if (op2type == MachineOperand::MO_MachineRegister) 237 minstr->SetMachineOperand(op2Position, machineRegNum); 238 else if (op2type == MachineOperand::MO_VirtualRegister) 239 { 240 if (op2Value->getValueType() == Value::ConstantVal) 241 {// value is constant and must be loaded from constant pool 242 returnFlags = returnFlags | (1 << op2Position); 243 } 244 minstr->SetMachineOperand(op2Position, op2type, op2Value); 245 } 246 else 247 { 248 assert(op2type != MO_CCRegister); 249 minstr->SetMachineOperand(op2Position, op2type, immedValue); 250 } 251 } 252 253 // If operand 3 (result) can be discarded, use a dead register if one exists 254 if (canDiscardResult && target.zeroRegNum >= 0) 255 minstr->SetMachineOperand(resultPosition, target.zeroRegNum); 256 else 257 minstr->SetMachineOperand(resultPosition, MachineOperand::MO_VirtualRegister, vmInstrNode->getValue()); 258 259 return returnFlags; 260 } 261 #endif 262 263 264 void 265 Set3OperandsFromInstr(MachineInstr* minstr, 266 InstructionNode* vmInstrNode, 267 const TargetMachine& target, 268 bool canDiscardResult, 269 int op1Position, 270 int op2Position, 271 int resultPosition) 272 { 273 assert(op1Position >= 0); 274 assert(resultPosition >= 0); 275 276 // operand 1 277 minstr->SetMachineOperand(op1Position, MachineOperand::MO_VirtualRegister, 278 vmInstrNode->leftChild()->getValue()); 279 280 // operand 2 (if any) 281 if (op2Position >= 0) 282 minstr->SetMachineOperand(op2Position, MachineOperand::MO_VirtualRegister, 283 vmInstrNode->rightChild()->getValue()); 284 285 // result operand: if it can be discarded, use a dead register if one exists 286 if (canDiscardResult && target.zeroRegNum >= 0) 287 minstr->SetMachineOperand(resultPosition, target.zeroRegNum); 288 else 289 minstr->SetMachineOperand(resultPosition, MachineOperand::MO_VirtualRegister, vmInstrNode->getValue()); 290 } 291 292 293 MachineOperand::MachineOperandType 294 ChooseRegOrImmed(Value* val, 295 MachineOpCode opCode, 296 const TargetMachine& target, 297 bool canUseImmed, 298 unsigned int& getMachineRegNum, 299 int64_t& getImmedValue) 300 { 301 MachineOperand::MachineOperandType opType = 302 MachineOperand::MO_VirtualRegister; 303 getMachineRegNum = 0; 304 getImmedValue = 0; 305 306 // Check for the common case first: argument is not constant 307 // 308 if (val->getValueType() != Value::ConstantVal) 309 return opType; 310 311 // Now get the constant value and check if it fits in the IMMED field. 312 // Take advantage of the fact that the max unsigned value will rarely 313 // fit into any IMMED field and ignore that case (i.e., cast smaller 314 // unsigned constants to signed). 315 // 316 bool isValidConstant; 317 int64_t intValue = GetConstantValueAsSignedInt(val, isValidConstant); 318 319 if (isValidConstant) 320 { 321 if (intValue == 0 && target.zeroRegNum >= 0) 322 { 323 opType = MachineOperand::MO_MachineRegister; 324 getMachineRegNum = target.zeroRegNum; 325 } 326 else if (canUseImmed && 327 target.getInstrInfo().constantFitsInImmedField(opCode,intValue)) 328 { 329 opType = MachineOperand::MO_SignExtendedImmed; 330 getImmedValue = intValue; 331 } 332 } 333 334 return opType; 335 } 336