1 //===- MachineCycleAnalysis.cpp - Compute CycleInfo for Machine IR --------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "llvm/CodeGen/MachineCycleAnalysis.h" 10 #include "llvm/ADT/GenericCycleImpl.h" 11 #include "llvm/CodeGen/MachineLoopInfo.h" 12 #include "llvm/CodeGen/MachineRegisterInfo.h" 13 #include "llvm/CodeGen/MachineSSAContext.h" 14 #include "llvm/CodeGen/TargetInstrInfo.h" 15 #include "llvm/CodeGen/TargetSubtargetInfo.h" 16 #include "llvm/InitializePasses.h" 17 18 using namespace llvm; 19 20 template class llvm::GenericCycleInfo<llvm::MachineSSAContext>; 21 template class llvm::GenericCycle<llvm::MachineSSAContext>; 22 23 char MachineCycleInfoWrapperPass::ID = 0; 24 25 MachineCycleInfoWrapperPass::MachineCycleInfoWrapperPass() 26 : MachineFunctionPass(ID) { 27 initializeMachineCycleInfoWrapperPassPass(*PassRegistry::getPassRegistry()); 28 } 29 30 INITIALIZE_PASS_BEGIN(MachineCycleInfoWrapperPass, "machine-cycles", 31 "Machine Cycle Info Analysis", true, true) 32 INITIALIZE_PASS_END(MachineCycleInfoWrapperPass, "machine-cycles", 33 "Machine Cycle Info Analysis", true, true) 34 35 void MachineCycleInfoWrapperPass::getAnalysisUsage(AnalysisUsage &AU) const { 36 AU.setPreservesAll(); 37 MachineFunctionPass::getAnalysisUsage(AU); 38 } 39 40 bool MachineCycleInfoWrapperPass::runOnMachineFunction(MachineFunction &Func) { 41 CI.clear(); 42 43 F = &Func; 44 CI.compute(Func); 45 return false; 46 } 47 48 void MachineCycleInfoWrapperPass::print(raw_ostream &OS, const Module *) const { 49 OS << "MachineCycleInfo for function: " << F->getName() << "\n"; 50 CI.print(OS); 51 } 52 53 void MachineCycleInfoWrapperPass::releaseMemory() { 54 CI.clear(); 55 F = nullptr; 56 } 57 58 namespace { 59 class MachineCycleInfoPrinterPass : public MachineFunctionPass { 60 public: 61 static char ID; 62 63 MachineCycleInfoPrinterPass(); 64 65 bool runOnMachineFunction(MachineFunction &F) override; 66 void getAnalysisUsage(AnalysisUsage &AU) const override; 67 }; 68 } // namespace 69 70 char MachineCycleInfoPrinterPass::ID = 0; 71 72 MachineCycleInfoPrinterPass::MachineCycleInfoPrinterPass() 73 : MachineFunctionPass(ID) { 74 initializeMachineCycleInfoPrinterPassPass(*PassRegistry::getPassRegistry()); 75 } 76 77 INITIALIZE_PASS_BEGIN(MachineCycleInfoPrinterPass, "print-machine-cycles", 78 "Print Machine Cycle Info Analysis", true, true) 79 INITIALIZE_PASS_DEPENDENCY(MachineCycleInfoWrapperPass) 80 INITIALIZE_PASS_END(MachineCycleInfoPrinterPass, "print-machine-cycles", 81 "Print Machine Cycle Info Analysis", true, true) 82 83 void MachineCycleInfoPrinterPass::getAnalysisUsage(AnalysisUsage &AU) const { 84 AU.setPreservesAll(); 85 AU.addRequired<MachineCycleInfoWrapperPass>(); 86 MachineFunctionPass::getAnalysisUsage(AU); 87 } 88 89 bool MachineCycleInfoPrinterPass::runOnMachineFunction(MachineFunction &F) { 90 auto &CI = getAnalysis<MachineCycleInfoWrapperPass>(); 91 CI.print(errs()); 92 return false; 93 } 94 95 bool llvm::isCycleInvariant(const MachineCycle *Cycle, MachineInstr &I) { 96 MachineFunction *MF = I.getParent()->getParent(); 97 MachineRegisterInfo *MRI = &MF->getRegInfo(); 98 const TargetSubtargetInfo &ST = MF->getSubtarget(); 99 const TargetRegisterInfo *TRI = ST.getRegisterInfo(); 100 const TargetInstrInfo *TII = ST.getInstrInfo(); 101 102 // The instruction is cycle invariant if all of its operands are. 103 for (const MachineOperand &MO : I.operands()) { 104 if (!MO.isReg()) 105 continue; 106 107 Register Reg = MO.getReg(); 108 if (Reg == 0) 109 continue; 110 111 // An instruction that uses or defines a physical register can't e.g. be 112 // hoisted, so mark this as not invariant. 113 if (Reg.isPhysical()) { 114 if (MO.isUse()) { 115 // If the physreg has no defs anywhere, it's just an ambient register 116 // and we can freely move its uses. Alternatively, if it's allocatable, 117 // it could get allocated to something with a def during allocation. 118 // However, if the physreg is known to always be caller saved/restored 119 // then this use is safe to hoist. 120 if (!MRI->isConstantPhysReg(Reg) && 121 !(TRI->isCallerPreservedPhysReg(Reg.asMCReg(), *I.getMF())) && 122 !TII->isIgnorableUse(MO)) 123 return false; 124 // Otherwise it's safe to move. 125 continue; 126 } else if (!MO.isDead()) { 127 // A def that isn't dead can't be moved. 128 return false; 129 } else if (any_of(Cycle->getEntries(), 130 [&](const MachineBasicBlock *Block) { 131 return Block->isLiveIn(Reg); 132 })) { 133 // If the reg is live into any header of the cycle we can't hoist an 134 // instruction which would clobber it. 135 return false; 136 } 137 } 138 139 if (!MO.isUse()) 140 continue; 141 142 assert(MRI->getVRegDef(Reg) && "Machine instr not mapped for this vreg?!"); 143 144 // If the cycle contains the definition of an operand, then the instruction 145 // isn't cycle invariant. 146 if (Cycle->contains(MRI->getVRegDef(Reg)->getParent())) 147 return false; 148 } 149 150 // If we got this far, the instruction is cycle invariant! 151 return true; 152 } 153