1 //===- MachineCycleAnalysis.cpp - Compute CycleInfo for Machine IR --------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "llvm/CodeGen/MachineCycleAnalysis.h" 10 #include "llvm/ADT/GenericCycleImpl.h" 11 #include "llvm/CodeGen/MachineRegisterInfo.h" 12 #include "llvm/CodeGen/TargetInstrInfo.h" 13 #include "llvm/CodeGen/TargetSubtargetInfo.h" 14 15 using namespace llvm; 16 17 template class llvm::GenericCycleInfo<llvm::MachineSSAContext>; 18 template class llvm::GenericCycle<llvm::MachineSSAContext>; 19 20 char MachineCycleInfoWrapperPass::ID = 0; 21 22 MachineCycleInfoWrapperPass::MachineCycleInfoWrapperPass() 23 : MachineFunctionPass(ID) { 24 initializeMachineCycleInfoWrapperPassPass(*PassRegistry::getPassRegistry()); 25 } 26 27 INITIALIZE_PASS_BEGIN(MachineCycleInfoWrapperPass, "machine-cycles", 28 "Machine Cycle Info Analysis", true, true) 29 INITIALIZE_PASS_END(MachineCycleInfoWrapperPass, "machine-cycles", 30 "Machine Cycle Info Analysis", true, true) 31 32 void MachineCycleInfoWrapperPass::getAnalysisUsage(AnalysisUsage &AU) const { 33 AU.setPreservesAll(); 34 MachineFunctionPass::getAnalysisUsage(AU); 35 } 36 37 bool MachineCycleInfoWrapperPass::runOnMachineFunction(MachineFunction &Func) { 38 CI.clear(); 39 40 F = &Func; 41 CI.compute(Func); 42 return false; 43 } 44 45 void MachineCycleInfoWrapperPass::print(raw_ostream &OS, const Module *) const { 46 OS << "MachineCycleInfo for function: " << F->getName() << "\n"; 47 CI.print(OS); 48 } 49 50 void MachineCycleInfoWrapperPass::releaseMemory() { 51 CI.clear(); 52 F = nullptr; 53 } 54 55 char MachineCycleInfoPrinterPass::ID = 0; 56 57 MachineCycleInfoPrinterPass::MachineCycleInfoPrinterPass() 58 : MachineFunctionPass(ID) { 59 initializeMachineCycleInfoPrinterPassPass(*PassRegistry::getPassRegistry()); 60 } 61 62 INITIALIZE_PASS_BEGIN(MachineCycleInfoPrinterPass, "print-machine-cycles", 63 "Print Machine Cycle Info Analysis", true, true) 64 INITIALIZE_PASS_DEPENDENCY(MachineCycleInfoWrapperPass) 65 INITIALIZE_PASS_END(MachineCycleInfoPrinterPass, "print-machine-cycles", 66 "Print Machine Cycle Info Analysis", true, true) 67 68 void MachineCycleInfoPrinterPass::getAnalysisUsage(AnalysisUsage &AU) const { 69 AU.setPreservesAll(); 70 AU.addRequired<MachineCycleInfoWrapperPass>(); 71 MachineFunctionPass::getAnalysisUsage(AU); 72 } 73 74 bool MachineCycleInfoPrinterPass::runOnMachineFunction(MachineFunction &F) { 75 auto &CI = getAnalysis<MachineCycleInfoWrapperPass>(); 76 CI.print(errs()); 77 return false; 78 } 79 80 bool llvm::isCycleInvariant(const MachineCycle *Cycle, MachineInstr &I) { 81 MachineFunction *MF = I.getParent()->getParent(); 82 MachineRegisterInfo *MRI = &MF->getRegInfo(); 83 const TargetSubtargetInfo &ST = MF->getSubtarget(); 84 const TargetRegisterInfo *TRI = ST.getRegisterInfo(); 85 const TargetInstrInfo *TII = ST.getInstrInfo(); 86 87 // The instruction is cycle invariant if all of its operands are. 88 for (const MachineOperand &MO : I.operands()) { 89 if (!MO.isReg()) 90 continue; 91 92 Register Reg = MO.getReg(); 93 if (Reg == 0) 94 continue; 95 96 // An instruction that uses or defines a physical register can't e.g. be 97 // hoisted, so mark this as not invariant. 98 if (Register::isPhysicalRegister(Reg)) { 99 if (MO.isUse()) { 100 // If the physreg has no defs anywhere, it's just an ambient register 101 // and we can freely move its uses. Alternatively, if it's allocatable, 102 // it could get allocated to something with a def during allocation. 103 // However, if the physreg is known to always be caller saved/restored 104 // then this use is safe to hoist. 105 if (!MRI->isConstantPhysReg(Reg) && 106 !(TRI->isCallerPreservedPhysReg(Reg.asMCReg(), *I.getMF())) && 107 !TII->isIgnorableUse(MO)) 108 return false; 109 // Otherwise it's safe to move. 110 continue; 111 } else if (!MO.isDead()) { 112 // A def that isn't dead can't be moved. 113 return false; 114 } else if (any_of(Cycle->getEntries(), 115 [&](const MachineBasicBlock *Block) { 116 return Block->isLiveIn(Reg); 117 })) { 118 // If the reg is live into any header of the cycle we can't hoist an 119 // instruction which would clobber it. 120 return false; 121 } 122 } 123 124 if (!MO.isUse()) 125 continue; 126 127 assert(MRI->getVRegDef(Reg) && "Machine instr not mapped for this vreg?!"); 128 129 // If the cycle contains the definition of an operand, then the instruction 130 // isn't cycle invariant. 131 if (Cycle->contains(MRI->getVRegDef(Reg)->getParent())) 132 return false; 133 } 134 135 // If we got this far, the instruction is cycle invariant! 136 return true; 137 } 138