1 //===- MachineCycleAnalysis.cpp - Compute CycleInfo for Machine IR --------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "llvm/CodeGen/MachineCycleAnalysis.h" 10 #include "llvm/ADT/GenericCycleImpl.h" 11 #include "llvm/CodeGen/MachineRegisterInfo.h" 12 #include "llvm/CodeGen/MachineSSAContext.h" 13 #include "llvm/CodeGen/TargetInstrInfo.h" 14 #include "llvm/CodeGen/TargetSubtargetInfo.h" 15 #include "llvm/InitializePasses.h" 16 17 using namespace llvm; 18 19 template class llvm::GenericCycleInfo<llvm::MachineSSAContext>; 20 template class llvm::GenericCycle<llvm::MachineSSAContext>; 21 22 char MachineCycleInfoWrapperPass::ID = 0; 23 24 MachineCycleInfoWrapperPass::MachineCycleInfoWrapperPass() 25 : MachineFunctionPass(ID) { 26 initializeMachineCycleInfoWrapperPassPass(*PassRegistry::getPassRegistry()); 27 } 28 29 INITIALIZE_PASS_BEGIN(MachineCycleInfoWrapperPass, "machine-cycles", 30 "Machine Cycle Info Analysis", true, true) 31 INITIALIZE_PASS_END(MachineCycleInfoWrapperPass, "machine-cycles", 32 "Machine Cycle Info Analysis", true, true) 33 34 void MachineCycleInfoWrapperPass::getAnalysisUsage(AnalysisUsage &AU) const { 35 AU.setPreservesAll(); 36 MachineFunctionPass::getAnalysisUsage(AU); 37 } 38 39 bool MachineCycleInfoWrapperPass::runOnMachineFunction(MachineFunction &Func) { 40 CI.clear(); 41 42 F = &Func; 43 CI.compute(Func); 44 return false; 45 } 46 47 void MachineCycleInfoWrapperPass::print(raw_ostream &OS, const Module *) const { 48 OS << "MachineCycleInfo for function: " << F->getName() << "\n"; 49 CI.print(OS); 50 } 51 52 void MachineCycleInfoWrapperPass::releaseMemory() { 53 CI.clear(); 54 F = nullptr; 55 } 56 57 class MachineCycleInfoPrinterPass : public MachineFunctionPass { 58 public: 59 static char ID; 60 61 MachineCycleInfoPrinterPass(); 62 63 bool runOnMachineFunction(MachineFunction &F) override; 64 void getAnalysisUsage(AnalysisUsage &AU) const override; 65 }; 66 67 char MachineCycleInfoPrinterPass::ID = 0; 68 69 MachineCycleInfoPrinterPass::MachineCycleInfoPrinterPass() 70 : MachineFunctionPass(ID) { 71 initializeMachineCycleInfoPrinterPassPass(*PassRegistry::getPassRegistry()); 72 } 73 74 INITIALIZE_PASS_BEGIN(MachineCycleInfoPrinterPass, "print-machine-cycles", 75 "Print Machine Cycle Info Analysis", true, true) 76 INITIALIZE_PASS_DEPENDENCY(MachineCycleInfoWrapperPass) 77 INITIALIZE_PASS_END(MachineCycleInfoPrinterPass, "print-machine-cycles", 78 "Print Machine Cycle Info Analysis", true, true) 79 80 void MachineCycleInfoPrinterPass::getAnalysisUsage(AnalysisUsage &AU) const { 81 AU.setPreservesAll(); 82 AU.addRequired<MachineCycleInfoWrapperPass>(); 83 MachineFunctionPass::getAnalysisUsage(AU); 84 } 85 86 bool MachineCycleInfoPrinterPass::runOnMachineFunction(MachineFunction &F) { 87 auto &CI = getAnalysis<MachineCycleInfoWrapperPass>(); 88 CI.print(errs()); 89 return false; 90 } 91 92 bool llvm::isCycleInvariant(const MachineCycle *Cycle, MachineInstr &I) { 93 MachineFunction *MF = I.getParent()->getParent(); 94 MachineRegisterInfo *MRI = &MF->getRegInfo(); 95 const TargetSubtargetInfo &ST = MF->getSubtarget(); 96 const TargetRegisterInfo *TRI = ST.getRegisterInfo(); 97 const TargetInstrInfo *TII = ST.getInstrInfo(); 98 99 // The instruction is cycle invariant if all of its operands are. 100 for (const MachineOperand &MO : I.operands()) { 101 if (!MO.isReg()) 102 continue; 103 104 Register Reg = MO.getReg(); 105 if (Reg == 0) 106 continue; 107 108 // An instruction that uses or defines a physical register can't e.g. be 109 // hoisted, so mark this as not invariant. 110 if (Register::isPhysicalRegister(Reg)) { 111 if (MO.isUse()) { 112 // If the physreg has no defs anywhere, it's just an ambient register 113 // and we can freely move its uses. Alternatively, if it's allocatable, 114 // it could get allocated to something with a def during allocation. 115 // However, if the physreg is known to always be caller saved/restored 116 // then this use is safe to hoist. 117 if (!MRI->isConstantPhysReg(Reg) && 118 !(TRI->isCallerPreservedPhysReg(Reg.asMCReg(), *I.getMF())) && 119 !TII->isIgnorableUse(MO)) 120 return false; 121 // Otherwise it's safe to move. 122 continue; 123 } else if (!MO.isDead()) { 124 // A def that isn't dead can't be moved. 125 return false; 126 } else if (any_of(Cycle->getEntries(), 127 [&](const MachineBasicBlock *Block) { 128 return Block->isLiveIn(Reg); 129 })) { 130 // If the reg is live into any header of the cycle we can't hoist an 131 // instruction which would clobber it. 132 return false; 133 } 134 } 135 136 if (!MO.isUse()) 137 continue; 138 139 assert(MRI->getVRegDef(Reg) && "Machine instr not mapped for this vreg?!"); 140 141 // If the cycle contains the definition of an operand, then the instruction 142 // isn't cycle invariant. 143 if (Cycle->contains(MRI->getVRegDef(Reg)->getParent())) 144 return false; 145 } 146 147 // If we got this far, the instruction is cycle invariant! 148 return true; 149 } 150