1 //===-- llvm/CodeGen/MachineBasicBlock.cpp ----------------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // Collect the sequence of machine instructions for a basic block. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "llvm/CodeGen/MachineBasicBlock.h" 15 #include "llvm/ADT/SmallPtrSet.h" 16 #include "llvm/ADT/SmallString.h" 17 #include "llvm/CodeGen/LiveIntervalAnalysis.h" 18 #include "llvm/CodeGen/LiveVariables.h" 19 #include "llvm/CodeGen/MachineDominators.h" 20 #include "llvm/CodeGen/MachineFunction.h" 21 #include "llvm/CodeGen/MachineInstrBuilder.h" 22 #include "llvm/CodeGen/MachineLoopInfo.h" 23 #include "llvm/CodeGen/MachineRegisterInfo.h" 24 #include "llvm/CodeGen/SlotIndexes.h" 25 #include "llvm/IR/BasicBlock.h" 26 #include "llvm/IR/DataLayout.h" 27 #include "llvm/IR/ModuleSlotTracker.h" 28 #include "llvm/MC/MCAsmInfo.h" 29 #include "llvm/MC/MCContext.h" 30 #include "llvm/Support/Debug.h" 31 #include "llvm/Support/Format.h" 32 #include "llvm/Support/raw_ostream.h" 33 #include "llvm/Target/TargetInstrInfo.h" 34 #include "llvm/Target/TargetMachine.h" 35 #include "llvm/Target/TargetRegisterInfo.h" 36 #include "llvm/Target/TargetSubtargetInfo.h" 37 #include <algorithm> 38 using namespace llvm; 39 40 #define DEBUG_TYPE "codegen" 41 42 MachineBasicBlock::MachineBasicBlock(MachineFunction &mf, const BasicBlock *bb) 43 : BB(bb), Number(-1), xParent(&mf) { 44 Insts.Parent = this; 45 } 46 47 MachineBasicBlock::~MachineBasicBlock() { 48 } 49 50 /// Return the MCSymbol for this basic block. 51 MCSymbol *MachineBasicBlock::getSymbol() const { 52 if (!CachedMCSymbol) { 53 const MachineFunction *MF = getParent(); 54 MCContext &Ctx = MF->getContext(); 55 const char *Prefix = Ctx.getAsmInfo()->getPrivateLabelPrefix(); 56 CachedMCSymbol = Ctx.getOrCreateSymbol(Twine(Prefix) + "BB" + 57 Twine(MF->getFunctionNumber()) + 58 "_" + Twine(getNumber())); 59 } 60 61 return CachedMCSymbol; 62 } 63 64 65 raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineBasicBlock &MBB) { 66 MBB.print(OS); 67 return OS; 68 } 69 70 /// When an MBB is added to an MF, we need to update the parent pointer of the 71 /// MBB, the MBB numbering, and any instructions in the MBB to be on the right 72 /// operand list for registers. 73 /// 74 /// MBBs start out as #-1. When a MBB is added to a MachineFunction, it 75 /// gets the next available unique MBB number. If it is removed from a 76 /// MachineFunction, it goes back to being #-1. 77 void ilist_traits<MachineBasicBlock>::addNodeToList(MachineBasicBlock *N) { 78 MachineFunction &MF = *N->getParent(); 79 N->Number = MF.addToMBBNumbering(N); 80 81 // Make sure the instructions have their operands in the reginfo lists. 82 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 83 for (MachineBasicBlock::instr_iterator 84 I = N->instr_begin(), E = N->instr_end(); I != E; ++I) 85 I->AddRegOperandsToUseLists(RegInfo); 86 } 87 88 void ilist_traits<MachineBasicBlock>::removeNodeFromList(MachineBasicBlock *N) { 89 N->getParent()->removeFromMBBNumbering(N->Number); 90 N->Number = -1; 91 } 92 93 /// When we add an instruction to a basic block list, we update its parent 94 /// pointer and add its operands from reg use/def lists if appropriate. 95 void ilist_traits<MachineInstr>::addNodeToList(MachineInstr *N) { 96 assert(!N->getParent() && "machine instruction already in a basic block"); 97 N->setParent(Parent); 98 99 // Add the instruction's register operands to their corresponding 100 // use/def lists. 101 MachineFunction *MF = Parent->getParent(); 102 N->AddRegOperandsToUseLists(MF->getRegInfo()); 103 } 104 105 /// When we remove an instruction from a basic block list, we update its parent 106 /// pointer and remove its operands from reg use/def lists if appropriate. 107 void ilist_traits<MachineInstr>::removeNodeFromList(MachineInstr *N) { 108 assert(N->getParent() && "machine instruction not in a basic block"); 109 110 // Remove from the use/def lists. 111 if (MachineFunction *MF = N->getParent()->getParent()) 112 N->RemoveRegOperandsFromUseLists(MF->getRegInfo()); 113 114 N->setParent(nullptr); 115 } 116 117 /// When moving a range of instructions from one MBB list to another, we need to 118 /// update the parent pointers and the use/def lists. 119 void ilist_traits<MachineInstr>:: 120 transferNodesFromList(ilist_traits<MachineInstr> &fromList, 121 ilist_iterator<MachineInstr> first, 122 ilist_iterator<MachineInstr> last) { 123 assert(Parent->getParent() == fromList.Parent->getParent() && 124 "MachineInstr parent mismatch!"); 125 126 // Splice within the same MBB -> no change. 127 if (Parent == fromList.Parent) return; 128 129 // If splicing between two blocks within the same function, just update the 130 // parent pointers. 131 for (; first != last; ++first) 132 first->setParent(Parent); 133 } 134 135 void ilist_traits<MachineInstr>::deleteNode(MachineInstr* MI) { 136 assert(!MI->getParent() && "MI is still in a block!"); 137 Parent->getParent()->DeleteMachineInstr(MI); 138 } 139 140 MachineBasicBlock::iterator MachineBasicBlock::getFirstNonPHI() { 141 instr_iterator I = instr_begin(), E = instr_end(); 142 while (I != E && I->isPHI()) 143 ++I; 144 assert((I == E || !I->isInsideBundle()) && 145 "First non-phi MI cannot be inside a bundle!"); 146 return I; 147 } 148 149 MachineBasicBlock::iterator 150 MachineBasicBlock::SkipPHIsAndLabels(MachineBasicBlock::iterator I) { 151 iterator E = end(); 152 while (I != E && (I->isPHI() || I->isPosition() || I->isDebugValue())) 153 ++I; 154 // FIXME: This needs to change if we wish to bundle labels / dbg_values 155 // inside the bundle. 156 assert((I == E || !I->isInsideBundle()) && 157 "First non-phi / non-label instruction is inside a bundle!"); 158 return I; 159 } 160 161 MachineBasicBlock::iterator MachineBasicBlock::getFirstTerminator() { 162 iterator B = begin(), E = end(), I = E; 163 while (I != B && ((--I)->isTerminator() || I->isDebugValue())) 164 ; /*noop */ 165 while (I != E && !I->isTerminator()) 166 ++I; 167 return I; 168 } 169 170 MachineBasicBlock::instr_iterator MachineBasicBlock::getFirstInstrTerminator() { 171 instr_iterator B = instr_begin(), E = instr_end(), I = E; 172 while (I != B && ((--I)->isTerminator() || I->isDebugValue())) 173 ; /*noop */ 174 while (I != E && !I->isTerminator()) 175 ++I; 176 return I; 177 } 178 179 MachineBasicBlock::iterator MachineBasicBlock::getFirstNonDebugInstr() { 180 // Skip over begin-of-block dbg_value instructions. 181 iterator I = begin(), E = end(); 182 while (I != E && I->isDebugValue()) 183 ++I; 184 return I; 185 } 186 187 MachineBasicBlock::iterator MachineBasicBlock::getLastNonDebugInstr() { 188 // Skip over end-of-block dbg_value instructions. 189 instr_iterator B = instr_begin(), I = instr_end(); 190 while (I != B) { 191 --I; 192 // Return instruction that starts a bundle. 193 if (I->isDebugValue() || I->isInsideBundle()) 194 continue; 195 return I; 196 } 197 // The block is all debug values. 198 return end(); 199 } 200 201 const MachineBasicBlock *MachineBasicBlock::getLandingPadSuccessor() const { 202 // A block with a landing pad successor only has one other successor. 203 if (succ_size() > 2) 204 return nullptr; 205 for (const_succ_iterator I = succ_begin(), E = succ_end(); I != E; ++I) 206 if ((*I)->isEHPad()) 207 return *I; 208 return nullptr; 209 } 210 211 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) 212 void MachineBasicBlock::dump() const { 213 print(dbgs()); 214 } 215 #endif 216 217 StringRef MachineBasicBlock::getName() const { 218 if (const BasicBlock *LBB = getBasicBlock()) 219 return LBB->getName(); 220 else 221 return "(null)"; 222 } 223 224 /// Return a hopefully unique identifier for this block. 225 std::string MachineBasicBlock::getFullName() const { 226 std::string Name; 227 if (getParent()) 228 Name = (getParent()->getName() + ":").str(); 229 if (getBasicBlock()) 230 Name += getBasicBlock()->getName(); 231 else 232 Name += ("BB" + Twine(getNumber())).str(); 233 return Name; 234 } 235 236 void MachineBasicBlock::print(raw_ostream &OS, SlotIndexes *Indexes) const { 237 const MachineFunction *MF = getParent(); 238 if (!MF) { 239 OS << "Can't print out MachineBasicBlock because parent MachineFunction" 240 << " is null\n"; 241 return; 242 } 243 const Function *F = MF->getFunction(); 244 const Module *M = F ? F->getParent() : nullptr; 245 ModuleSlotTracker MST(M); 246 print(OS, MST, Indexes); 247 } 248 249 void MachineBasicBlock::print(raw_ostream &OS, ModuleSlotTracker &MST, 250 SlotIndexes *Indexes) const { 251 const MachineFunction *MF = getParent(); 252 if (!MF) { 253 OS << "Can't print out MachineBasicBlock because parent MachineFunction" 254 << " is null\n"; 255 return; 256 } 257 258 if (Indexes) 259 OS << Indexes->getMBBStartIdx(this) << '\t'; 260 261 OS << "BB#" << getNumber() << ": "; 262 263 const char *Comma = ""; 264 if (const BasicBlock *LBB = getBasicBlock()) { 265 OS << Comma << "derived from LLVM BB "; 266 LBB->printAsOperand(OS, /*PrintType=*/false, MST); 267 Comma = ", "; 268 } 269 if (isEHPad()) { OS << Comma << "EH LANDING PAD"; Comma = ", "; } 270 if (hasAddressTaken()) { OS << Comma << "ADDRESS TAKEN"; Comma = ", "; } 271 if (Alignment) 272 OS << Comma << "Align " << Alignment << " (" << (1u << Alignment) 273 << " bytes)"; 274 275 OS << '\n'; 276 277 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo(); 278 if (!livein_empty()) { 279 if (Indexes) OS << '\t'; 280 OS << " Live Ins:"; 281 for (const auto &LI : make_range(livein_begin(), livein_end())) { 282 OS << ' ' << PrintReg(LI.PhysReg, TRI); 283 if (LI.LaneMask != ~0u) 284 OS << format(":%08X", LI.LaneMask); 285 } 286 OS << '\n'; 287 } 288 // Print the preds of this block according to the CFG. 289 if (!pred_empty()) { 290 if (Indexes) OS << '\t'; 291 OS << " Predecessors according to CFG:"; 292 for (const_pred_iterator PI = pred_begin(), E = pred_end(); PI != E; ++PI) 293 OS << " BB#" << (*PI)->getNumber(); 294 OS << '\n'; 295 } 296 297 for (const_instr_iterator I = instr_begin(); I != instr_end(); ++I) { 298 if (Indexes) { 299 if (Indexes->hasIndex(I)) 300 OS << Indexes->getInstructionIndex(I); 301 OS << '\t'; 302 } 303 OS << '\t'; 304 if (I->isInsideBundle()) 305 OS << " * "; 306 I->print(OS, MST); 307 } 308 309 // Print the successors of this block according to the CFG. 310 if (!succ_empty()) { 311 if (Indexes) OS << '\t'; 312 OS << " Successors according to CFG:"; 313 for (const_succ_iterator SI = succ_begin(), E = succ_end(); SI != E; ++SI) { 314 OS << " BB#" << (*SI)->getNumber(); 315 if (!Weights.empty()) 316 OS << '(' << *getWeightIterator(SI) << ')'; 317 } 318 OS << '\n'; 319 } 320 } 321 322 void MachineBasicBlock::printAsOperand(raw_ostream &OS, 323 bool /*PrintType*/) const { 324 OS << "BB#" << getNumber(); 325 } 326 327 void MachineBasicBlock::removeLiveIn(MCPhysReg Reg, unsigned LaneMask) { 328 LiveInVector::iterator I = std::find_if( 329 LiveIns.begin(), LiveIns.end(), 330 [Reg] (const RegisterMaskPair &LI) { return LI.PhysReg == Reg; }); 331 if (I == LiveIns.end()) 332 return; 333 334 I->LaneMask &= ~LaneMask; 335 if (I->LaneMask == 0) 336 LiveIns.erase(I); 337 } 338 339 bool MachineBasicBlock::isLiveIn(MCPhysReg Reg, unsigned LaneMask) const { 340 livein_iterator I = std::find_if( 341 LiveIns.begin(), LiveIns.end(), 342 [Reg] (const RegisterMaskPair &LI) { return LI.PhysReg == Reg; }); 343 return I != livein_end() && (I->LaneMask & LaneMask) != 0; 344 } 345 346 void MachineBasicBlock::sortUniqueLiveIns() { 347 std::sort(LiveIns.begin(), LiveIns.end(), 348 [](const RegisterMaskPair &LI0, const RegisterMaskPair &LI1) { 349 return LI0.PhysReg < LI1.PhysReg; 350 }); 351 // Liveins are sorted by physreg now we can merge their lanemasks. 352 LiveInVector::const_iterator I = LiveIns.begin(); 353 LiveInVector::const_iterator J; 354 LiveInVector::iterator Out = LiveIns.begin(); 355 for (; I != LiveIns.end(); ++Out, I = J) { 356 unsigned PhysReg = I->PhysReg; 357 unsigned LaneMask = I->LaneMask; 358 for (J = std::next(I); J != LiveIns.end() && J->PhysReg == PhysReg; ++J) 359 LaneMask |= J->LaneMask; 360 Out->PhysReg = PhysReg; 361 Out->LaneMask = LaneMask; 362 } 363 LiveIns.erase(Out, LiveIns.end()); 364 } 365 366 unsigned 367 MachineBasicBlock::addLiveIn(MCPhysReg PhysReg, const TargetRegisterClass *RC) { 368 assert(getParent() && "MBB must be inserted in function"); 369 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg) && "Expected physreg"); 370 assert(RC && "Register class is required"); 371 assert((isEHPad() || this == &getParent()->front()) && 372 "Only the entry block and landing pads can have physreg live ins"); 373 374 bool LiveIn = isLiveIn(PhysReg); 375 iterator I = SkipPHIsAndLabels(begin()), E = end(); 376 MachineRegisterInfo &MRI = getParent()->getRegInfo(); 377 const TargetInstrInfo &TII = *getParent()->getSubtarget().getInstrInfo(); 378 379 // Look for an existing copy. 380 if (LiveIn) 381 for (;I != E && I->isCopy(); ++I) 382 if (I->getOperand(1).getReg() == PhysReg) { 383 unsigned VirtReg = I->getOperand(0).getReg(); 384 if (!MRI.constrainRegClass(VirtReg, RC)) 385 llvm_unreachable("Incompatible live-in register class."); 386 return VirtReg; 387 } 388 389 // No luck, create a virtual register. 390 unsigned VirtReg = MRI.createVirtualRegister(RC); 391 BuildMI(*this, I, DebugLoc(), TII.get(TargetOpcode::COPY), VirtReg) 392 .addReg(PhysReg, RegState::Kill); 393 if (!LiveIn) 394 addLiveIn(PhysReg); 395 return VirtReg; 396 } 397 398 void MachineBasicBlock::moveBefore(MachineBasicBlock *NewAfter) { 399 getParent()->splice(NewAfter, this); 400 } 401 402 void MachineBasicBlock::moveAfter(MachineBasicBlock *NewBefore) { 403 MachineFunction::iterator BBI = NewBefore; 404 getParent()->splice(++BBI, this); 405 } 406 407 void MachineBasicBlock::updateTerminator() { 408 const TargetInstrInfo *TII = getParent()->getSubtarget().getInstrInfo(); 409 // A block with no successors has no concerns with fall-through edges. 410 if (this->succ_empty()) return; 411 412 MachineBasicBlock *TBB = nullptr, *FBB = nullptr; 413 SmallVector<MachineOperand, 4> Cond; 414 DebugLoc dl; // FIXME: this is nowhere 415 bool B = TII->AnalyzeBranch(*this, TBB, FBB, Cond); 416 (void) B; 417 assert(!B && "UpdateTerminators requires analyzable predecessors!"); 418 if (Cond.empty()) { 419 if (TBB) { 420 // The block has an unconditional branch. If its successor is now 421 // its layout successor, delete the branch. 422 if (isLayoutSuccessor(TBB)) 423 TII->RemoveBranch(*this); 424 } else { 425 // The block has an unconditional fallthrough. If its successor is not 426 // its layout successor, insert a branch. First we have to locate the 427 // only non-landing-pad successor, as that is the fallthrough block. 428 for (succ_iterator SI = succ_begin(), SE = succ_end(); SI != SE; ++SI) { 429 if ((*SI)->isEHPad()) 430 continue; 431 assert(!TBB && "Found more than one non-landing-pad successor!"); 432 TBB = *SI; 433 } 434 435 // If there is no non-landing-pad successor, the block has no 436 // fall-through edges to be concerned with. 437 if (!TBB) 438 return; 439 440 // Finally update the unconditional successor to be reached via a branch 441 // if it would not be reached by fallthrough. 442 if (!isLayoutSuccessor(TBB)) 443 TII->InsertBranch(*this, TBB, nullptr, Cond, dl); 444 } 445 } else { 446 if (FBB) { 447 // The block has a non-fallthrough conditional branch. If one of its 448 // successors is its layout successor, rewrite it to a fallthrough 449 // conditional branch. 450 if (isLayoutSuccessor(TBB)) { 451 if (TII->ReverseBranchCondition(Cond)) 452 return; 453 TII->RemoveBranch(*this); 454 TII->InsertBranch(*this, FBB, nullptr, Cond, dl); 455 } else if (isLayoutSuccessor(FBB)) { 456 TII->RemoveBranch(*this); 457 TII->InsertBranch(*this, TBB, nullptr, Cond, dl); 458 } 459 } else { 460 // Walk through the successors and find the successor which is not 461 // a landing pad and is not the conditional branch destination (in TBB) 462 // as the fallthrough successor. 463 MachineBasicBlock *FallthroughBB = nullptr; 464 for (succ_iterator SI = succ_begin(), SE = succ_end(); SI != SE; ++SI) { 465 if ((*SI)->isEHPad() || *SI == TBB) 466 continue; 467 assert(!FallthroughBB && "Found more than one fallthrough successor."); 468 FallthroughBB = *SI; 469 } 470 if (!FallthroughBB && canFallThrough()) { 471 // We fallthrough to the same basic block as the conditional jump 472 // targets. Remove the conditional jump, leaving unconditional 473 // fallthrough. 474 // FIXME: This does not seem like a reasonable pattern to support, but 475 // it has been seen in the wild coming out of degenerate ARM test cases. 476 TII->RemoveBranch(*this); 477 478 // Finally update the unconditional successor to be reached via a branch 479 // if it would not be reached by fallthrough. 480 if (!isLayoutSuccessor(TBB)) 481 TII->InsertBranch(*this, TBB, nullptr, Cond, dl); 482 return; 483 } 484 485 // The block has a fallthrough conditional branch. 486 if (isLayoutSuccessor(TBB)) { 487 if (TII->ReverseBranchCondition(Cond)) { 488 // We can't reverse the condition, add an unconditional branch. 489 Cond.clear(); 490 TII->InsertBranch(*this, FallthroughBB, nullptr, Cond, dl); 491 return; 492 } 493 TII->RemoveBranch(*this); 494 TII->InsertBranch(*this, FallthroughBB, nullptr, Cond, dl); 495 } else if (!isLayoutSuccessor(FallthroughBB)) { 496 TII->RemoveBranch(*this); 497 TII->InsertBranch(*this, TBB, FallthroughBB, Cond, dl); 498 } 499 } 500 } 501 } 502 503 void MachineBasicBlock::addSuccessor(MachineBasicBlock *succ, uint32_t weight) { 504 505 // If we see non-zero value for the first time it means we actually use Weight 506 // list, so we fill all Weights with 0's. 507 if (weight != 0 && Weights.empty()) 508 Weights.resize(Successors.size()); 509 510 if (weight != 0 || !Weights.empty()) 511 Weights.push_back(weight); 512 513 Successors.push_back(succ); 514 succ->addPredecessor(this); 515 } 516 517 void MachineBasicBlock::removeSuccessor(MachineBasicBlock *succ) { 518 succ->removePredecessor(this); 519 succ_iterator I = std::find(Successors.begin(), Successors.end(), succ); 520 assert(I != Successors.end() && "Not a current successor!"); 521 522 // If Weight list is empty it means we don't use it (disabled optimization). 523 if (!Weights.empty()) { 524 weight_iterator WI = getWeightIterator(I); 525 Weights.erase(WI); 526 } 527 528 Successors.erase(I); 529 } 530 531 MachineBasicBlock::succ_iterator 532 MachineBasicBlock::removeSuccessor(succ_iterator I) { 533 assert(I != Successors.end() && "Not a current successor!"); 534 535 // If Weight list is empty it means we don't use it (disabled optimization). 536 if (!Weights.empty()) { 537 weight_iterator WI = getWeightIterator(I); 538 Weights.erase(WI); 539 } 540 541 (*I)->removePredecessor(this); 542 return Successors.erase(I); 543 } 544 545 void MachineBasicBlock::replaceSuccessor(MachineBasicBlock *Old, 546 MachineBasicBlock *New) { 547 if (Old == New) 548 return; 549 550 succ_iterator E = succ_end(); 551 succ_iterator NewI = E; 552 succ_iterator OldI = E; 553 for (succ_iterator I = succ_begin(); I != E; ++I) { 554 if (*I == Old) { 555 OldI = I; 556 if (NewI != E) 557 break; 558 } 559 if (*I == New) { 560 NewI = I; 561 if (OldI != E) 562 break; 563 } 564 } 565 assert(OldI != E && "Old is not a successor of this block"); 566 Old->removePredecessor(this); 567 568 // If New isn't already a successor, let it take Old's place. 569 if (NewI == E) { 570 New->addPredecessor(this); 571 *OldI = New; 572 return; 573 } 574 575 // New is already a successor. 576 // Update its weight instead of adding a duplicate edge. 577 if (!Weights.empty()) { 578 weight_iterator OldWI = getWeightIterator(OldI); 579 *getWeightIterator(NewI) += *OldWI; 580 Weights.erase(OldWI); 581 } 582 Successors.erase(OldI); 583 } 584 585 void MachineBasicBlock::addPredecessor(MachineBasicBlock *pred) { 586 Predecessors.push_back(pred); 587 } 588 589 void MachineBasicBlock::removePredecessor(MachineBasicBlock *pred) { 590 pred_iterator I = std::find(Predecessors.begin(), Predecessors.end(), pred); 591 assert(I != Predecessors.end() && "Pred is not a predecessor of this block!"); 592 Predecessors.erase(I); 593 } 594 595 void MachineBasicBlock::transferSuccessors(MachineBasicBlock *fromMBB) { 596 if (this == fromMBB) 597 return; 598 599 while (!fromMBB->succ_empty()) { 600 MachineBasicBlock *Succ = *fromMBB->succ_begin(); 601 uint32_t Weight = 0; 602 603 // If Weight list is empty it means we don't use it (disabled optimization). 604 if (!fromMBB->Weights.empty()) 605 Weight = *fromMBB->Weights.begin(); 606 607 addSuccessor(Succ, Weight); 608 fromMBB->removeSuccessor(Succ); 609 } 610 } 611 612 void 613 MachineBasicBlock::transferSuccessorsAndUpdatePHIs(MachineBasicBlock *fromMBB) { 614 if (this == fromMBB) 615 return; 616 617 while (!fromMBB->succ_empty()) { 618 MachineBasicBlock *Succ = *fromMBB->succ_begin(); 619 uint32_t Weight = 0; 620 if (!fromMBB->Weights.empty()) 621 Weight = *fromMBB->Weights.begin(); 622 addSuccessor(Succ, Weight); 623 fromMBB->removeSuccessor(Succ); 624 625 // Fix up any PHI nodes in the successor. 626 for (MachineBasicBlock::instr_iterator MI = Succ->instr_begin(), 627 ME = Succ->instr_end(); MI != ME && MI->isPHI(); ++MI) 628 for (unsigned i = 2, e = MI->getNumOperands()+1; i != e; i += 2) { 629 MachineOperand &MO = MI->getOperand(i); 630 if (MO.getMBB() == fromMBB) 631 MO.setMBB(this); 632 } 633 } 634 } 635 636 bool MachineBasicBlock::isPredecessor(const MachineBasicBlock *MBB) const { 637 return std::find(pred_begin(), pred_end(), MBB) != pred_end(); 638 } 639 640 bool MachineBasicBlock::isSuccessor(const MachineBasicBlock *MBB) const { 641 return std::find(succ_begin(), succ_end(), MBB) != succ_end(); 642 } 643 644 bool MachineBasicBlock::isLayoutSuccessor(const MachineBasicBlock *MBB) const { 645 MachineFunction::const_iterator I(this); 646 return std::next(I) == MachineFunction::const_iterator(MBB); 647 } 648 649 bool MachineBasicBlock::canFallThrough() { 650 MachineFunction::iterator Fallthrough = this; 651 ++Fallthrough; 652 // If FallthroughBlock is off the end of the function, it can't fall through. 653 if (Fallthrough == getParent()->end()) 654 return false; 655 656 // If FallthroughBlock isn't a successor, no fallthrough is possible. 657 if (!isSuccessor(Fallthrough)) 658 return false; 659 660 // Analyze the branches, if any, at the end of the block. 661 MachineBasicBlock *TBB = nullptr, *FBB = nullptr; 662 SmallVector<MachineOperand, 4> Cond; 663 const TargetInstrInfo *TII = getParent()->getSubtarget().getInstrInfo(); 664 if (TII->AnalyzeBranch(*this, TBB, FBB, Cond)) { 665 // If we couldn't analyze the branch, examine the last instruction. 666 // If the block doesn't end in a known control barrier, assume fallthrough 667 // is possible. The isPredicated check is needed because this code can be 668 // called during IfConversion, where an instruction which is normally a 669 // Barrier is predicated and thus no longer an actual control barrier. 670 return empty() || !back().isBarrier() || TII->isPredicated(&back()); 671 } 672 673 // If there is no branch, control always falls through. 674 if (!TBB) return true; 675 676 // If there is some explicit branch to the fallthrough block, it can obviously 677 // reach, even though the branch should get folded to fall through implicitly. 678 if (MachineFunction::iterator(TBB) == Fallthrough || 679 MachineFunction::iterator(FBB) == Fallthrough) 680 return true; 681 682 // If it's an unconditional branch to some block not the fall through, it 683 // doesn't fall through. 684 if (Cond.empty()) return false; 685 686 // Otherwise, if it is conditional and has no explicit false block, it falls 687 // through. 688 return FBB == nullptr; 689 } 690 691 MachineBasicBlock * 692 MachineBasicBlock::SplitCriticalEdge(MachineBasicBlock *Succ, Pass *P) { 693 // Splitting the critical edge to a landing pad block is non-trivial. Don't do 694 // it in this generic function. 695 if (Succ->isEHPad()) 696 return nullptr; 697 698 MachineFunction *MF = getParent(); 699 DebugLoc dl; // FIXME: this is nowhere 700 701 // Performance might be harmed on HW that implements branching using exec mask 702 // where both sides of the branches are always executed. 703 if (MF->getTarget().requiresStructuredCFG()) 704 return nullptr; 705 706 // We may need to update this's terminator, but we can't do that if 707 // AnalyzeBranch fails. If this uses a jump table, we won't touch it. 708 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo(); 709 MachineBasicBlock *TBB = nullptr, *FBB = nullptr; 710 SmallVector<MachineOperand, 4> Cond; 711 if (TII->AnalyzeBranch(*this, TBB, FBB, Cond)) 712 return nullptr; 713 714 // Avoid bugpoint weirdness: A block may end with a conditional branch but 715 // jumps to the same MBB is either case. We have duplicate CFG edges in that 716 // case that we can't handle. Since this never happens in properly optimized 717 // code, just skip those edges. 718 if (TBB && TBB == FBB) { 719 DEBUG(dbgs() << "Won't split critical edge after degenerate BB#" 720 << getNumber() << '\n'); 721 return nullptr; 722 } 723 724 MachineBasicBlock *NMBB = MF->CreateMachineBasicBlock(); 725 MF->insert(std::next(MachineFunction::iterator(this)), NMBB); 726 DEBUG(dbgs() << "Splitting critical edge:" 727 " BB#" << getNumber() 728 << " -- BB#" << NMBB->getNumber() 729 << " -- BB#" << Succ->getNumber() << '\n'); 730 731 LiveIntervals *LIS = P->getAnalysisIfAvailable<LiveIntervals>(); 732 SlotIndexes *Indexes = P->getAnalysisIfAvailable<SlotIndexes>(); 733 if (LIS) 734 LIS->insertMBBInMaps(NMBB); 735 else if (Indexes) 736 Indexes->insertMBBInMaps(NMBB); 737 738 // On some targets like Mips, branches may kill virtual registers. Make sure 739 // that LiveVariables is properly updated after updateTerminator replaces the 740 // terminators. 741 LiveVariables *LV = P->getAnalysisIfAvailable<LiveVariables>(); 742 743 // Collect a list of virtual registers killed by the terminators. 744 SmallVector<unsigned, 4> KilledRegs; 745 if (LV) 746 for (instr_iterator I = getFirstInstrTerminator(), E = instr_end(); 747 I != E; ++I) { 748 MachineInstr *MI = I; 749 for (MachineInstr::mop_iterator OI = MI->operands_begin(), 750 OE = MI->operands_end(); OI != OE; ++OI) { 751 if (!OI->isReg() || OI->getReg() == 0 || 752 !OI->isUse() || !OI->isKill() || OI->isUndef()) 753 continue; 754 unsigned Reg = OI->getReg(); 755 if (TargetRegisterInfo::isPhysicalRegister(Reg) || 756 LV->getVarInfo(Reg).removeKill(MI)) { 757 KilledRegs.push_back(Reg); 758 DEBUG(dbgs() << "Removing terminator kill: " << *MI); 759 OI->setIsKill(false); 760 } 761 } 762 } 763 764 SmallVector<unsigned, 4> UsedRegs; 765 if (LIS) { 766 for (instr_iterator I = getFirstInstrTerminator(), E = instr_end(); 767 I != E; ++I) { 768 MachineInstr *MI = I; 769 770 for (MachineInstr::mop_iterator OI = MI->operands_begin(), 771 OE = MI->operands_end(); OI != OE; ++OI) { 772 if (!OI->isReg() || OI->getReg() == 0) 773 continue; 774 775 unsigned Reg = OI->getReg(); 776 if (std::find(UsedRegs.begin(), UsedRegs.end(), Reg) == UsedRegs.end()) 777 UsedRegs.push_back(Reg); 778 } 779 } 780 } 781 782 ReplaceUsesOfBlockWith(Succ, NMBB); 783 784 // If updateTerminator() removes instructions, we need to remove them from 785 // SlotIndexes. 786 SmallVector<MachineInstr*, 4> Terminators; 787 if (Indexes) { 788 for (instr_iterator I = getFirstInstrTerminator(), E = instr_end(); 789 I != E; ++I) 790 Terminators.push_back(I); 791 } 792 793 updateTerminator(); 794 795 if (Indexes) { 796 SmallVector<MachineInstr*, 4> NewTerminators; 797 for (instr_iterator I = getFirstInstrTerminator(), E = instr_end(); 798 I != E; ++I) 799 NewTerminators.push_back(I); 800 801 for (SmallVectorImpl<MachineInstr*>::iterator I = Terminators.begin(), 802 E = Terminators.end(); I != E; ++I) { 803 if (std::find(NewTerminators.begin(), NewTerminators.end(), *I) == 804 NewTerminators.end()) 805 Indexes->removeMachineInstrFromMaps(*I); 806 } 807 } 808 809 // Insert unconditional "jump Succ" instruction in NMBB if necessary. 810 NMBB->addSuccessor(Succ); 811 if (!NMBB->isLayoutSuccessor(Succ)) { 812 Cond.clear(); 813 TII->InsertBranch(*NMBB, Succ, nullptr, Cond, dl); 814 815 if (Indexes) { 816 for (instr_iterator I = NMBB->instr_begin(), E = NMBB->instr_end(); 817 I != E; ++I) { 818 // Some instructions may have been moved to NMBB by updateTerminator(), 819 // so we first remove any instruction that already has an index. 820 if (Indexes->hasIndex(I)) 821 Indexes->removeMachineInstrFromMaps(I); 822 Indexes->insertMachineInstrInMaps(I); 823 } 824 } 825 } 826 827 // Fix PHI nodes in Succ so they refer to NMBB instead of this 828 for (MachineBasicBlock::instr_iterator 829 i = Succ->instr_begin(),e = Succ->instr_end(); 830 i != e && i->isPHI(); ++i) 831 for (unsigned ni = 1, ne = i->getNumOperands(); ni != ne; ni += 2) 832 if (i->getOperand(ni+1).getMBB() == this) 833 i->getOperand(ni+1).setMBB(NMBB); 834 835 // Inherit live-ins from the successor 836 for (const auto &LI : Succ->liveins()) 837 NMBB->addLiveIn(LI); 838 839 // Update LiveVariables. 840 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo(); 841 if (LV) { 842 // Restore kills of virtual registers that were killed by the terminators. 843 while (!KilledRegs.empty()) { 844 unsigned Reg = KilledRegs.pop_back_val(); 845 for (instr_iterator I = instr_end(), E = instr_begin(); I != E;) { 846 if (!(--I)->addRegisterKilled(Reg, TRI, /* addIfNotFound= */ false)) 847 continue; 848 if (TargetRegisterInfo::isVirtualRegister(Reg)) 849 LV->getVarInfo(Reg).Kills.push_back(I); 850 DEBUG(dbgs() << "Restored terminator kill: " << *I); 851 break; 852 } 853 } 854 // Update relevant live-through information. 855 LV->addNewBlock(NMBB, this, Succ); 856 } 857 858 if (LIS) { 859 // After splitting the edge and updating SlotIndexes, live intervals may be 860 // in one of two situations, depending on whether this block was the last in 861 // the function. If the original block was the last in the function, all 862 // live intervals will end prior to the beginning of the new split block. If 863 // the original block was not at the end of the function, all live intervals 864 // will extend to the end of the new split block. 865 866 bool isLastMBB = 867 std::next(MachineFunction::iterator(NMBB)) == getParent()->end(); 868 869 SlotIndex StartIndex = Indexes->getMBBEndIdx(this); 870 SlotIndex PrevIndex = StartIndex.getPrevSlot(); 871 SlotIndex EndIndex = Indexes->getMBBEndIdx(NMBB); 872 873 // Find the registers used from NMBB in PHIs in Succ. 874 SmallSet<unsigned, 8> PHISrcRegs; 875 for (MachineBasicBlock::instr_iterator 876 I = Succ->instr_begin(), E = Succ->instr_end(); 877 I != E && I->isPHI(); ++I) { 878 for (unsigned ni = 1, ne = I->getNumOperands(); ni != ne; ni += 2) { 879 if (I->getOperand(ni+1).getMBB() == NMBB) { 880 MachineOperand &MO = I->getOperand(ni); 881 unsigned Reg = MO.getReg(); 882 PHISrcRegs.insert(Reg); 883 if (MO.isUndef()) 884 continue; 885 886 LiveInterval &LI = LIS->getInterval(Reg); 887 VNInfo *VNI = LI.getVNInfoAt(PrevIndex); 888 assert(VNI && 889 "PHI sources should be live out of their predecessors."); 890 LI.addSegment(LiveInterval::Segment(StartIndex, EndIndex, VNI)); 891 } 892 } 893 } 894 895 MachineRegisterInfo *MRI = &getParent()->getRegInfo(); 896 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) { 897 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); 898 if (PHISrcRegs.count(Reg) || !LIS->hasInterval(Reg)) 899 continue; 900 901 LiveInterval &LI = LIS->getInterval(Reg); 902 if (!LI.liveAt(PrevIndex)) 903 continue; 904 905 bool isLiveOut = LI.liveAt(LIS->getMBBStartIdx(Succ)); 906 if (isLiveOut && isLastMBB) { 907 VNInfo *VNI = LI.getVNInfoAt(PrevIndex); 908 assert(VNI && "LiveInterval should have VNInfo where it is live."); 909 LI.addSegment(LiveInterval::Segment(StartIndex, EndIndex, VNI)); 910 } else if (!isLiveOut && !isLastMBB) { 911 LI.removeSegment(StartIndex, EndIndex); 912 } 913 } 914 915 // Update all intervals for registers whose uses may have been modified by 916 // updateTerminator(). 917 LIS->repairIntervalsInRange(this, getFirstTerminator(), end(), UsedRegs); 918 } 919 920 if (MachineDominatorTree *MDT = 921 P->getAnalysisIfAvailable<MachineDominatorTree>()) 922 MDT->recordSplitCriticalEdge(this, Succ, NMBB); 923 924 if (MachineLoopInfo *MLI = P->getAnalysisIfAvailable<MachineLoopInfo>()) 925 if (MachineLoop *TIL = MLI->getLoopFor(this)) { 926 // If one or the other blocks were not in a loop, the new block is not 927 // either, and thus LI doesn't need to be updated. 928 if (MachineLoop *DestLoop = MLI->getLoopFor(Succ)) { 929 if (TIL == DestLoop) { 930 // Both in the same loop, the NMBB joins loop. 931 DestLoop->addBasicBlockToLoop(NMBB, MLI->getBase()); 932 } else if (TIL->contains(DestLoop)) { 933 // Edge from an outer loop to an inner loop. Add to the outer loop. 934 TIL->addBasicBlockToLoop(NMBB, MLI->getBase()); 935 } else if (DestLoop->contains(TIL)) { 936 // Edge from an inner loop to an outer loop. Add to the outer loop. 937 DestLoop->addBasicBlockToLoop(NMBB, MLI->getBase()); 938 } else { 939 // Edge from two loops with no containment relation. Because these 940 // are natural loops, we know that the destination block must be the 941 // header of its loop (adding a branch into a loop elsewhere would 942 // create an irreducible loop). 943 assert(DestLoop->getHeader() == Succ && 944 "Should not create irreducible loops!"); 945 if (MachineLoop *P = DestLoop->getParentLoop()) 946 P->addBasicBlockToLoop(NMBB, MLI->getBase()); 947 } 948 } 949 } 950 951 return NMBB; 952 } 953 954 /// Prepare MI to be removed from its bundle. This fixes bundle flags on MI's 955 /// neighboring instructions so the bundle won't be broken by removing MI. 956 static void unbundleSingleMI(MachineInstr *MI) { 957 // Removing the first instruction in a bundle. 958 if (MI->isBundledWithSucc() && !MI->isBundledWithPred()) 959 MI->unbundleFromSucc(); 960 // Removing the last instruction in a bundle. 961 if (MI->isBundledWithPred() && !MI->isBundledWithSucc()) 962 MI->unbundleFromPred(); 963 // If MI is not bundled, or if it is internal to a bundle, the neighbor flags 964 // are already fine. 965 } 966 967 MachineBasicBlock::instr_iterator 968 MachineBasicBlock::erase(MachineBasicBlock::instr_iterator I) { 969 unbundleSingleMI(I); 970 return Insts.erase(I); 971 } 972 973 MachineInstr *MachineBasicBlock::remove_instr(MachineInstr *MI) { 974 unbundleSingleMI(MI); 975 MI->clearFlag(MachineInstr::BundledPred); 976 MI->clearFlag(MachineInstr::BundledSucc); 977 return Insts.remove(MI); 978 } 979 980 MachineBasicBlock::instr_iterator 981 MachineBasicBlock::insert(instr_iterator I, MachineInstr *MI) { 982 assert(!MI->isBundledWithPred() && !MI->isBundledWithSucc() && 983 "Cannot insert instruction with bundle flags"); 984 // Set the bundle flags when inserting inside a bundle. 985 if (I != instr_end() && I->isBundledWithPred()) { 986 MI->setFlag(MachineInstr::BundledPred); 987 MI->setFlag(MachineInstr::BundledSucc); 988 } 989 return Insts.insert(I, MI); 990 } 991 992 /// This method unlinks 'this' from the containing function, and returns it, but 993 /// does not delete it. 994 MachineBasicBlock *MachineBasicBlock::removeFromParent() { 995 assert(getParent() && "Not embedded in a function!"); 996 getParent()->remove(this); 997 return this; 998 } 999 1000 /// This method unlinks 'this' from the containing function, and deletes it. 1001 void MachineBasicBlock::eraseFromParent() { 1002 assert(getParent() && "Not embedded in a function!"); 1003 getParent()->erase(this); 1004 } 1005 1006 /// Given a machine basic block that branched to 'Old', change the code and CFG 1007 /// so that it branches to 'New' instead. 1008 void MachineBasicBlock::ReplaceUsesOfBlockWith(MachineBasicBlock *Old, 1009 MachineBasicBlock *New) { 1010 assert(Old != New && "Cannot replace self with self!"); 1011 1012 MachineBasicBlock::instr_iterator I = instr_end(); 1013 while (I != instr_begin()) { 1014 --I; 1015 if (!I->isTerminator()) break; 1016 1017 // Scan the operands of this machine instruction, replacing any uses of Old 1018 // with New. 1019 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) 1020 if (I->getOperand(i).isMBB() && 1021 I->getOperand(i).getMBB() == Old) 1022 I->getOperand(i).setMBB(New); 1023 } 1024 1025 // Update the successor information. 1026 replaceSuccessor(Old, New); 1027 } 1028 1029 /// Various pieces of code can cause excess edges in the CFG to be inserted. If 1030 /// we have proven that MBB can only branch to DestA and DestB, remove any other 1031 /// MBB successors from the CFG. DestA and DestB can be null. 1032 /// 1033 /// Besides DestA and DestB, retain other edges leading to LandingPads 1034 /// (currently there can be only one; we don't check or require that here). 1035 /// Note it is possible that DestA and/or DestB are LandingPads. 1036 bool MachineBasicBlock::CorrectExtraCFGEdges(MachineBasicBlock *DestA, 1037 MachineBasicBlock *DestB, 1038 bool isCond) { 1039 // The values of DestA and DestB frequently come from a call to the 1040 // 'TargetInstrInfo::AnalyzeBranch' method. We take our meaning of the initial 1041 // values from there. 1042 // 1043 // 1. If both DestA and DestB are null, then the block ends with no branches 1044 // (it falls through to its successor). 1045 // 2. If DestA is set, DestB is null, and isCond is false, then the block ends 1046 // with only an unconditional branch. 1047 // 3. If DestA is set, DestB is null, and isCond is true, then the block ends 1048 // with a conditional branch that falls through to a successor (DestB). 1049 // 4. If DestA and DestB is set and isCond is true, then the block ends with a 1050 // conditional branch followed by an unconditional branch. DestA is the 1051 // 'true' destination and DestB is the 'false' destination. 1052 1053 bool Changed = false; 1054 1055 MachineFunction::iterator FallThru = 1056 std::next(MachineFunction::iterator(this)); 1057 1058 if (!DestA && !DestB) { 1059 // Block falls through to successor. 1060 DestA = FallThru; 1061 DestB = FallThru; 1062 } else if (DestA && !DestB) { 1063 if (isCond) 1064 // Block ends in conditional jump that falls through to successor. 1065 DestB = FallThru; 1066 } else { 1067 assert(DestA && DestB && isCond && 1068 "CFG in a bad state. Cannot correct CFG edges"); 1069 } 1070 1071 // Remove superfluous edges. I.e., those which aren't destinations of this 1072 // basic block, duplicate edges, or landing pads. 1073 SmallPtrSet<const MachineBasicBlock*, 8> SeenMBBs; 1074 MachineBasicBlock::succ_iterator SI = succ_begin(); 1075 while (SI != succ_end()) { 1076 const MachineBasicBlock *MBB = *SI; 1077 if (!SeenMBBs.insert(MBB).second || 1078 (MBB != DestA && MBB != DestB && !MBB->isEHPad())) { 1079 // This is a superfluous edge, remove it. 1080 SI = removeSuccessor(SI); 1081 Changed = true; 1082 } else { 1083 ++SI; 1084 } 1085 } 1086 1087 return Changed; 1088 } 1089 1090 /// Find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE 1091 /// instructions. Return UnknownLoc if there is none. 1092 DebugLoc 1093 MachineBasicBlock::findDebugLoc(instr_iterator MBBI) { 1094 DebugLoc DL; 1095 instr_iterator E = instr_end(); 1096 if (MBBI == E) 1097 return DL; 1098 1099 // Skip debug declarations, we don't want a DebugLoc from them. 1100 while (MBBI != E && MBBI->isDebugValue()) 1101 MBBI++; 1102 if (MBBI != E) 1103 DL = MBBI->getDebugLoc(); 1104 return DL; 1105 } 1106 1107 /// Return weight of the edge from this block to MBB. 1108 uint32_t MachineBasicBlock::getSuccWeight(const_succ_iterator Succ) const { 1109 if (Weights.empty()) 1110 return 0; 1111 1112 return *getWeightIterator(Succ); 1113 } 1114 1115 /// Set successor weight of a given iterator. 1116 void MachineBasicBlock::setSuccWeight(succ_iterator I, uint32_t weight) { 1117 if (Weights.empty()) 1118 return; 1119 *getWeightIterator(I) = weight; 1120 } 1121 1122 /// Return wight iterator corresonding to the I successor iterator. 1123 MachineBasicBlock::weight_iterator MachineBasicBlock:: 1124 getWeightIterator(MachineBasicBlock::succ_iterator I) { 1125 assert(Weights.size() == Successors.size() && "Async weight list!"); 1126 size_t index = std::distance(Successors.begin(), I); 1127 assert(index < Weights.size() && "Not a current successor!"); 1128 return Weights.begin() + index; 1129 } 1130 1131 /// Return wight iterator corresonding to the I successor iterator. 1132 MachineBasicBlock::const_weight_iterator MachineBasicBlock:: 1133 getWeightIterator(MachineBasicBlock::const_succ_iterator I) const { 1134 assert(Weights.size() == Successors.size() && "Async weight list!"); 1135 const size_t index = std::distance(Successors.begin(), I); 1136 assert(index < Weights.size() && "Not a current successor!"); 1137 return Weights.begin() + index; 1138 } 1139 1140 /// Return whether (physical) register "Reg" has been <def>ined and not <kill>ed 1141 /// as of just before "MI". 1142 /// 1143 /// Search is localised to a neighborhood of 1144 /// Neighborhood instructions before (searching for defs or kills) and N 1145 /// instructions after (searching just for defs) MI. 1146 MachineBasicBlock::LivenessQueryResult 1147 MachineBasicBlock::computeRegisterLiveness(const TargetRegisterInfo *TRI, 1148 unsigned Reg, const_iterator Before, 1149 unsigned Neighborhood) const { 1150 unsigned N = Neighborhood; 1151 1152 // Start by searching backwards from Before, looking for kills, reads or defs. 1153 const_iterator I(Before); 1154 // If this is the first insn in the block, don't search backwards. 1155 if (I != begin()) { 1156 do { 1157 --I; 1158 1159 MachineOperandIteratorBase::PhysRegInfo Analysis = 1160 ConstMIOperands(I).analyzePhysReg(Reg, TRI); 1161 1162 if (Analysis.Defines) 1163 // Outputs happen after inputs so they take precedence if both are 1164 // present. 1165 return Analysis.DefinesDead ? LQR_Dead : LQR_Live; 1166 1167 if (Analysis.Kills || Analysis.Clobbers) 1168 // Register killed, so isn't live. 1169 return LQR_Dead; 1170 1171 else if (Analysis.ReadsOverlap) 1172 // Defined or read without a previous kill - live. 1173 return Analysis.Reads ? LQR_Live : LQR_OverlappingLive; 1174 1175 } while (I != begin() && --N > 0); 1176 } 1177 1178 // Did we get to the start of the block? 1179 if (I == begin()) { 1180 // If so, the register's state is definitely defined by the live-in state. 1181 for (MCRegAliasIterator RAI(Reg, TRI, /*IncludeSelf=*/true); 1182 RAI.isValid(); ++RAI) { 1183 if (isLiveIn(*RAI)) 1184 return (*RAI == Reg) ? LQR_Live : LQR_OverlappingLive; 1185 } 1186 1187 return LQR_Dead; 1188 } 1189 1190 N = Neighborhood; 1191 1192 // Try searching forwards from Before, looking for reads or defs. 1193 I = const_iterator(Before); 1194 // If this is the last insn in the block, don't search forwards. 1195 if (I != end()) { 1196 for (++I; I != end() && N > 0; ++I, --N) { 1197 MachineOperandIteratorBase::PhysRegInfo Analysis = 1198 ConstMIOperands(I).analyzePhysReg(Reg, TRI); 1199 1200 if (Analysis.ReadsOverlap) 1201 // Used, therefore must have been live. 1202 return (Analysis.Reads) ? 1203 LQR_Live : LQR_OverlappingLive; 1204 1205 else if (Analysis.Clobbers || Analysis.Defines) 1206 // Defined (but not read) therefore cannot have been live. 1207 return LQR_Dead; 1208 } 1209 } 1210 1211 // At this point we have no idea of the liveness of the register. 1212 return LQR_Unknown; 1213 } 1214