1 //===-- LiveVariables.cpp - Live Variable Analysis for Machine Code -------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file was developed by the LLVM research group and is distributed under 6 // the University of Illinois Open Source License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the LiveVariable analysis pass. For each machine 11 // instruction in the function, this pass calculates the set of registers that 12 // are immediately dead after the instruction (i.e., the instruction calculates 13 // the value, but it is never used) and the set of registers that are used by 14 // the instruction, but are never used after the instruction (i.e., they are 15 // killed). 16 // 17 // This class computes live variables using are sparse implementation based on 18 // the machine code SSA form. This class computes live variable information for 19 // each virtual and _register allocatable_ physical register in a function. It 20 // uses the dominance properties of SSA form to efficiently compute live 21 // variables for virtual registers, and assumes that physical registers are only 22 // live within a single basic block (allowing it to do a single local analysis 23 // to resolve physical register lifetimes in each basic block). If a physical 24 // register is not register allocatable, it is not tracked. This is useful for 25 // things like the stack pointer and condition codes. 26 // 27 //===----------------------------------------------------------------------===// 28 29 #include "llvm/CodeGen/LiveVariables.h" 30 #include "llvm/CodeGen/MachineInstr.h" 31 #include "llvm/Target/TargetInstrInfo.h" 32 #include "llvm/Target/TargetMachine.h" 33 #include "llvm/Support/CFG.h" 34 #include "Support/DepthFirstIterator.h" 35 36 namespace llvm { 37 38 static RegisterAnalysis<LiveVariables> X("livevars", "Live Variable Analysis"); 39 40 const std::pair<MachineBasicBlock*, unsigned> & 41 LiveVariables::getMachineBasicBlockInfo(MachineBasicBlock *MBB) const{ 42 return BBMap.find(MBB->getBasicBlock())->second; 43 } 44 45 LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) { 46 assert(RegIdx >= MRegisterInfo::FirstVirtualRegister && 47 "getVarInfo: not a virtual register!"); 48 RegIdx -= MRegisterInfo::FirstVirtualRegister; 49 if (RegIdx >= VirtRegInfo.size()) { 50 if (RegIdx >= 2*VirtRegInfo.size()) 51 VirtRegInfo.resize(RegIdx*2); 52 else 53 VirtRegInfo.resize(2*VirtRegInfo.size()); 54 } 55 return VirtRegInfo[RegIdx]; 56 } 57 58 59 60 void LiveVariables::MarkVirtRegAliveInBlock(VarInfo &VRInfo, 61 const BasicBlock *BB) { 62 const std::pair<MachineBasicBlock*,unsigned> &Info = BBMap.find(BB)->second; 63 MachineBasicBlock *MBB = Info.first; 64 unsigned BBNum = Info.second; 65 66 // Check to see if this basic block is one of the killing blocks. If so, 67 // remove it... 68 for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i) 69 if (VRInfo.Kills[i].first == MBB) { 70 VRInfo.Kills.erase(VRInfo.Kills.begin()+i); // Erase entry 71 break; 72 } 73 74 if (MBB == VRInfo.DefBlock) return; // Terminate recursion 75 76 if (VRInfo.AliveBlocks.size() <= BBNum) 77 VRInfo.AliveBlocks.resize(BBNum+1); // Make space... 78 79 if (VRInfo.AliveBlocks[BBNum]) 80 return; // We already know the block is live 81 82 // Mark the variable known alive in this bb 83 VRInfo.AliveBlocks[BBNum] = true; 84 85 for (pred_const_iterator PI = pred_begin(BB), E = pred_end(BB); PI != E; ++PI) 86 MarkVirtRegAliveInBlock(VRInfo, *PI); 87 } 88 89 void LiveVariables::HandleVirtRegUse(VarInfo &VRInfo, MachineBasicBlock *MBB, 90 MachineInstr *MI) { 91 // Check to see if this basic block is already a kill block... 92 if (!VRInfo.Kills.empty() && VRInfo.Kills.back().first == MBB) { 93 // Yes, this register is killed in this basic block already. Increase the 94 // live range by updating the kill instruction. 95 VRInfo.Kills.back().second = MI; 96 return; 97 } 98 99 #ifndef NDEBUG 100 for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i) 101 assert(VRInfo.Kills[i].first != MBB && "entry should be at end!"); 102 #endif 103 104 assert(MBB != VRInfo.DefBlock && "Should have kill for defblock!"); 105 106 // Add a new kill entry for this basic block. 107 VRInfo.Kills.push_back(std::make_pair(MBB, MI)); 108 109 // Update all dominating blocks to mark them known live. 110 const BasicBlock *BB = MBB->getBasicBlock(); 111 for (pred_const_iterator PI = pred_begin(BB), E = pred_end(BB); 112 PI != E; ++PI) 113 MarkVirtRegAliveInBlock(VRInfo, *PI); 114 } 115 116 void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) { 117 if (PhysRegInfo[Reg]) { 118 PhysRegInfo[Reg] = MI; 119 PhysRegUsed[Reg] = true; 120 } 121 } 122 123 void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI) { 124 // Does this kill a previous version of this register? 125 if (MachineInstr *LastUse = PhysRegInfo[Reg]) { 126 if (PhysRegUsed[Reg]) 127 RegistersKilled.insert(std::make_pair(LastUse, Reg)); 128 else 129 RegistersDead.insert(std::make_pair(LastUse, Reg)); 130 } 131 PhysRegInfo[Reg] = MI; 132 PhysRegUsed[Reg] = false; 133 134 for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg); 135 *AliasSet; ++AliasSet) { 136 if (MachineInstr *LastUse = PhysRegInfo[*AliasSet]) { 137 if (PhysRegUsed[*AliasSet]) 138 RegistersKilled.insert(std::make_pair(LastUse, *AliasSet)); 139 else 140 RegistersDead.insert(std::make_pair(LastUse, *AliasSet)); 141 } 142 PhysRegInfo[*AliasSet] = MI; 143 PhysRegUsed[*AliasSet] = false; 144 } 145 } 146 147 bool LiveVariables::runOnMachineFunction(MachineFunction &MF) { 148 // First time though, initialize AllocatablePhysicalRegisters for the target 149 if (AllocatablePhysicalRegisters.empty()) { 150 const MRegisterInfo &MRI = *MF.getTarget().getRegisterInfo(); 151 assert(&MRI && "Target doesn't have register information?"); 152 153 // Make space, initializing to false... 154 AllocatablePhysicalRegisters.resize(MRegisterInfo::FirstVirtualRegister); 155 156 // Loop over all of the register classes... 157 for (MRegisterInfo::regclass_iterator RCI = MRI.regclass_begin(), 158 E = MRI.regclass_end(); RCI != E; ++RCI) 159 // Loop over all of the allocatable registers in the function... 160 for (TargetRegisterClass::iterator I = (*RCI)->allocation_order_begin(MF), 161 E = (*RCI)->allocation_order_end(MF); I != E; ++I) 162 AllocatablePhysicalRegisters[*I] = true; // The reg is allocatable! 163 } 164 165 // Build BBMap... 166 unsigned BBNum = 0; 167 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) 168 BBMap[I->getBasicBlock()] = std::make_pair(I, BBNum++); 169 170 // PhysRegInfo - Keep track of which instruction was the last use of a 171 // physical register. This is a purely local property, because all physical 172 // register references as presumed dead across basic blocks. 173 // 174 MachineInstr *PhysRegInfoA[MRegisterInfo::FirstVirtualRegister]; 175 bool PhysRegUsedA[MRegisterInfo::FirstVirtualRegister]; 176 std::fill(PhysRegInfoA, PhysRegInfoA+MRegisterInfo::FirstVirtualRegister, 177 (MachineInstr*)0); 178 PhysRegInfo = PhysRegInfoA; 179 PhysRegUsed = PhysRegUsedA; 180 181 const TargetInstrInfo &TII = MF.getTarget().getInstrInfo(); 182 RegInfo = MF.getTarget().getRegisterInfo(); 183 184 /// Get some space for a respectable number of registers... 185 VirtRegInfo.resize(64); 186 187 // Calculate live variable information in depth first order on the CFG of the 188 // function. This guarantees that we will see the definition of a virtual 189 // register before its uses due to dominance properties of SSA (except for PHI 190 // nodes, which are treated as a special case). 191 // 192 const BasicBlock *Entry = MF.getFunction()->begin(); 193 for (df_iterator<const BasicBlock*> DFI = df_begin(Entry), E = df_end(Entry); 194 DFI != E; ++DFI) { 195 const BasicBlock *BB = *DFI; 196 std::pair<MachineBasicBlock*, unsigned> &BBRec = BBMap.find(BB)->second; 197 MachineBasicBlock *MBB = BBRec.first; 198 unsigned BBNum = BBRec.second; 199 200 // Loop over all of the instructions, processing them. 201 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); 202 I != E; ++I) { 203 MachineInstr *MI = *I; 204 const TargetInstrDescriptor &MID = TII.get(MI->getOpcode()); 205 206 // Process all of the operands of the instruction... 207 unsigned NumOperandsToProcess = MI->getNumOperands(); 208 209 // Unless it is a PHI node. In this case, ONLY process the DEF, not any 210 // of the uses. They will be handled in other basic blocks. 211 if (MI->getOpcode() == TargetInstrInfo::PHI) 212 NumOperandsToProcess = 1; 213 214 // Loop over implicit uses, using them. 215 for (const unsigned *ImplicitUses = MID.ImplicitUses; 216 *ImplicitUses; ++ImplicitUses) 217 HandlePhysRegUse(*ImplicitUses, MI); 218 219 // Process all explicit uses... 220 for (unsigned i = 0; i != NumOperandsToProcess; ++i) { 221 MachineOperand &MO = MI->getOperand(i); 222 if (MO.isUse()) { 223 if (MO.isVirtualRegister() && !MO.getVRegValueOrNull()) { 224 HandleVirtRegUse(getVarInfo(MO.getReg()), MBB, MI); 225 } else if (MO.isPhysicalRegister() && 226 AllocatablePhysicalRegisters[MO.getReg()]) { 227 HandlePhysRegUse(MO.getReg(), MI); 228 } 229 } 230 } 231 232 // Loop over implicit defs, defining them. 233 for (const unsigned *ImplicitDefs = MID.ImplicitDefs; 234 *ImplicitDefs; ++ImplicitDefs) 235 HandlePhysRegDef(*ImplicitDefs, MI); 236 237 // Process all explicit defs... 238 for (unsigned i = 0; i != NumOperandsToProcess; ++i) { 239 MachineOperand &MO = MI->getOperand(i); 240 if (MO.isDef()) { 241 if (MO.isVirtualRegister()) { 242 VarInfo &VRInfo = getVarInfo(MO.getReg()); 243 244 assert(VRInfo.DefBlock == 0 && "Variable multiply defined!"); 245 VRInfo.DefBlock = MBB; // Created here... 246 VRInfo.DefInst = MI; 247 VRInfo.Kills.push_back(std::make_pair(MBB, MI)); // Defaults to dead 248 } else if (MO.isPhysicalRegister() && 249 AllocatablePhysicalRegisters[MO.getReg()]) { 250 HandlePhysRegDef(MO.getReg(), MI); 251 } 252 } 253 } 254 } 255 256 // Handle any virtual assignments from PHI nodes which might be at the 257 // bottom of this basic block. We check all of our successor blocks to see 258 // if they have PHI nodes, and if so, we simulate an assignment at the end 259 // of the current block. 260 for (succ_const_iterator SI = succ_begin(BB), E = succ_end(BB); 261 SI != E; ++SI) { 262 MachineBasicBlock *Succ = BBMap.find(*SI)->second.first; 263 264 // PHI nodes are guaranteed to be at the top of the block... 265 for (MachineBasicBlock::iterator I = Succ->begin(), E = Succ->end(); 266 I != E && (*I)->getOpcode() == TargetInstrInfo::PHI; ++I) { 267 MachineInstr *MI = *I; 268 for (unsigned i = 1; ; i += 2) 269 if (MI->getOperand(i+1).getMachineBasicBlock() == MBB) { 270 MachineOperand &MO = MI->getOperand(i); 271 if (!MO.getVRegValueOrNull()) { 272 VarInfo &VRInfo = getVarInfo(MO.getReg()); 273 274 // Only mark it alive only in the block we are representing... 275 MarkVirtRegAliveInBlock(VRInfo, BB); 276 break; // Found the PHI entry for this block... 277 } 278 } 279 } 280 } 281 282 // Loop over PhysRegInfo, killing any registers that are available at the 283 // end of the basic block. This also resets the PhysRegInfo map. 284 for (unsigned i = 0, e = MRegisterInfo::FirstVirtualRegister; i != e; ++i) 285 if (PhysRegInfo[i]) 286 HandlePhysRegDef(i, 0); 287 } 288 289 // Convert the information we have gathered into VirtRegInfo and transform it 290 // into a form usable by RegistersKilled. 291 // 292 for (unsigned i = 0, e = VirtRegInfo.size(); i != e; ++i) 293 for (unsigned j = 0, e = VirtRegInfo[i].Kills.size(); j != e; ++j) { 294 if (VirtRegInfo[i].Kills[j].second == VirtRegInfo[i].DefInst) 295 RegistersDead.insert(std::make_pair(VirtRegInfo[i].Kills[j].second, 296 i + MRegisterInfo::FirstVirtualRegister)); 297 298 else 299 RegistersKilled.insert(std::make_pair(VirtRegInfo[i].Kills[j].second, 300 i + MRegisterInfo::FirstVirtualRegister)); 301 } 302 303 return false; 304 } 305 306 } // End llvm namespace 307