1 //===-------- InlineSpiller.cpp - Insert spills and restores inline -------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // The inline spiller modifies the machine function directly instead of 11 // inserting spills and restores in VirtRegMap. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #define DEBUG_TYPE "spiller" 16 #include "Spiller.h" 17 #include "VirtRegMap.h" 18 #include "llvm/CodeGen/LiveIntervalAnalysis.h" 19 #include "llvm/CodeGen/MachineFrameInfo.h" 20 #include "llvm/CodeGen/MachineFunction.h" 21 #include "llvm/CodeGen/MachineRegisterInfo.h" 22 #include "llvm/Target/TargetMachine.h" 23 #include "llvm/Target/TargetInstrInfo.h" 24 #include "llvm/Support/Debug.h" 25 #include "llvm/Support/raw_ostream.h" 26 27 using namespace llvm; 28 29 namespace { 30 class InlineSpiller : public Spiller { 31 MachineFunction &mf_; 32 LiveIntervals &lis_; 33 VirtRegMap &vrm_; 34 MachineFrameInfo &mfi_; 35 MachineRegisterInfo &mri_; 36 const TargetInstrInfo &tii_; 37 const TargetRegisterInfo &tri_; 38 39 ~InlineSpiller() {} 40 41 public: 42 InlineSpiller(MachineFunction *mf, LiveIntervals *lis, VirtRegMap *vrm) 43 : mf_(*mf), lis_(*lis), vrm_(*vrm), 44 mfi_(*mf->getFrameInfo()), 45 mri_(mf->getRegInfo()), 46 tii_(*mf->getTarget().getInstrInfo()), 47 tri_(*mf->getTarget().getRegisterInfo()) {} 48 49 void spill(LiveInterval *li, 50 std::vector<LiveInterval*> &newIntervals, 51 SmallVectorImpl<LiveInterval*> &spillIs, 52 SlotIndex *earliestIndex); 53 }; 54 } 55 56 namespace llvm { 57 Spiller *createInlineSpiller(MachineFunction *mf, 58 LiveIntervals *lis, 59 const MachineLoopInfo *mli, 60 VirtRegMap *vrm) { 61 return new InlineSpiller(mf, lis, vrm); 62 } 63 } 64 65 void InlineSpiller::spill(LiveInterval *li, 66 std::vector<LiveInterval*> &newIntervals, 67 SmallVectorImpl<LiveInterval*> &spillIs, 68 SlotIndex *earliestIndex) { 69 DEBUG(dbgs() << "Inline spilling " << *li << "\n"); 70 assert(li->isSpillable() && "Attempting to spill already spilled value."); 71 assert(!li->isStackSlot() && "Trying to spill a stack slot."); 72 73 const TargetRegisterClass *RC = mri_.getRegClass(li->reg); 74 unsigned SS = vrm_.assignVirt2StackSlot(li->reg); 75 76 for (MachineRegisterInfo::reg_iterator RI = mri_.reg_begin(li->reg); 77 MachineInstr *MI = RI.skipInstruction();) { 78 SlotIndex Idx = lis_.getInstructionIndex(MI).getDefIndex(); 79 80 // Analyze instruction. 81 bool Reads, Writes; 82 SmallVector<unsigned, 8> Ops; 83 tie(Reads, Writes) = MI->readsWritesVirtualRegister(li->reg, &Ops); 84 85 // Allocate interval around instruction. 86 // FIXME: Infer regclass from instruction alone. 87 unsigned NewVReg = mri_.createVirtualRegister(RC); 88 vrm_.grow(); 89 LiveInterval &NewLI = lis_.getOrCreateInterval(NewVReg); 90 NewLI.markNotSpillable(); 91 92 // Reload if instruction reads register. 93 if (Reads) { 94 MachineBasicBlock::iterator MII = MI; 95 tii_.loadRegFromStackSlot(*MI->getParent(), MII, NewVReg, SS, RC, &tri_); 96 --MII; // Point to load instruction. 97 SlotIndex LoadIdx = lis_.InsertMachineInstrInMaps(MII).getDefIndex(); 98 vrm_.addSpillSlotUse(SS, MII); 99 DEBUG(dbgs() << "\treload: " << LoadIdx << '\t' << *MII); 100 VNInfo *LoadVNI = NewLI.getNextValue(LoadIdx, 0, true, 101 lis_.getVNInfoAllocator()); 102 NewLI.addRange(LiveRange(LoadIdx, Idx, LoadVNI)); 103 } 104 105 // Rewrite instruction operands. 106 bool hasLiveDef = false; 107 for (unsigned i = 0, e = Ops.size(); i != e; ++i) { 108 MachineOperand &MO = MI->getOperand(Ops[i]); 109 MO.setReg(NewVReg); 110 if (MO.isUse()) { 111 if (!MI->isRegTiedToDefOperand(Ops[i])) 112 MO.setIsKill(); 113 } else { 114 if (!MO.isDead()) 115 hasLiveDef = true; 116 } 117 } 118 DEBUG(dbgs() << "\trewrite: " << Idx << '\t' << *MI); 119 120 // Spill is instruction writes register. 121 // FIXME: Use a second vreg if instruction has no tied ops. 122 if (Writes && hasLiveDef) { 123 MachineBasicBlock::iterator MII = MI; 124 tii_.storeRegToStackSlot(*MI->getParent(), ++MII, NewVReg, true, SS, RC, 125 &tri_); 126 --MII; // Point to store instruction. 127 SlotIndex StoreIdx = lis_.InsertMachineInstrInMaps(MII).getDefIndex(); 128 vrm_.addSpillSlotUse(SS, MII); 129 DEBUG(dbgs() << "\tspilled: " << StoreIdx << '\t' << *MII); 130 VNInfo *StoreVNI = NewLI.getNextValue(Idx, 0, true, 131 lis_.getVNInfoAllocator()); 132 NewLI.addRange(LiveRange(Idx, StoreIdx, StoreVNI)); 133 } 134 135 DEBUG(dbgs() << "\tinterval: " << NewLI << '\n'); 136 newIntervals.push_back(&NewLI); 137 } 138 } 139