1 //===- llvm/CodeGen/GlobalISel/Utils.cpp -------------------------*- C++ -*-==// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file This file implements the utility functions used by the GlobalISel 9 /// pipeline. 10 //===----------------------------------------------------------------------===// 11 12 #include "llvm/CodeGen/GlobalISel/Utils.h" 13 #include "llvm/ADT/APFloat.h" 14 #include "llvm/ADT/Twine.h" 15 #include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h" 16 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h" 17 #include "llvm/CodeGen/MachineInstr.h" 18 #include "llvm/CodeGen/MachineInstrBuilder.h" 19 #include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h" 20 #include "llvm/CodeGen/MachineRegisterInfo.h" 21 #include "llvm/CodeGen/StackProtector.h" 22 #include "llvm/CodeGen/TargetInstrInfo.h" 23 #include "llvm/CodeGen/TargetPassConfig.h" 24 #include "llvm/CodeGen/TargetRegisterInfo.h" 25 #include "llvm/IR/Constants.h" 26 27 #define DEBUG_TYPE "globalisel-utils" 28 29 using namespace llvm; 30 31 Register llvm::constrainRegToClass(MachineRegisterInfo &MRI, 32 const TargetInstrInfo &TII, 33 const RegisterBankInfo &RBI, Register Reg, 34 const TargetRegisterClass &RegClass) { 35 if (!RBI.constrainGenericRegister(Reg, RegClass, MRI)) 36 return MRI.createVirtualRegister(&RegClass); 37 38 return Reg; 39 } 40 41 Register llvm::constrainOperandRegClass( 42 const MachineFunction &MF, const TargetRegisterInfo &TRI, 43 MachineRegisterInfo &MRI, const TargetInstrInfo &TII, 44 const RegisterBankInfo &RBI, MachineInstr &InsertPt, 45 const TargetRegisterClass &RegClass, const MachineOperand &RegMO) { 46 Register Reg = RegMO.getReg(); 47 // Assume physical registers are properly constrained. 48 assert(Register::isVirtualRegister(Reg) && "PhysReg not implemented"); 49 50 Register ConstrainedReg = constrainRegToClass(MRI, TII, RBI, Reg, RegClass); 51 // If we created a new virtual register because the class is not compatible 52 // then create a copy between the new and the old register. 53 if (ConstrainedReg != Reg) { 54 MachineBasicBlock::iterator InsertIt(&InsertPt); 55 MachineBasicBlock &MBB = *InsertPt.getParent(); 56 if (RegMO.isUse()) { 57 BuildMI(MBB, InsertIt, InsertPt.getDebugLoc(), 58 TII.get(TargetOpcode::COPY), ConstrainedReg) 59 .addReg(Reg); 60 } else { 61 assert(RegMO.isDef() && "Must be a definition"); 62 BuildMI(MBB, std::next(InsertIt), InsertPt.getDebugLoc(), 63 TII.get(TargetOpcode::COPY), Reg) 64 .addReg(ConstrainedReg); 65 } 66 } else { 67 if (GISelChangeObserver *Observer = MF.getObserver()) { 68 if (!RegMO.isDef()) { 69 MachineInstr *RegDef = MRI.getVRegDef(Reg); 70 Observer->changedInstr(*RegDef); 71 } 72 Observer->changingAllUsesOfReg(MRI, Reg); 73 Observer->finishedChangingAllUsesOfReg(); 74 } 75 } 76 return ConstrainedReg; 77 } 78 79 Register llvm::constrainOperandRegClass( 80 const MachineFunction &MF, const TargetRegisterInfo &TRI, 81 MachineRegisterInfo &MRI, const TargetInstrInfo &TII, 82 const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II, 83 const MachineOperand &RegMO, unsigned OpIdx) { 84 Register Reg = RegMO.getReg(); 85 // Assume physical registers are properly constrained. 86 assert(Register::isVirtualRegister(Reg) && "PhysReg not implemented"); 87 88 const TargetRegisterClass *RegClass = TII.getRegClass(II, OpIdx, &TRI, MF); 89 // Some of the target independent instructions, like COPY, may not impose any 90 // register class constraints on some of their operands: If it's a use, we can 91 // skip constraining as the instruction defining the register would constrain 92 // it. 93 94 // We can't constrain unallocatable register classes, because we can't create 95 // virtual registers for these classes, so we need to let targets handled this 96 // case. 97 if (RegClass && !RegClass->isAllocatable()) 98 RegClass = TRI.getConstrainedRegClassForOperand(RegMO, MRI); 99 100 if (!RegClass) { 101 assert((!isTargetSpecificOpcode(II.getOpcode()) || RegMO.isUse()) && 102 "Register class constraint is required unless either the " 103 "instruction is target independent or the operand is a use"); 104 // FIXME: Just bailing out like this here could be not enough, unless we 105 // expect the users of this function to do the right thing for PHIs and 106 // COPY: 107 // v1 = COPY v0 108 // v2 = COPY v1 109 // v1 here may end up not being constrained at all. Please notice that to 110 // reproduce the issue we likely need a destination pattern of a selection 111 // rule producing such extra copies, not just an input GMIR with them as 112 // every existing target using selectImpl handles copies before calling it 113 // and they never reach this function. 114 return Reg; 115 } 116 return constrainOperandRegClass(MF, TRI, MRI, TII, RBI, InsertPt, *RegClass, 117 RegMO); 118 } 119 120 bool llvm::constrainSelectedInstRegOperands(MachineInstr &I, 121 const TargetInstrInfo &TII, 122 const TargetRegisterInfo &TRI, 123 const RegisterBankInfo &RBI) { 124 assert(!isPreISelGenericOpcode(I.getOpcode()) && 125 "A selected instruction is expected"); 126 MachineBasicBlock &MBB = *I.getParent(); 127 MachineFunction &MF = *MBB.getParent(); 128 MachineRegisterInfo &MRI = MF.getRegInfo(); 129 130 for (unsigned OpI = 0, OpE = I.getNumExplicitOperands(); OpI != OpE; ++OpI) { 131 MachineOperand &MO = I.getOperand(OpI); 132 133 // There's nothing to be done on non-register operands. 134 if (!MO.isReg()) 135 continue; 136 137 LLVM_DEBUG(dbgs() << "Converting operand: " << MO << '\n'); 138 assert(MO.isReg() && "Unsupported non-reg operand"); 139 140 Register Reg = MO.getReg(); 141 // Physical registers don't need to be constrained. 142 if (Register::isPhysicalRegister(Reg)) 143 continue; 144 145 // Register operands with a value of 0 (e.g. predicate operands) don't need 146 // to be constrained. 147 if (Reg == 0) 148 continue; 149 150 // If the operand is a vreg, we should constrain its regclass, and only 151 // insert COPYs if that's impossible. 152 // constrainOperandRegClass does that for us. 153 MO.setReg(constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, I.getDesc(), 154 MO, OpI)); 155 156 // Tie uses to defs as indicated in MCInstrDesc if this hasn't already been 157 // done. 158 if (MO.isUse()) { 159 int DefIdx = I.getDesc().getOperandConstraint(OpI, MCOI::TIED_TO); 160 if (DefIdx != -1 && !I.isRegTiedToUseOperand(DefIdx)) 161 I.tieOperands(DefIdx, OpI); 162 } 163 } 164 return true; 165 } 166 167 bool llvm::canReplaceReg(Register DstReg, Register SrcReg, 168 MachineRegisterInfo &MRI) { 169 // Give up if either DstReg or SrcReg is a physical register. 170 if (DstReg.isPhysical() || SrcReg.isPhysical()) 171 return false; 172 // Give up if the types don't match. 173 if (MRI.getType(DstReg) != MRI.getType(SrcReg)) 174 return false; 175 // Replace if either DstReg has no constraints or the register 176 // constraints match. 177 return !MRI.getRegClassOrRegBank(DstReg) || 178 MRI.getRegClassOrRegBank(DstReg) == MRI.getRegClassOrRegBank(SrcReg); 179 } 180 181 bool llvm::isTriviallyDead(const MachineInstr &MI, 182 const MachineRegisterInfo &MRI) { 183 // FIXME: This logical is mostly duplicated with 184 // DeadMachineInstructionElim::isDead. Why is LOCAL_ESCAPE not considered in 185 // MachineInstr::isLabel? 186 187 // Don't delete frame allocation labels. 188 if (MI.getOpcode() == TargetOpcode::LOCAL_ESCAPE) 189 return false; 190 191 // If we can move an instruction, we can remove it. Otherwise, it has 192 // a side-effect of some sort. 193 bool SawStore = false; 194 if (!MI.isSafeToMove(/*AA=*/nullptr, SawStore) && !MI.isPHI()) 195 return false; 196 197 // Instructions without side-effects are dead iff they only define dead vregs. 198 for (auto &MO : MI.operands()) { 199 if (!MO.isReg() || !MO.isDef()) 200 continue; 201 202 Register Reg = MO.getReg(); 203 if (Register::isPhysicalRegister(Reg) || !MRI.use_nodbg_empty(Reg)) 204 return false; 205 } 206 return true; 207 } 208 209 static void reportGISelDiagnostic(DiagnosticSeverity Severity, 210 MachineFunction &MF, 211 const TargetPassConfig &TPC, 212 MachineOptimizationRemarkEmitter &MORE, 213 MachineOptimizationRemarkMissed &R) { 214 bool IsFatal = Severity == DS_Error && 215 TPC.isGlobalISelAbortEnabled(); 216 // Print the function name explicitly if we don't have a debug location (which 217 // makes the diagnostic less useful) or if we're going to emit a raw error. 218 if (!R.getLocation().isValid() || IsFatal) 219 R << (" (in function: " + MF.getName() + ")").str(); 220 221 if (IsFatal) 222 report_fatal_error(R.getMsg()); 223 else 224 MORE.emit(R); 225 } 226 227 void llvm::reportGISelWarning(MachineFunction &MF, const TargetPassConfig &TPC, 228 MachineOptimizationRemarkEmitter &MORE, 229 MachineOptimizationRemarkMissed &R) { 230 reportGISelDiagnostic(DS_Warning, MF, TPC, MORE, R); 231 } 232 233 void llvm::reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, 234 MachineOptimizationRemarkEmitter &MORE, 235 MachineOptimizationRemarkMissed &R) { 236 MF.getProperties().set(MachineFunctionProperties::Property::FailedISel); 237 reportGISelDiagnostic(DS_Error, MF, TPC, MORE, R); 238 } 239 240 void llvm::reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, 241 MachineOptimizationRemarkEmitter &MORE, 242 const char *PassName, StringRef Msg, 243 const MachineInstr &MI) { 244 MachineOptimizationRemarkMissed R(PassName, "GISelFailure: ", 245 MI.getDebugLoc(), MI.getParent()); 246 R << Msg; 247 // Printing MI is expensive; only do it if expensive remarks are enabled. 248 if (TPC.isGlobalISelAbortEnabled() || MORE.allowExtraAnalysis(PassName)) 249 R << ": " << ore::MNV("Inst", MI); 250 reportGISelFailure(MF, TPC, MORE, R); 251 } 252 253 Optional<int64_t> llvm::getConstantVRegVal(Register VReg, 254 const MachineRegisterInfo &MRI) { 255 Optional<ValueAndVReg> ValAndVReg = 256 getConstantVRegValWithLookThrough(VReg, MRI, /*LookThroughInstrs*/ false); 257 assert((!ValAndVReg || ValAndVReg->VReg == VReg) && 258 "Value found while looking through instrs"); 259 if (!ValAndVReg) 260 return None; 261 return ValAndVReg->Value; 262 } 263 264 Optional<ValueAndVReg> llvm::getConstantVRegValWithLookThrough( 265 Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs, 266 bool HandleFConstant) { 267 SmallVector<std::pair<unsigned, unsigned>, 4> SeenOpcodes; 268 MachineInstr *MI; 269 auto IsConstantOpcode = [HandleFConstant](unsigned Opcode) { 270 return Opcode == TargetOpcode::G_CONSTANT || 271 (HandleFConstant && Opcode == TargetOpcode::G_FCONSTANT); 272 }; 273 auto GetImmediateValue = [HandleFConstant, 274 &MRI](const MachineInstr &MI) -> Optional<APInt> { 275 const MachineOperand &CstVal = MI.getOperand(1); 276 if (!CstVal.isImm() && !CstVal.isCImm() && 277 (!HandleFConstant || !CstVal.isFPImm())) 278 return None; 279 if (!CstVal.isFPImm()) { 280 unsigned BitWidth = 281 MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); 282 APInt Val = CstVal.isImm() ? APInt(BitWidth, CstVal.getImm()) 283 : CstVal.getCImm()->getValue(); 284 assert(Val.getBitWidth() == BitWidth && 285 "Value bitwidth doesn't match definition type"); 286 return Val; 287 } 288 return CstVal.getFPImm()->getValueAPF().bitcastToAPInt(); 289 }; 290 while ((MI = MRI.getVRegDef(VReg)) && !IsConstantOpcode(MI->getOpcode()) && 291 LookThroughInstrs) { 292 switch (MI->getOpcode()) { 293 case TargetOpcode::G_TRUNC: 294 case TargetOpcode::G_SEXT: 295 case TargetOpcode::G_ZEXT: 296 SeenOpcodes.push_back(std::make_pair( 297 MI->getOpcode(), 298 MRI.getType(MI->getOperand(0).getReg()).getSizeInBits())); 299 VReg = MI->getOperand(1).getReg(); 300 break; 301 case TargetOpcode::COPY: 302 VReg = MI->getOperand(1).getReg(); 303 if (Register::isPhysicalRegister(VReg)) 304 return None; 305 break; 306 case TargetOpcode::G_INTTOPTR: 307 VReg = MI->getOperand(1).getReg(); 308 break; 309 default: 310 return None; 311 } 312 } 313 if (!MI || !IsConstantOpcode(MI->getOpcode())) 314 return None; 315 316 Optional<APInt> MaybeVal = GetImmediateValue(*MI); 317 if (!MaybeVal) 318 return None; 319 APInt &Val = *MaybeVal; 320 while (!SeenOpcodes.empty()) { 321 std::pair<unsigned, unsigned> OpcodeAndSize = SeenOpcodes.pop_back_val(); 322 switch (OpcodeAndSize.first) { 323 case TargetOpcode::G_TRUNC: 324 Val = Val.trunc(OpcodeAndSize.second); 325 break; 326 case TargetOpcode::G_SEXT: 327 Val = Val.sext(OpcodeAndSize.second); 328 break; 329 case TargetOpcode::G_ZEXT: 330 Val = Val.zext(OpcodeAndSize.second); 331 break; 332 } 333 } 334 335 if (Val.getBitWidth() > 64) 336 return None; 337 338 return ValueAndVReg{Val.getSExtValue(), VReg}; 339 } 340 341 const llvm::ConstantFP * 342 llvm::getConstantFPVRegVal(Register VReg, const MachineRegisterInfo &MRI) { 343 MachineInstr *MI = MRI.getVRegDef(VReg); 344 if (TargetOpcode::G_FCONSTANT != MI->getOpcode()) 345 return nullptr; 346 return MI->getOperand(1).getFPImm(); 347 } 348 349 namespace { 350 struct DefinitionAndSourceRegister { 351 llvm::MachineInstr *MI; 352 Register Reg; 353 }; 354 } // namespace 355 356 static llvm::Optional<DefinitionAndSourceRegister> 357 getDefSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI) { 358 Register DefSrcReg = Reg; 359 auto *DefMI = MRI.getVRegDef(Reg); 360 auto DstTy = MRI.getType(DefMI->getOperand(0).getReg()); 361 if (!DstTy.isValid()) 362 return None; 363 while (DefMI->getOpcode() == TargetOpcode::COPY) { 364 Register SrcReg = DefMI->getOperand(1).getReg(); 365 auto SrcTy = MRI.getType(SrcReg); 366 if (!SrcTy.isValid() || SrcTy != DstTy) 367 break; 368 DefMI = MRI.getVRegDef(SrcReg); 369 DefSrcReg = SrcReg; 370 } 371 return DefinitionAndSourceRegister{DefMI, DefSrcReg}; 372 } 373 374 llvm::MachineInstr *llvm::getDefIgnoringCopies(Register Reg, 375 const MachineRegisterInfo &MRI) { 376 Optional<DefinitionAndSourceRegister> DefSrcReg = 377 getDefSrcRegIgnoringCopies(Reg, MRI); 378 return DefSrcReg ? DefSrcReg->MI : nullptr; 379 } 380 381 Register llvm::getSrcRegIgnoringCopies(Register Reg, 382 const MachineRegisterInfo &MRI) { 383 Optional<DefinitionAndSourceRegister> DefSrcReg = 384 getDefSrcRegIgnoringCopies(Reg, MRI); 385 return DefSrcReg ? DefSrcReg->Reg : Register(); 386 } 387 388 llvm::MachineInstr *llvm::getOpcodeDef(unsigned Opcode, Register Reg, 389 const MachineRegisterInfo &MRI) { 390 MachineInstr *DefMI = getDefIgnoringCopies(Reg, MRI); 391 return DefMI && DefMI->getOpcode() == Opcode ? DefMI : nullptr; 392 } 393 394 APFloat llvm::getAPFloatFromSize(double Val, unsigned Size) { 395 if (Size == 32) 396 return APFloat(float(Val)); 397 if (Size == 64) 398 return APFloat(Val); 399 if (Size != 16) 400 llvm_unreachable("Unsupported FPConstant size"); 401 bool Ignored; 402 APFloat APF(Val); 403 APF.convert(APFloat::IEEEhalf(), APFloat::rmNearestTiesToEven, &Ignored); 404 return APF; 405 } 406 407 Optional<APInt> llvm::ConstantFoldBinOp(unsigned Opcode, const Register Op1, 408 const Register Op2, 409 const MachineRegisterInfo &MRI) { 410 auto MaybeOp2Cst = getConstantVRegVal(Op2, MRI); 411 if (!MaybeOp2Cst) 412 return None; 413 414 auto MaybeOp1Cst = getConstantVRegVal(Op1, MRI); 415 if (!MaybeOp1Cst) 416 return None; 417 418 LLT Ty = MRI.getType(Op1); 419 APInt C1(Ty.getSizeInBits(), *MaybeOp1Cst, true); 420 APInt C2(Ty.getSizeInBits(), *MaybeOp2Cst, true); 421 switch (Opcode) { 422 default: 423 break; 424 case TargetOpcode::G_ADD: 425 return C1 + C2; 426 case TargetOpcode::G_AND: 427 return C1 & C2; 428 case TargetOpcode::G_ASHR: 429 return C1.ashr(C2); 430 case TargetOpcode::G_LSHR: 431 return C1.lshr(C2); 432 case TargetOpcode::G_MUL: 433 return C1 * C2; 434 case TargetOpcode::G_OR: 435 return C1 | C2; 436 case TargetOpcode::G_SHL: 437 return C1 << C2; 438 case TargetOpcode::G_SUB: 439 return C1 - C2; 440 case TargetOpcode::G_XOR: 441 return C1 ^ C2; 442 case TargetOpcode::G_UDIV: 443 if (!C2.getBoolValue()) 444 break; 445 return C1.udiv(C2); 446 case TargetOpcode::G_SDIV: 447 if (!C2.getBoolValue()) 448 break; 449 return C1.sdiv(C2); 450 case TargetOpcode::G_UREM: 451 if (!C2.getBoolValue()) 452 break; 453 return C1.urem(C2); 454 case TargetOpcode::G_SREM: 455 if (!C2.getBoolValue()) 456 break; 457 return C1.srem(C2); 458 } 459 460 return None; 461 } 462 463 bool llvm::isKnownNeverNaN(Register Val, const MachineRegisterInfo &MRI, 464 bool SNaN) { 465 const MachineInstr *DefMI = MRI.getVRegDef(Val); 466 if (!DefMI) 467 return false; 468 469 if (DefMI->getFlag(MachineInstr::FmNoNans)) 470 return true; 471 472 if (SNaN) { 473 // FP operations quiet. For now, just handle the ones inserted during 474 // legalization. 475 switch (DefMI->getOpcode()) { 476 case TargetOpcode::G_FPEXT: 477 case TargetOpcode::G_FPTRUNC: 478 case TargetOpcode::G_FCANONICALIZE: 479 return true; 480 default: 481 return false; 482 } 483 } 484 485 return false; 486 } 487 488 Align llvm::inferAlignFromPtrInfo(MachineFunction &MF, 489 const MachinePointerInfo &MPO) { 490 auto PSV = MPO.V.dyn_cast<const PseudoSourceValue *>(); 491 if (auto FSPV = dyn_cast_or_null<FixedStackPseudoSourceValue>(PSV)) { 492 MachineFrameInfo &MFI = MF.getFrameInfo(); 493 return commonAlignment(MFI.getObjectAlign(FSPV->getFrameIndex()), 494 MPO.Offset); 495 } 496 497 return Align(1); 498 } 499 500 Register llvm::getFunctionLiveInPhysReg(MachineFunction &MF, 501 const TargetInstrInfo &TII, 502 MCRegister PhysReg, 503 const TargetRegisterClass &RC, 504 LLT RegTy) { 505 DebugLoc DL; // FIXME: Is no location the right choice? 506 MachineBasicBlock &EntryMBB = MF.front(); 507 MachineRegisterInfo &MRI = MF.getRegInfo(); 508 Register LiveIn = MRI.getLiveInVirtReg(PhysReg); 509 if (LiveIn) { 510 MachineInstr *Def = MRI.getVRegDef(LiveIn); 511 if (Def) { 512 // FIXME: Should the verifier check this is in the entry block? 513 assert(Def->getParent() == &EntryMBB && "live-in copy not in entry block"); 514 return LiveIn; 515 } 516 517 // It's possible the incoming argument register and copy was added during 518 // lowering, but later deleted due to being/becoming dead. If this happens, 519 // re-insert the copy. 520 } else { 521 // The live in register was not present, so add it. 522 LiveIn = MF.addLiveIn(PhysReg, &RC); 523 if (RegTy.isValid()) 524 MRI.setType(LiveIn, RegTy); 525 } 526 527 BuildMI(EntryMBB, EntryMBB.begin(), DL, TII.get(TargetOpcode::COPY), LiveIn) 528 .addReg(PhysReg); 529 if (!EntryMBB.isLiveIn(PhysReg)) 530 EntryMBB.addLiveIn(PhysReg); 531 return LiveIn; 532 } 533 534 Optional<APInt> llvm::ConstantFoldExtOp(unsigned Opcode, const Register Op1, 535 uint64_t Imm, 536 const MachineRegisterInfo &MRI) { 537 auto MaybeOp1Cst = getConstantVRegVal(Op1, MRI); 538 if (MaybeOp1Cst) { 539 LLT Ty = MRI.getType(Op1); 540 APInt C1(Ty.getSizeInBits(), *MaybeOp1Cst, true); 541 switch (Opcode) { 542 default: 543 break; 544 case TargetOpcode::G_SEXT_INREG: 545 return C1.trunc(Imm).sext(C1.getBitWidth()); 546 } 547 } 548 return None; 549 } 550 551 void llvm::getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU) { 552 AU.addPreserved<StackProtector>(); 553 } 554 555 static unsigned getLCMSize(unsigned OrigSize, unsigned TargetSize) { 556 unsigned Mul = OrigSize * TargetSize; 557 unsigned GCDSize = greatestCommonDivisor(OrigSize, TargetSize); 558 return Mul / GCDSize; 559 } 560 561 LLT llvm::getLCMType(LLT OrigTy, LLT TargetTy) { 562 const unsigned OrigSize = OrigTy.getSizeInBits(); 563 const unsigned TargetSize = TargetTy.getSizeInBits(); 564 565 if (OrigSize == TargetSize) 566 return OrigTy; 567 568 if (OrigTy.isVector()) { 569 const LLT OrigElt = OrigTy.getElementType(); 570 571 if (TargetTy.isVector()) { 572 const LLT TargetElt = TargetTy.getElementType(); 573 574 if (OrigElt.getSizeInBits() == TargetElt.getSizeInBits()) { 575 int GCDElts = greatestCommonDivisor(OrigTy.getNumElements(), 576 TargetTy.getNumElements()); 577 // Prefer the original element type. 578 int Mul = OrigTy.getNumElements() * TargetTy.getNumElements(); 579 return LLT::vector(Mul / GCDElts, OrigTy.getElementType()); 580 } 581 } else { 582 if (OrigElt.getSizeInBits() == TargetSize) 583 return OrigTy; 584 } 585 586 unsigned LCMSize = getLCMSize(OrigSize, TargetSize); 587 return LLT::vector(LCMSize / OrigElt.getSizeInBits(), OrigElt); 588 } 589 590 if (TargetTy.isVector()) { 591 unsigned LCMSize = getLCMSize(OrigSize, TargetSize); 592 return LLT::vector(LCMSize / OrigSize, OrigTy); 593 } 594 595 unsigned LCMSize = getLCMSize(OrigSize, TargetSize); 596 597 // Preserve pointer types. 598 if (LCMSize == OrigSize) 599 return OrigTy; 600 if (LCMSize == TargetSize) 601 return TargetTy; 602 603 return LLT::scalar(LCMSize); 604 } 605 606 LLT llvm::getGCDType(LLT OrigTy, LLT TargetTy) { 607 const unsigned OrigSize = OrigTy.getSizeInBits(); 608 const unsigned TargetSize = TargetTy.getSizeInBits(); 609 610 if (OrigSize == TargetSize) 611 return OrigTy; 612 613 if (OrigTy.isVector()) { 614 LLT OrigElt = OrigTy.getElementType(); 615 if (TargetTy.isVector()) { 616 LLT TargetElt = TargetTy.getElementType(); 617 if (OrigElt.getSizeInBits() == TargetElt.getSizeInBits()) { 618 int GCD = greatestCommonDivisor(OrigTy.getNumElements(), 619 TargetTy.getNumElements()); 620 return LLT::scalarOrVector(GCD, OrigElt); 621 } 622 } else { 623 // If the source is a vector of pointers, return a pointer element. 624 if (OrigElt.getSizeInBits() == TargetSize) 625 return OrigElt; 626 } 627 628 unsigned GCD = greatestCommonDivisor(OrigSize, TargetSize); 629 if (GCD == OrigElt.getSizeInBits()) 630 return OrigElt; 631 632 // If we can't produce the original element type, we have to use a smaller 633 // scalar. 634 if (GCD < OrigElt.getSizeInBits()) 635 return LLT::scalar(GCD); 636 return LLT::vector(GCD / OrigElt.getSizeInBits(), OrigElt); 637 } 638 639 if (TargetTy.isVector()) { 640 // Try to preserve the original element type. 641 LLT TargetElt = TargetTy.getElementType(); 642 if (TargetElt.getSizeInBits() == OrigSize) 643 return OrigTy; 644 } 645 646 unsigned GCD = greatestCommonDivisor(OrigSize, TargetSize); 647 return LLT::scalar(GCD); 648 } 649 650 Optional<int> llvm::getSplatIndex(MachineInstr &MI) { 651 assert(MI.getOpcode() == TargetOpcode::G_SHUFFLE_VECTOR && 652 "Only G_SHUFFLE_VECTOR can have a splat index!"); 653 ArrayRef<int> Mask = MI.getOperand(3).getShuffleMask(); 654 auto FirstDefinedIdx = find_if(Mask, [](int Elt) { return Elt >= 0; }); 655 656 // If all elements are undefined, this shuffle can be considered a splat. 657 // Return 0 for better potential for callers to simplify. 658 if (FirstDefinedIdx == Mask.end()) 659 return 0; 660 661 // Make sure all remaining elements are either undef or the same 662 // as the first non-undef value. 663 int SplatValue = *FirstDefinedIdx; 664 if (any_of(make_range(std::next(FirstDefinedIdx), Mask.end()), 665 [&SplatValue](int Elt) { return Elt >= 0 && Elt != SplatValue; })) 666 return None; 667 668 return SplatValue; 669 } 670