1 //===- llvm/CodeGen/GlobalISel/Utils.cpp -------------------------*- C++ -*-==// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file This file implements the utility functions used by the GlobalISel 9 /// pipeline. 10 //===----------------------------------------------------------------------===// 11 12 #include "llvm/CodeGen/GlobalISel/Utils.h" 13 #include "llvm/ADT/APFloat.h" 14 #include "llvm/ADT/Twine.h" 15 #include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h" 16 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h" 17 #include "llvm/CodeGen/MachineInstr.h" 18 #include "llvm/CodeGen/MachineInstrBuilder.h" 19 #include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h" 20 #include "llvm/CodeGen/MachineRegisterInfo.h" 21 #include "llvm/CodeGen/StackProtector.h" 22 #include "llvm/CodeGen/TargetInstrInfo.h" 23 #include "llvm/CodeGen/TargetPassConfig.h" 24 #include "llvm/CodeGen/TargetRegisterInfo.h" 25 #include "llvm/IR/Constants.h" 26 27 #define DEBUG_TYPE "globalisel-utils" 28 29 using namespace llvm; 30 31 Register llvm::constrainRegToClass(MachineRegisterInfo &MRI, 32 const TargetInstrInfo &TII, 33 const RegisterBankInfo &RBI, Register Reg, 34 const TargetRegisterClass &RegClass) { 35 if (!RBI.constrainGenericRegister(Reg, RegClass, MRI)) 36 return MRI.createVirtualRegister(&RegClass); 37 38 return Reg; 39 } 40 41 Register llvm::constrainOperandRegClass( 42 const MachineFunction &MF, const TargetRegisterInfo &TRI, 43 MachineRegisterInfo &MRI, const TargetInstrInfo &TII, 44 const RegisterBankInfo &RBI, MachineInstr &InsertPt, 45 const TargetRegisterClass &RegClass, const MachineOperand &RegMO) { 46 Register Reg = RegMO.getReg(); 47 // Assume physical registers are properly constrained. 48 assert(Register::isVirtualRegister(Reg) && "PhysReg not implemented"); 49 50 Register ConstrainedReg = constrainRegToClass(MRI, TII, RBI, Reg, RegClass); 51 // If we created a new virtual register because the class is not compatible 52 // then create a copy between the new and the old register. 53 if (ConstrainedReg != Reg) { 54 MachineBasicBlock::iterator InsertIt(&InsertPt); 55 MachineBasicBlock &MBB = *InsertPt.getParent(); 56 if (RegMO.isUse()) { 57 BuildMI(MBB, InsertIt, InsertPt.getDebugLoc(), 58 TII.get(TargetOpcode::COPY), ConstrainedReg) 59 .addReg(Reg); 60 } else { 61 assert(RegMO.isDef() && "Must be a definition"); 62 BuildMI(MBB, std::next(InsertIt), InsertPt.getDebugLoc(), 63 TII.get(TargetOpcode::COPY), Reg) 64 .addReg(ConstrainedReg); 65 } 66 } else { 67 if (GISelChangeObserver *Observer = MF.getObserver()) { 68 if (!RegMO.isDef()) { 69 MachineInstr *RegDef = MRI.getVRegDef(Reg); 70 Observer->changedInstr(*RegDef); 71 } 72 Observer->changingAllUsesOfReg(MRI, Reg); 73 Observer->finishedChangingAllUsesOfReg(); 74 } 75 } 76 return ConstrainedReg; 77 } 78 79 Register llvm::constrainOperandRegClass( 80 const MachineFunction &MF, const TargetRegisterInfo &TRI, 81 MachineRegisterInfo &MRI, const TargetInstrInfo &TII, 82 const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II, 83 const MachineOperand &RegMO, unsigned OpIdx) { 84 Register Reg = RegMO.getReg(); 85 // Assume physical registers are properly constrained. 86 assert(Register::isVirtualRegister(Reg) && "PhysReg not implemented"); 87 88 const TargetRegisterClass *RegClass = TII.getRegClass(II, OpIdx, &TRI, MF); 89 // Some of the target independent instructions, like COPY, may not impose any 90 // register class constraints on some of their operands: If it's a use, we can 91 // skip constraining as the instruction defining the register would constrain 92 // it. 93 94 // We can't constrain unallocatable register classes, because we can't create 95 // virtual registers for these classes, so we need to let targets handled this 96 // case. 97 if (RegClass && !RegClass->isAllocatable()) 98 RegClass = TRI.getConstrainedRegClassForOperand(RegMO, MRI); 99 100 if (!RegClass) { 101 assert((!isTargetSpecificOpcode(II.getOpcode()) || RegMO.isUse()) && 102 "Register class constraint is required unless either the " 103 "instruction is target independent or the operand is a use"); 104 // FIXME: Just bailing out like this here could be not enough, unless we 105 // expect the users of this function to do the right thing for PHIs and 106 // COPY: 107 // v1 = COPY v0 108 // v2 = COPY v1 109 // v1 here may end up not being constrained at all. Please notice that to 110 // reproduce the issue we likely need a destination pattern of a selection 111 // rule producing such extra copies, not just an input GMIR with them as 112 // every existing target using selectImpl handles copies before calling it 113 // and they never reach this function. 114 return Reg; 115 } 116 return constrainOperandRegClass(MF, TRI, MRI, TII, RBI, InsertPt, *RegClass, 117 RegMO); 118 } 119 120 bool llvm::constrainSelectedInstRegOperands(MachineInstr &I, 121 const TargetInstrInfo &TII, 122 const TargetRegisterInfo &TRI, 123 const RegisterBankInfo &RBI) { 124 assert(!isPreISelGenericOpcode(I.getOpcode()) && 125 "A selected instruction is expected"); 126 MachineBasicBlock &MBB = *I.getParent(); 127 MachineFunction &MF = *MBB.getParent(); 128 MachineRegisterInfo &MRI = MF.getRegInfo(); 129 130 for (unsigned OpI = 0, OpE = I.getNumExplicitOperands(); OpI != OpE; ++OpI) { 131 MachineOperand &MO = I.getOperand(OpI); 132 133 // There's nothing to be done on non-register operands. 134 if (!MO.isReg()) 135 continue; 136 137 LLVM_DEBUG(dbgs() << "Converting operand: " << MO << '\n'); 138 assert(MO.isReg() && "Unsupported non-reg operand"); 139 140 Register Reg = MO.getReg(); 141 // Physical registers don't need to be constrained. 142 if (Register::isPhysicalRegister(Reg)) 143 continue; 144 145 // Register operands with a value of 0 (e.g. predicate operands) don't need 146 // to be constrained. 147 if (Reg == 0) 148 continue; 149 150 // If the operand is a vreg, we should constrain its regclass, and only 151 // insert COPYs if that's impossible. 152 // constrainOperandRegClass does that for us. 153 MO.setReg(constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, I.getDesc(), 154 MO, OpI)); 155 156 // Tie uses to defs as indicated in MCInstrDesc if this hasn't already been 157 // done. 158 if (MO.isUse()) { 159 int DefIdx = I.getDesc().getOperandConstraint(OpI, MCOI::TIED_TO); 160 if (DefIdx != -1 && !I.isRegTiedToUseOperand(DefIdx)) 161 I.tieOperands(DefIdx, OpI); 162 } 163 } 164 return true; 165 } 166 167 bool llvm::canReplaceReg(Register DstReg, Register SrcReg, 168 MachineRegisterInfo &MRI) { 169 // Give up if either DstReg or SrcReg is a physical register. 170 if (DstReg.isPhysical() || SrcReg.isPhysical()) 171 return false; 172 // Give up if the types don't match. 173 if (MRI.getType(DstReg) != MRI.getType(SrcReg)) 174 return false; 175 // Replace if either DstReg has no constraints or the register 176 // constraints match. 177 return !MRI.getRegClassOrRegBank(DstReg) || 178 MRI.getRegClassOrRegBank(DstReg) == MRI.getRegClassOrRegBank(SrcReg); 179 } 180 181 bool llvm::isTriviallyDead(const MachineInstr &MI, 182 const MachineRegisterInfo &MRI) { 183 // If we can move an instruction, we can remove it. Otherwise, it has 184 // a side-effect of some sort. 185 bool SawStore = false; 186 if (!MI.isSafeToMove(/*AA=*/nullptr, SawStore) && !MI.isPHI()) 187 return false; 188 189 // Instructions without side-effects are dead iff they only define dead vregs. 190 for (auto &MO : MI.operands()) { 191 if (!MO.isReg() || !MO.isDef()) 192 continue; 193 194 Register Reg = MO.getReg(); 195 if (Register::isPhysicalRegister(Reg) || !MRI.use_nodbg_empty(Reg)) 196 return false; 197 } 198 return true; 199 } 200 201 void llvm::reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, 202 MachineOptimizationRemarkEmitter &MORE, 203 MachineOptimizationRemarkMissed &R) { 204 MF.getProperties().set(MachineFunctionProperties::Property::FailedISel); 205 206 // Print the function name explicitly if we don't have a debug location (which 207 // makes the diagnostic less useful) or if we're going to emit a raw error. 208 if (!R.getLocation().isValid() || TPC.isGlobalISelAbortEnabled()) 209 R << (" (in function: " + MF.getName() + ")").str(); 210 211 if (TPC.isGlobalISelAbortEnabled()) 212 report_fatal_error(R.getMsg()); 213 else 214 MORE.emit(R); 215 } 216 217 void llvm::reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, 218 MachineOptimizationRemarkEmitter &MORE, 219 const char *PassName, StringRef Msg, 220 const MachineInstr &MI) { 221 MachineOptimizationRemarkMissed R(PassName, "GISelFailure: ", 222 MI.getDebugLoc(), MI.getParent()); 223 R << Msg; 224 // Printing MI is expensive; only do it if expensive remarks are enabled. 225 if (TPC.isGlobalISelAbortEnabled() || MORE.allowExtraAnalysis(PassName)) 226 R << ": " << ore::MNV("Inst", MI); 227 reportGISelFailure(MF, TPC, MORE, R); 228 } 229 230 Optional<int64_t> llvm::getConstantVRegVal(Register VReg, 231 const MachineRegisterInfo &MRI) { 232 Optional<ValueAndVReg> ValAndVReg = 233 getConstantVRegValWithLookThrough(VReg, MRI, /*LookThroughInstrs*/ false); 234 assert((!ValAndVReg || ValAndVReg->VReg == VReg) && 235 "Value found while looking through instrs"); 236 if (!ValAndVReg) 237 return None; 238 return ValAndVReg->Value; 239 } 240 241 Optional<ValueAndVReg> llvm::getConstantVRegValWithLookThrough( 242 Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs, 243 bool HandleFConstant) { 244 SmallVector<std::pair<unsigned, unsigned>, 4> SeenOpcodes; 245 MachineInstr *MI; 246 auto IsConstantOpcode = [HandleFConstant](unsigned Opcode) { 247 return Opcode == TargetOpcode::G_CONSTANT || 248 (HandleFConstant && Opcode == TargetOpcode::G_FCONSTANT); 249 }; 250 auto GetImmediateValue = [HandleFConstant, 251 &MRI](const MachineInstr &MI) -> Optional<APInt> { 252 const MachineOperand &CstVal = MI.getOperand(1); 253 if (!CstVal.isImm() && !CstVal.isCImm() && 254 (!HandleFConstant || !CstVal.isFPImm())) 255 return None; 256 if (!CstVal.isFPImm()) { 257 unsigned BitWidth = 258 MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); 259 APInt Val = CstVal.isImm() ? APInt(BitWidth, CstVal.getImm()) 260 : CstVal.getCImm()->getValue(); 261 assert(Val.getBitWidth() == BitWidth && 262 "Value bitwidth doesn't match definition type"); 263 return Val; 264 } 265 return CstVal.getFPImm()->getValueAPF().bitcastToAPInt(); 266 }; 267 while ((MI = MRI.getVRegDef(VReg)) && !IsConstantOpcode(MI->getOpcode()) && 268 LookThroughInstrs) { 269 switch (MI->getOpcode()) { 270 case TargetOpcode::G_TRUNC: 271 case TargetOpcode::G_SEXT: 272 case TargetOpcode::G_ZEXT: 273 SeenOpcodes.push_back(std::make_pair( 274 MI->getOpcode(), 275 MRI.getType(MI->getOperand(0).getReg()).getSizeInBits())); 276 VReg = MI->getOperand(1).getReg(); 277 break; 278 case TargetOpcode::COPY: 279 VReg = MI->getOperand(1).getReg(); 280 if (Register::isPhysicalRegister(VReg)) 281 return None; 282 break; 283 case TargetOpcode::G_INTTOPTR: 284 VReg = MI->getOperand(1).getReg(); 285 break; 286 default: 287 return None; 288 } 289 } 290 if (!MI || !IsConstantOpcode(MI->getOpcode())) 291 return None; 292 293 Optional<APInt> MaybeVal = GetImmediateValue(*MI); 294 if (!MaybeVal) 295 return None; 296 APInt &Val = *MaybeVal; 297 while (!SeenOpcodes.empty()) { 298 std::pair<unsigned, unsigned> OpcodeAndSize = SeenOpcodes.pop_back_val(); 299 switch (OpcodeAndSize.first) { 300 case TargetOpcode::G_TRUNC: 301 Val = Val.trunc(OpcodeAndSize.second); 302 break; 303 case TargetOpcode::G_SEXT: 304 Val = Val.sext(OpcodeAndSize.second); 305 break; 306 case TargetOpcode::G_ZEXT: 307 Val = Val.zext(OpcodeAndSize.second); 308 break; 309 } 310 } 311 312 if (Val.getBitWidth() > 64) 313 return None; 314 315 return ValueAndVReg{Val.getSExtValue(), VReg}; 316 } 317 318 const llvm::ConstantFP * 319 llvm::getConstantFPVRegVal(Register VReg, const MachineRegisterInfo &MRI) { 320 MachineInstr *MI = MRI.getVRegDef(VReg); 321 if (TargetOpcode::G_FCONSTANT != MI->getOpcode()) 322 return nullptr; 323 return MI->getOperand(1).getFPImm(); 324 } 325 326 namespace { 327 struct DefinitionAndSourceRegister { 328 llvm::MachineInstr *MI; 329 Register Reg; 330 }; 331 } // namespace 332 333 static llvm::Optional<DefinitionAndSourceRegister> 334 getDefSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI) { 335 Register DefSrcReg = Reg; 336 auto *DefMI = MRI.getVRegDef(Reg); 337 auto DstTy = MRI.getType(DefMI->getOperand(0).getReg()); 338 if (!DstTy.isValid()) 339 return None; 340 while (DefMI->getOpcode() == TargetOpcode::COPY) { 341 Register SrcReg = DefMI->getOperand(1).getReg(); 342 auto SrcTy = MRI.getType(SrcReg); 343 if (!SrcTy.isValid() || SrcTy != DstTy) 344 break; 345 DefMI = MRI.getVRegDef(SrcReg); 346 DefSrcReg = SrcReg; 347 } 348 return DefinitionAndSourceRegister{DefMI, DefSrcReg}; 349 } 350 351 llvm::MachineInstr *llvm::getDefIgnoringCopies(Register Reg, 352 const MachineRegisterInfo &MRI) { 353 Optional<DefinitionAndSourceRegister> DefSrcReg = 354 getDefSrcRegIgnoringCopies(Reg, MRI); 355 return DefSrcReg ? DefSrcReg->MI : nullptr; 356 } 357 358 Register llvm::getSrcRegIgnoringCopies(Register Reg, 359 const MachineRegisterInfo &MRI) { 360 Optional<DefinitionAndSourceRegister> DefSrcReg = 361 getDefSrcRegIgnoringCopies(Reg, MRI); 362 return DefSrcReg ? DefSrcReg->Reg : Register(); 363 } 364 365 llvm::MachineInstr *llvm::getOpcodeDef(unsigned Opcode, Register Reg, 366 const MachineRegisterInfo &MRI) { 367 MachineInstr *DefMI = getDefIgnoringCopies(Reg, MRI); 368 return DefMI && DefMI->getOpcode() == Opcode ? DefMI : nullptr; 369 } 370 371 APFloat llvm::getAPFloatFromSize(double Val, unsigned Size) { 372 if (Size == 32) 373 return APFloat(float(Val)); 374 if (Size == 64) 375 return APFloat(Val); 376 if (Size != 16) 377 llvm_unreachable("Unsupported FPConstant size"); 378 bool Ignored; 379 APFloat APF(Val); 380 APF.convert(APFloat::IEEEhalf(), APFloat::rmNearestTiesToEven, &Ignored); 381 return APF; 382 } 383 384 Optional<APInt> llvm::ConstantFoldBinOp(unsigned Opcode, const unsigned Op1, 385 const unsigned Op2, 386 const MachineRegisterInfo &MRI) { 387 auto MaybeOp1Cst = getConstantVRegVal(Op1, MRI); 388 auto MaybeOp2Cst = getConstantVRegVal(Op2, MRI); 389 if (MaybeOp1Cst && MaybeOp2Cst) { 390 LLT Ty = MRI.getType(Op1); 391 APInt C1(Ty.getSizeInBits(), *MaybeOp1Cst, true); 392 APInt C2(Ty.getSizeInBits(), *MaybeOp2Cst, true); 393 switch (Opcode) { 394 default: 395 break; 396 case TargetOpcode::G_ADD: 397 return C1 + C2; 398 case TargetOpcode::G_AND: 399 return C1 & C2; 400 case TargetOpcode::G_ASHR: 401 return C1.ashr(C2); 402 case TargetOpcode::G_LSHR: 403 return C1.lshr(C2); 404 case TargetOpcode::G_MUL: 405 return C1 * C2; 406 case TargetOpcode::G_OR: 407 return C1 | C2; 408 case TargetOpcode::G_SHL: 409 return C1 << C2; 410 case TargetOpcode::G_SUB: 411 return C1 - C2; 412 case TargetOpcode::G_XOR: 413 return C1 ^ C2; 414 case TargetOpcode::G_UDIV: 415 if (!C2.getBoolValue()) 416 break; 417 return C1.udiv(C2); 418 case TargetOpcode::G_SDIV: 419 if (!C2.getBoolValue()) 420 break; 421 return C1.sdiv(C2); 422 case TargetOpcode::G_UREM: 423 if (!C2.getBoolValue()) 424 break; 425 return C1.urem(C2); 426 case TargetOpcode::G_SREM: 427 if (!C2.getBoolValue()) 428 break; 429 return C1.srem(C2); 430 } 431 } 432 return None; 433 } 434 435 bool llvm::isKnownNeverNaN(Register Val, const MachineRegisterInfo &MRI, 436 bool SNaN) { 437 const MachineInstr *DefMI = MRI.getVRegDef(Val); 438 if (!DefMI) 439 return false; 440 441 if (DefMI->getFlag(MachineInstr::FmNoNans)) 442 return true; 443 444 if (SNaN) { 445 // FP operations quiet. For now, just handle the ones inserted during 446 // legalization. 447 switch (DefMI->getOpcode()) { 448 case TargetOpcode::G_FPEXT: 449 case TargetOpcode::G_FPTRUNC: 450 case TargetOpcode::G_FCANONICALIZE: 451 return true; 452 default: 453 return false; 454 } 455 } 456 457 return false; 458 } 459 460 Optional<APInt> llvm::ConstantFoldExtOp(unsigned Opcode, const unsigned Op1, 461 uint64_t Imm, 462 const MachineRegisterInfo &MRI) { 463 auto MaybeOp1Cst = getConstantVRegVal(Op1, MRI); 464 if (MaybeOp1Cst) { 465 LLT Ty = MRI.getType(Op1); 466 APInt C1(Ty.getSizeInBits(), *MaybeOp1Cst, true); 467 switch (Opcode) { 468 default: 469 break; 470 case TargetOpcode::G_SEXT_INREG: 471 return C1.trunc(Imm).sext(C1.getBitWidth()); 472 } 473 } 474 return None; 475 } 476 477 void llvm::getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU) { 478 AU.addPreserved<StackProtector>(); 479 } 480