1 //===- llvm/CodeGen/GlobalISel/Utils.cpp -------------------------*- C++ -*-==// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file This file implements the utility functions used by the GlobalISel 9 /// pipeline. 10 //===----------------------------------------------------------------------===// 11 12 #include "llvm/CodeGen/GlobalISel/Utils.h" 13 #include "llvm/ADT/APFloat.h" 14 #include "llvm/ADT/Twine.h" 15 #include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h" 16 #include "llvm/CodeGen/GlobalISel/MIPatternMatch.h" 17 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h" 18 #include "llvm/CodeGen/MachineInstr.h" 19 #include "llvm/CodeGen/MachineInstrBuilder.h" 20 #include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h" 21 #include "llvm/CodeGen/MachineRegisterInfo.h" 22 #include "llvm/CodeGen/StackProtector.h" 23 #include "llvm/CodeGen/TargetInstrInfo.h" 24 #include "llvm/CodeGen/TargetPassConfig.h" 25 #include "llvm/CodeGen/TargetRegisterInfo.h" 26 #include "llvm/IR/Constants.h" 27 28 #define DEBUG_TYPE "globalisel-utils" 29 30 using namespace llvm; 31 using namespace MIPatternMatch; 32 33 Register llvm::constrainRegToClass(MachineRegisterInfo &MRI, 34 const TargetInstrInfo &TII, 35 const RegisterBankInfo &RBI, Register Reg, 36 const TargetRegisterClass &RegClass) { 37 if (!RBI.constrainGenericRegister(Reg, RegClass, MRI)) 38 return MRI.createVirtualRegister(&RegClass); 39 40 return Reg; 41 } 42 43 Register llvm::constrainOperandRegClass( 44 const MachineFunction &MF, const TargetRegisterInfo &TRI, 45 MachineRegisterInfo &MRI, const TargetInstrInfo &TII, 46 const RegisterBankInfo &RBI, MachineInstr &InsertPt, 47 const TargetRegisterClass &RegClass, const MachineOperand &RegMO) { 48 Register Reg = RegMO.getReg(); 49 // Assume physical registers are properly constrained. 50 assert(Register::isVirtualRegister(Reg) && "PhysReg not implemented"); 51 52 Register ConstrainedReg = constrainRegToClass(MRI, TII, RBI, Reg, RegClass); 53 // If we created a new virtual register because the class is not compatible 54 // then create a copy between the new and the old register. 55 if (ConstrainedReg != Reg) { 56 MachineBasicBlock::iterator InsertIt(&InsertPt); 57 MachineBasicBlock &MBB = *InsertPt.getParent(); 58 if (RegMO.isUse()) { 59 BuildMI(MBB, InsertIt, InsertPt.getDebugLoc(), 60 TII.get(TargetOpcode::COPY), ConstrainedReg) 61 .addReg(Reg); 62 } else { 63 assert(RegMO.isDef() && "Must be a definition"); 64 BuildMI(MBB, std::next(InsertIt), InsertPt.getDebugLoc(), 65 TII.get(TargetOpcode::COPY), Reg) 66 .addReg(ConstrainedReg); 67 } 68 } else { 69 if (GISelChangeObserver *Observer = MF.getObserver()) { 70 if (!RegMO.isDef()) { 71 MachineInstr *RegDef = MRI.getVRegDef(Reg); 72 Observer->changedInstr(*RegDef); 73 } 74 Observer->changingAllUsesOfReg(MRI, Reg); 75 Observer->finishedChangingAllUsesOfReg(); 76 } 77 } 78 return ConstrainedReg; 79 } 80 81 Register llvm::constrainOperandRegClass( 82 const MachineFunction &MF, const TargetRegisterInfo &TRI, 83 MachineRegisterInfo &MRI, const TargetInstrInfo &TII, 84 const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II, 85 const MachineOperand &RegMO, unsigned OpIdx) { 86 Register Reg = RegMO.getReg(); 87 // Assume physical registers are properly constrained. 88 assert(Register::isVirtualRegister(Reg) && "PhysReg not implemented"); 89 90 const TargetRegisterClass *RegClass = TII.getRegClass(II, OpIdx, &TRI, MF); 91 // Some of the target independent instructions, like COPY, may not impose any 92 // register class constraints on some of their operands: If it's a use, we can 93 // skip constraining as the instruction defining the register would constrain 94 // it. 95 96 // We can't constrain unallocatable register classes, because we can't create 97 // virtual registers for these classes, so we need to let targets handled this 98 // case. 99 if (RegClass && !RegClass->isAllocatable()) 100 RegClass = TRI.getConstrainedRegClassForOperand(RegMO, MRI); 101 102 if (!RegClass) { 103 assert((!isTargetSpecificOpcode(II.getOpcode()) || RegMO.isUse()) && 104 "Register class constraint is required unless either the " 105 "instruction is target independent or the operand is a use"); 106 // FIXME: Just bailing out like this here could be not enough, unless we 107 // expect the users of this function to do the right thing for PHIs and 108 // COPY: 109 // v1 = COPY v0 110 // v2 = COPY v1 111 // v1 here may end up not being constrained at all. Please notice that to 112 // reproduce the issue we likely need a destination pattern of a selection 113 // rule producing such extra copies, not just an input GMIR with them as 114 // every existing target using selectImpl handles copies before calling it 115 // and they never reach this function. 116 return Reg; 117 } 118 return constrainOperandRegClass(MF, TRI, MRI, TII, RBI, InsertPt, *RegClass, 119 RegMO); 120 } 121 122 bool llvm::constrainSelectedInstRegOperands(MachineInstr &I, 123 const TargetInstrInfo &TII, 124 const TargetRegisterInfo &TRI, 125 const RegisterBankInfo &RBI) { 126 assert(!isPreISelGenericOpcode(I.getOpcode()) && 127 "A selected instruction is expected"); 128 MachineBasicBlock &MBB = *I.getParent(); 129 MachineFunction &MF = *MBB.getParent(); 130 MachineRegisterInfo &MRI = MF.getRegInfo(); 131 132 for (unsigned OpI = 0, OpE = I.getNumExplicitOperands(); OpI != OpE; ++OpI) { 133 MachineOperand &MO = I.getOperand(OpI); 134 135 // There's nothing to be done on non-register operands. 136 if (!MO.isReg()) 137 continue; 138 139 LLVM_DEBUG(dbgs() << "Converting operand: " << MO << '\n'); 140 assert(MO.isReg() && "Unsupported non-reg operand"); 141 142 Register Reg = MO.getReg(); 143 // Physical registers don't need to be constrained. 144 if (Register::isPhysicalRegister(Reg)) 145 continue; 146 147 // Register operands with a value of 0 (e.g. predicate operands) don't need 148 // to be constrained. 149 if (Reg == 0) 150 continue; 151 152 // If the operand is a vreg, we should constrain its regclass, and only 153 // insert COPYs if that's impossible. 154 // constrainOperandRegClass does that for us. 155 MO.setReg(constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, I.getDesc(), 156 MO, OpI)); 157 158 // Tie uses to defs as indicated in MCInstrDesc if this hasn't already been 159 // done. 160 if (MO.isUse()) { 161 int DefIdx = I.getDesc().getOperandConstraint(OpI, MCOI::TIED_TO); 162 if (DefIdx != -1 && !I.isRegTiedToUseOperand(DefIdx)) 163 I.tieOperands(DefIdx, OpI); 164 } 165 } 166 return true; 167 } 168 169 bool llvm::canReplaceReg(Register DstReg, Register SrcReg, 170 MachineRegisterInfo &MRI) { 171 // Give up if either DstReg or SrcReg is a physical register. 172 if (DstReg.isPhysical() || SrcReg.isPhysical()) 173 return false; 174 // Give up if the types don't match. 175 if (MRI.getType(DstReg) != MRI.getType(SrcReg)) 176 return false; 177 // Replace if either DstReg has no constraints or the register 178 // constraints match. 179 return !MRI.getRegClassOrRegBank(DstReg) || 180 MRI.getRegClassOrRegBank(DstReg) == MRI.getRegClassOrRegBank(SrcReg); 181 } 182 183 bool llvm::isTriviallyDead(const MachineInstr &MI, 184 const MachineRegisterInfo &MRI) { 185 // FIXME: This logical is mostly duplicated with 186 // DeadMachineInstructionElim::isDead. Why is LOCAL_ESCAPE not considered in 187 // MachineInstr::isLabel? 188 189 // Don't delete frame allocation labels. 190 if (MI.getOpcode() == TargetOpcode::LOCAL_ESCAPE) 191 return false; 192 193 // If we can move an instruction, we can remove it. Otherwise, it has 194 // a side-effect of some sort. 195 bool SawStore = false; 196 if (!MI.isSafeToMove(/*AA=*/nullptr, SawStore) && !MI.isPHI()) 197 return false; 198 199 // Instructions without side-effects are dead iff they only define dead vregs. 200 for (auto &MO : MI.operands()) { 201 if (!MO.isReg() || !MO.isDef()) 202 continue; 203 204 Register Reg = MO.getReg(); 205 if (Register::isPhysicalRegister(Reg) || !MRI.use_nodbg_empty(Reg)) 206 return false; 207 } 208 return true; 209 } 210 211 static void reportGISelDiagnostic(DiagnosticSeverity Severity, 212 MachineFunction &MF, 213 const TargetPassConfig &TPC, 214 MachineOptimizationRemarkEmitter &MORE, 215 MachineOptimizationRemarkMissed &R) { 216 bool IsFatal = Severity == DS_Error && 217 TPC.isGlobalISelAbortEnabled(); 218 // Print the function name explicitly if we don't have a debug location (which 219 // makes the diagnostic less useful) or if we're going to emit a raw error. 220 if (!R.getLocation().isValid() || IsFatal) 221 R << (" (in function: " + MF.getName() + ")").str(); 222 223 if (IsFatal) 224 report_fatal_error(R.getMsg()); 225 else 226 MORE.emit(R); 227 } 228 229 void llvm::reportGISelWarning(MachineFunction &MF, const TargetPassConfig &TPC, 230 MachineOptimizationRemarkEmitter &MORE, 231 MachineOptimizationRemarkMissed &R) { 232 reportGISelDiagnostic(DS_Warning, MF, TPC, MORE, R); 233 } 234 235 void llvm::reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, 236 MachineOptimizationRemarkEmitter &MORE, 237 MachineOptimizationRemarkMissed &R) { 238 MF.getProperties().set(MachineFunctionProperties::Property::FailedISel); 239 reportGISelDiagnostic(DS_Error, MF, TPC, MORE, R); 240 } 241 242 void llvm::reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, 243 MachineOptimizationRemarkEmitter &MORE, 244 const char *PassName, StringRef Msg, 245 const MachineInstr &MI) { 246 MachineOptimizationRemarkMissed R(PassName, "GISelFailure: ", 247 MI.getDebugLoc(), MI.getParent()); 248 R << Msg; 249 // Printing MI is expensive; only do it if expensive remarks are enabled. 250 if (TPC.isGlobalISelAbortEnabled() || MORE.allowExtraAnalysis(PassName)) 251 R << ": " << ore::MNV("Inst", MI); 252 reportGISelFailure(MF, TPC, MORE, R); 253 } 254 255 Optional<int64_t> llvm::getConstantVRegVal(Register VReg, 256 const MachineRegisterInfo &MRI) { 257 Optional<ValueAndVReg> ValAndVReg = 258 getConstantVRegValWithLookThrough(VReg, MRI, /*LookThroughInstrs*/ false); 259 assert((!ValAndVReg || ValAndVReg->VReg == VReg) && 260 "Value found while looking through instrs"); 261 if (!ValAndVReg) 262 return None; 263 return ValAndVReg->Value; 264 } 265 266 Optional<ValueAndVReg> llvm::getConstantVRegValWithLookThrough( 267 Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs, 268 bool HandleFConstant) { 269 SmallVector<std::pair<unsigned, unsigned>, 4> SeenOpcodes; 270 MachineInstr *MI; 271 auto IsConstantOpcode = [HandleFConstant](unsigned Opcode) { 272 return Opcode == TargetOpcode::G_CONSTANT || 273 (HandleFConstant && Opcode == TargetOpcode::G_FCONSTANT); 274 }; 275 auto GetImmediateValue = [HandleFConstant, 276 &MRI](const MachineInstr &MI) -> Optional<APInt> { 277 const MachineOperand &CstVal = MI.getOperand(1); 278 if (!CstVal.isImm() && !CstVal.isCImm() && 279 (!HandleFConstant || !CstVal.isFPImm())) 280 return None; 281 if (!CstVal.isFPImm()) { 282 unsigned BitWidth = 283 MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); 284 APInt Val = CstVal.isImm() ? APInt(BitWidth, CstVal.getImm()) 285 : CstVal.getCImm()->getValue(); 286 assert(Val.getBitWidth() == BitWidth && 287 "Value bitwidth doesn't match definition type"); 288 return Val; 289 } 290 return CstVal.getFPImm()->getValueAPF().bitcastToAPInt(); 291 }; 292 while ((MI = MRI.getVRegDef(VReg)) && !IsConstantOpcode(MI->getOpcode()) && 293 LookThroughInstrs) { 294 switch (MI->getOpcode()) { 295 case TargetOpcode::G_TRUNC: 296 case TargetOpcode::G_SEXT: 297 case TargetOpcode::G_ZEXT: 298 SeenOpcodes.push_back(std::make_pair( 299 MI->getOpcode(), 300 MRI.getType(MI->getOperand(0).getReg()).getSizeInBits())); 301 VReg = MI->getOperand(1).getReg(); 302 break; 303 case TargetOpcode::COPY: 304 VReg = MI->getOperand(1).getReg(); 305 if (Register::isPhysicalRegister(VReg)) 306 return None; 307 break; 308 case TargetOpcode::G_INTTOPTR: 309 VReg = MI->getOperand(1).getReg(); 310 break; 311 default: 312 return None; 313 } 314 } 315 if (!MI || !IsConstantOpcode(MI->getOpcode())) 316 return None; 317 318 Optional<APInt> MaybeVal = GetImmediateValue(*MI); 319 if (!MaybeVal) 320 return None; 321 APInt &Val = *MaybeVal; 322 while (!SeenOpcodes.empty()) { 323 std::pair<unsigned, unsigned> OpcodeAndSize = SeenOpcodes.pop_back_val(); 324 switch (OpcodeAndSize.first) { 325 case TargetOpcode::G_TRUNC: 326 Val = Val.trunc(OpcodeAndSize.second); 327 break; 328 case TargetOpcode::G_SEXT: 329 Val = Val.sext(OpcodeAndSize.second); 330 break; 331 case TargetOpcode::G_ZEXT: 332 Val = Val.zext(OpcodeAndSize.second); 333 break; 334 } 335 } 336 337 if (Val.getBitWidth() > 64) 338 return None; 339 340 return ValueAndVReg{Val.getSExtValue(), VReg}; 341 } 342 343 const ConstantFP * 344 llvm::getConstantFPVRegVal(Register VReg, const MachineRegisterInfo &MRI) { 345 MachineInstr *MI = MRI.getVRegDef(VReg); 346 if (TargetOpcode::G_FCONSTANT != MI->getOpcode()) 347 return nullptr; 348 return MI->getOperand(1).getFPImm(); 349 } 350 351 namespace { 352 struct DefinitionAndSourceRegister { 353 MachineInstr *MI; 354 Register Reg; 355 }; 356 } // namespace 357 358 static Optional<DefinitionAndSourceRegister> 359 getDefSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI) { 360 Register DefSrcReg = Reg; 361 auto *DefMI = MRI.getVRegDef(Reg); 362 auto DstTy = MRI.getType(DefMI->getOperand(0).getReg()); 363 if (!DstTy.isValid()) 364 return None; 365 while (DefMI->getOpcode() == TargetOpcode::COPY) { 366 Register SrcReg = DefMI->getOperand(1).getReg(); 367 auto SrcTy = MRI.getType(SrcReg); 368 if (!SrcTy.isValid()) 369 break; 370 DefMI = MRI.getVRegDef(SrcReg); 371 DefSrcReg = SrcReg; 372 } 373 return DefinitionAndSourceRegister{DefMI, DefSrcReg}; 374 } 375 376 MachineInstr *llvm::getDefIgnoringCopies(Register Reg, 377 const MachineRegisterInfo &MRI) { 378 Optional<DefinitionAndSourceRegister> DefSrcReg = 379 getDefSrcRegIgnoringCopies(Reg, MRI); 380 return DefSrcReg ? DefSrcReg->MI : nullptr; 381 } 382 383 Register llvm::getSrcRegIgnoringCopies(Register Reg, 384 const MachineRegisterInfo &MRI) { 385 Optional<DefinitionAndSourceRegister> DefSrcReg = 386 getDefSrcRegIgnoringCopies(Reg, MRI); 387 return DefSrcReg ? DefSrcReg->Reg : Register(); 388 } 389 390 MachineInstr *llvm::getOpcodeDef(unsigned Opcode, Register Reg, 391 const MachineRegisterInfo &MRI) { 392 MachineInstr *DefMI = getDefIgnoringCopies(Reg, MRI); 393 return DefMI && DefMI->getOpcode() == Opcode ? DefMI : nullptr; 394 } 395 396 APFloat llvm::getAPFloatFromSize(double Val, unsigned Size) { 397 if (Size == 32) 398 return APFloat(float(Val)); 399 if (Size == 64) 400 return APFloat(Val); 401 if (Size != 16) 402 llvm_unreachable("Unsupported FPConstant size"); 403 bool Ignored; 404 APFloat APF(Val); 405 APF.convert(APFloat::IEEEhalf(), APFloat::rmNearestTiesToEven, &Ignored); 406 return APF; 407 } 408 409 Optional<APInt> llvm::ConstantFoldBinOp(unsigned Opcode, const Register Op1, 410 const Register Op2, 411 const MachineRegisterInfo &MRI) { 412 auto MaybeOp2Cst = getConstantVRegVal(Op2, MRI); 413 if (!MaybeOp2Cst) 414 return None; 415 416 auto MaybeOp1Cst = getConstantVRegVal(Op1, MRI); 417 if (!MaybeOp1Cst) 418 return None; 419 420 LLT Ty = MRI.getType(Op1); 421 APInt C1(Ty.getSizeInBits(), *MaybeOp1Cst, true); 422 APInt C2(Ty.getSizeInBits(), *MaybeOp2Cst, true); 423 switch (Opcode) { 424 default: 425 break; 426 case TargetOpcode::G_ADD: 427 return C1 + C2; 428 case TargetOpcode::G_AND: 429 return C1 & C2; 430 case TargetOpcode::G_ASHR: 431 return C1.ashr(C2); 432 case TargetOpcode::G_LSHR: 433 return C1.lshr(C2); 434 case TargetOpcode::G_MUL: 435 return C1 * C2; 436 case TargetOpcode::G_OR: 437 return C1 | C2; 438 case TargetOpcode::G_SHL: 439 return C1 << C2; 440 case TargetOpcode::G_SUB: 441 return C1 - C2; 442 case TargetOpcode::G_XOR: 443 return C1 ^ C2; 444 case TargetOpcode::G_UDIV: 445 if (!C2.getBoolValue()) 446 break; 447 return C1.udiv(C2); 448 case TargetOpcode::G_SDIV: 449 if (!C2.getBoolValue()) 450 break; 451 return C1.sdiv(C2); 452 case TargetOpcode::G_UREM: 453 if (!C2.getBoolValue()) 454 break; 455 return C1.urem(C2); 456 case TargetOpcode::G_SREM: 457 if (!C2.getBoolValue()) 458 break; 459 return C1.srem(C2); 460 } 461 462 return None; 463 } 464 465 bool llvm::isKnownNeverNaN(Register Val, const MachineRegisterInfo &MRI, 466 bool SNaN) { 467 const MachineInstr *DefMI = MRI.getVRegDef(Val); 468 if (!DefMI) 469 return false; 470 471 if (DefMI->getFlag(MachineInstr::FmNoNans)) 472 return true; 473 474 if (SNaN) { 475 // FP operations quiet. For now, just handle the ones inserted during 476 // legalization. 477 switch (DefMI->getOpcode()) { 478 case TargetOpcode::G_FPEXT: 479 case TargetOpcode::G_FPTRUNC: 480 case TargetOpcode::G_FCANONICALIZE: 481 return true; 482 default: 483 return false; 484 } 485 } 486 487 return false; 488 } 489 490 Align llvm::inferAlignFromPtrInfo(MachineFunction &MF, 491 const MachinePointerInfo &MPO) { 492 auto PSV = MPO.V.dyn_cast<const PseudoSourceValue *>(); 493 if (auto FSPV = dyn_cast_or_null<FixedStackPseudoSourceValue>(PSV)) { 494 MachineFrameInfo &MFI = MF.getFrameInfo(); 495 return commonAlignment(MFI.getObjectAlign(FSPV->getFrameIndex()), 496 MPO.Offset); 497 } 498 499 return Align(1); 500 } 501 502 Register llvm::getFunctionLiveInPhysReg(MachineFunction &MF, 503 const TargetInstrInfo &TII, 504 MCRegister PhysReg, 505 const TargetRegisterClass &RC, 506 LLT RegTy) { 507 DebugLoc DL; // FIXME: Is no location the right choice? 508 MachineBasicBlock &EntryMBB = MF.front(); 509 MachineRegisterInfo &MRI = MF.getRegInfo(); 510 Register LiveIn = MRI.getLiveInVirtReg(PhysReg); 511 if (LiveIn) { 512 MachineInstr *Def = MRI.getVRegDef(LiveIn); 513 if (Def) { 514 // FIXME: Should the verifier check this is in the entry block? 515 assert(Def->getParent() == &EntryMBB && "live-in copy not in entry block"); 516 return LiveIn; 517 } 518 519 // It's possible the incoming argument register and copy was added during 520 // lowering, but later deleted due to being/becoming dead. If this happens, 521 // re-insert the copy. 522 } else { 523 // The live in register was not present, so add it. 524 LiveIn = MF.addLiveIn(PhysReg, &RC); 525 if (RegTy.isValid()) 526 MRI.setType(LiveIn, RegTy); 527 } 528 529 BuildMI(EntryMBB, EntryMBB.begin(), DL, TII.get(TargetOpcode::COPY), LiveIn) 530 .addReg(PhysReg); 531 if (!EntryMBB.isLiveIn(PhysReg)) 532 EntryMBB.addLiveIn(PhysReg); 533 return LiveIn; 534 } 535 536 Optional<APInt> llvm::ConstantFoldExtOp(unsigned Opcode, const Register Op1, 537 uint64_t Imm, 538 const MachineRegisterInfo &MRI) { 539 auto MaybeOp1Cst = getConstantVRegVal(Op1, MRI); 540 if (MaybeOp1Cst) { 541 LLT Ty = MRI.getType(Op1); 542 APInt C1(Ty.getSizeInBits(), *MaybeOp1Cst, true); 543 switch (Opcode) { 544 default: 545 break; 546 case TargetOpcode::G_SEXT_INREG: 547 return C1.trunc(Imm).sext(C1.getBitWidth()); 548 } 549 } 550 return None; 551 } 552 553 void llvm::getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU) { 554 AU.addPreserved<StackProtector>(); 555 } 556 557 static unsigned getLCMSize(unsigned OrigSize, unsigned TargetSize) { 558 unsigned Mul = OrigSize * TargetSize; 559 unsigned GCDSize = greatestCommonDivisor(OrigSize, TargetSize); 560 return Mul / GCDSize; 561 } 562 563 LLT llvm::getLCMType(LLT OrigTy, LLT TargetTy) { 564 const unsigned OrigSize = OrigTy.getSizeInBits(); 565 const unsigned TargetSize = TargetTy.getSizeInBits(); 566 567 if (OrigSize == TargetSize) 568 return OrigTy; 569 570 if (OrigTy.isVector()) { 571 const LLT OrigElt = OrigTy.getElementType(); 572 573 if (TargetTy.isVector()) { 574 const LLT TargetElt = TargetTy.getElementType(); 575 576 if (OrigElt.getSizeInBits() == TargetElt.getSizeInBits()) { 577 int GCDElts = greatestCommonDivisor(OrigTy.getNumElements(), 578 TargetTy.getNumElements()); 579 // Prefer the original element type. 580 int Mul = OrigTy.getNumElements() * TargetTy.getNumElements(); 581 return LLT::vector(Mul / GCDElts, OrigTy.getElementType()); 582 } 583 } else { 584 if (OrigElt.getSizeInBits() == TargetSize) 585 return OrigTy; 586 } 587 588 unsigned LCMSize = getLCMSize(OrigSize, TargetSize); 589 return LLT::vector(LCMSize / OrigElt.getSizeInBits(), OrigElt); 590 } 591 592 if (TargetTy.isVector()) { 593 unsigned LCMSize = getLCMSize(OrigSize, TargetSize); 594 return LLT::vector(LCMSize / OrigSize, OrigTy); 595 } 596 597 unsigned LCMSize = getLCMSize(OrigSize, TargetSize); 598 599 // Preserve pointer types. 600 if (LCMSize == OrigSize) 601 return OrigTy; 602 if (LCMSize == TargetSize) 603 return TargetTy; 604 605 return LLT::scalar(LCMSize); 606 } 607 608 LLT llvm::getGCDType(LLT OrigTy, LLT TargetTy) { 609 const unsigned OrigSize = OrigTy.getSizeInBits(); 610 const unsigned TargetSize = TargetTy.getSizeInBits(); 611 612 if (OrigSize == TargetSize) 613 return OrigTy; 614 615 if (OrigTy.isVector()) { 616 LLT OrigElt = OrigTy.getElementType(); 617 if (TargetTy.isVector()) { 618 LLT TargetElt = TargetTy.getElementType(); 619 if (OrigElt.getSizeInBits() == TargetElt.getSizeInBits()) { 620 int GCD = greatestCommonDivisor(OrigTy.getNumElements(), 621 TargetTy.getNumElements()); 622 return LLT::scalarOrVector(GCD, OrigElt); 623 } 624 } else { 625 // If the source is a vector of pointers, return a pointer element. 626 if (OrigElt.getSizeInBits() == TargetSize) 627 return OrigElt; 628 } 629 630 unsigned GCD = greatestCommonDivisor(OrigSize, TargetSize); 631 if (GCD == OrigElt.getSizeInBits()) 632 return OrigElt; 633 634 // If we can't produce the original element type, we have to use a smaller 635 // scalar. 636 if (GCD < OrigElt.getSizeInBits()) 637 return LLT::scalar(GCD); 638 return LLT::vector(GCD / OrigElt.getSizeInBits(), OrigElt); 639 } 640 641 if (TargetTy.isVector()) { 642 // Try to preserve the original element type. 643 LLT TargetElt = TargetTy.getElementType(); 644 if (TargetElt.getSizeInBits() == OrigSize) 645 return OrigTy; 646 } 647 648 unsigned GCD = greatestCommonDivisor(OrigSize, TargetSize); 649 return LLT::scalar(GCD); 650 } 651 652 Optional<int> llvm::getSplatIndex(MachineInstr &MI) { 653 assert(MI.getOpcode() == TargetOpcode::G_SHUFFLE_VECTOR && 654 "Only G_SHUFFLE_VECTOR can have a splat index!"); 655 ArrayRef<int> Mask = MI.getOperand(3).getShuffleMask(); 656 auto FirstDefinedIdx = find_if(Mask, [](int Elt) { return Elt >= 0; }); 657 658 // If all elements are undefined, this shuffle can be considered a splat. 659 // Return 0 for better potential for callers to simplify. 660 if (FirstDefinedIdx == Mask.end()) 661 return 0; 662 663 // Make sure all remaining elements are either undef or the same 664 // as the first non-undef value. 665 int SplatValue = *FirstDefinedIdx; 666 if (any_of(make_range(std::next(FirstDefinedIdx), Mask.end()), 667 [&SplatValue](int Elt) { return Elt >= 0 && Elt != SplatValue; })) 668 return None; 669 670 return SplatValue; 671 } 672 673 static bool isBuildVectorOp(unsigned Opcode) { 674 return Opcode == TargetOpcode::G_BUILD_VECTOR || 675 Opcode == TargetOpcode::G_BUILD_VECTOR_TRUNC; 676 } 677 678 // TODO: Handle mixed undef elements. 679 static bool isBuildVectorConstantSplat(const MachineInstr &MI, 680 const MachineRegisterInfo &MRI, 681 int64_t SplatValue) { 682 if (!isBuildVectorOp(MI.getOpcode())) 683 return false; 684 685 const unsigned NumOps = MI.getNumOperands(); 686 for (unsigned I = 1; I != NumOps; ++I) { 687 Register Element = MI.getOperand(I).getReg(); 688 int64_t ElementValue; 689 if (!mi_match(Element, MRI, m_ICst(ElementValue)) || 690 ElementValue != SplatValue) 691 return false; 692 } 693 694 return true; 695 } 696 697 bool llvm::isBuildVectorAllZeros(const MachineInstr &MI, 698 const MachineRegisterInfo &MRI) { 699 return isBuildVectorConstantSplat(MI, MRI, 0); 700 } 701 702 bool llvm::isBuildVectorAllOnes(const MachineInstr &MI, 703 const MachineRegisterInfo &MRI) { 704 return isBuildVectorConstantSplat(MI, MRI, -1); 705 } 706