1 //===- llvm/CodeGen/GlobalISel/Utils.cpp -------------------------*- C++ -*-==// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file This file implements the utility functions used by the GlobalISel 9 /// pipeline. 10 //===----------------------------------------------------------------------===// 11 12 #include "llvm/CodeGen/GlobalISel/Utils.h" 13 #include "llvm/ADT/APFloat.h" 14 #include "llvm/ADT/APInt.h" 15 #include "llvm/ADT/Optional.h" 16 #include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h" 17 #include "llvm/CodeGen/GlobalISel/MIPatternMatch.h" 18 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h" 19 #include "llvm/CodeGen/MachineInstr.h" 20 #include "llvm/CodeGen/MachineInstrBuilder.h" 21 #include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h" 22 #include "llvm/CodeGen/MachineRegisterInfo.h" 23 #include "llvm/CodeGen/StackProtector.h" 24 #include "llvm/CodeGen/TargetInstrInfo.h" 25 #include "llvm/CodeGen/TargetLowering.h" 26 #include "llvm/CodeGen/TargetPassConfig.h" 27 #include "llvm/CodeGen/TargetRegisterInfo.h" 28 #include "llvm/IR/Constants.h" 29 #include "llvm/Target/TargetMachine.h" 30 31 #define DEBUG_TYPE "globalisel-utils" 32 33 using namespace llvm; 34 using namespace MIPatternMatch; 35 36 Register llvm::constrainRegToClass(MachineRegisterInfo &MRI, 37 const TargetInstrInfo &TII, 38 const RegisterBankInfo &RBI, Register Reg, 39 const TargetRegisterClass &RegClass) { 40 if (!RBI.constrainGenericRegister(Reg, RegClass, MRI)) 41 return MRI.createVirtualRegister(&RegClass); 42 43 return Reg; 44 } 45 46 Register llvm::constrainOperandRegClass( 47 const MachineFunction &MF, const TargetRegisterInfo &TRI, 48 MachineRegisterInfo &MRI, const TargetInstrInfo &TII, 49 const RegisterBankInfo &RBI, MachineInstr &InsertPt, 50 const TargetRegisterClass &RegClass, const MachineOperand &RegMO) { 51 Register Reg = RegMO.getReg(); 52 // Assume physical registers are properly constrained. 53 assert(Register::isVirtualRegister(Reg) && "PhysReg not implemented"); 54 55 Register ConstrainedReg = constrainRegToClass(MRI, TII, RBI, Reg, RegClass); 56 // If we created a new virtual register because the class is not compatible 57 // then create a copy between the new and the old register. 58 if (ConstrainedReg != Reg) { 59 MachineBasicBlock::iterator InsertIt(&InsertPt); 60 MachineBasicBlock &MBB = *InsertPt.getParent(); 61 if (RegMO.isUse()) { 62 BuildMI(MBB, InsertIt, InsertPt.getDebugLoc(), 63 TII.get(TargetOpcode::COPY), ConstrainedReg) 64 .addReg(Reg); 65 } else { 66 assert(RegMO.isDef() && "Must be a definition"); 67 BuildMI(MBB, std::next(InsertIt), InsertPt.getDebugLoc(), 68 TII.get(TargetOpcode::COPY), Reg) 69 .addReg(ConstrainedReg); 70 } 71 } else { 72 if (GISelChangeObserver *Observer = MF.getObserver()) { 73 if (!RegMO.isDef()) { 74 MachineInstr *RegDef = MRI.getVRegDef(Reg); 75 Observer->changedInstr(*RegDef); 76 } 77 Observer->changingAllUsesOfReg(MRI, Reg); 78 Observer->finishedChangingAllUsesOfReg(); 79 } 80 } 81 return ConstrainedReg; 82 } 83 84 Register llvm::constrainOperandRegClass( 85 const MachineFunction &MF, const TargetRegisterInfo &TRI, 86 MachineRegisterInfo &MRI, const TargetInstrInfo &TII, 87 const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II, 88 const MachineOperand &RegMO, unsigned OpIdx) { 89 Register Reg = RegMO.getReg(); 90 // Assume physical registers are properly constrained. 91 assert(Register::isVirtualRegister(Reg) && "PhysReg not implemented"); 92 93 const TargetRegisterClass *RegClass = TII.getRegClass(II, OpIdx, &TRI, MF); 94 // Some of the target independent instructions, like COPY, may not impose any 95 // register class constraints on some of their operands: If it's a use, we can 96 // skip constraining as the instruction defining the register would constrain 97 // it. 98 99 // We can't constrain unallocatable register classes, because we can't create 100 // virtual registers for these classes, so we need to let targets handled this 101 // case. 102 if (RegClass && !RegClass->isAllocatable()) 103 RegClass = TRI.getConstrainedRegClassForOperand(RegMO, MRI); 104 105 if (!RegClass) { 106 assert((!isTargetSpecificOpcode(II.getOpcode()) || RegMO.isUse()) && 107 "Register class constraint is required unless either the " 108 "instruction is target independent or the operand is a use"); 109 // FIXME: Just bailing out like this here could be not enough, unless we 110 // expect the users of this function to do the right thing for PHIs and 111 // COPY: 112 // v1 = COPY v0 113 // v2 = COPY v1 114 // v1 here may end up not being constrained at all. Please notice that to 115 // reproduce the issue we likely need a destination pattern of a selection 116 // rule producing such extra copies, not just an input GMIR with them as 117 // every existing target using selectImpl handles copies before calling it 118 // and they never reach this function. 119 return Reg; 120 } 121 return constrainOperandRegClass(MF, TRI, MRI, TII, RBI, InsertPt, *RegClass, 122 RegMO); 123 } 124 125 bool llvm::constrainSelectedInstRegOperands(MachineInstr &I, 126 const TargetInstrInfo &TII, 127 const TargetRegisterInfo &TRI, 128 const RegisterBankInfo &RBI) { 129 assert(!isPreISelGenericOpcode(I.getOpcode()) && 130 "A selected instruction is expected"); 131 MachineBasicBlock &MBB = *I.getParent(); 132 MachineFunction &MF = *MBB.getParent(); 133 MachineRegisterInfo &MRI = MF.getRegInfo(); 134 135 for (unsigned OpI = 0, OpE = I.getNumExplicitOperands(); OpI != OpE; ++OpI) { 136 MachineOperand &MO = I.getOperand(OpI); 137 138 // There's nothing to be done on non-register operands. 139 if (!MO.isReg()) 140 continue; 141 142 LLVM_DEBUG(dbgs() << "Converting operand: " << MO << '\n'); 143 assert(MO.isReg() && "Unsupported non-reg operand"); 144 145 Register Reg = MO.getReg(); 146 // Physical registers don't need to be constrained. 147 if (Register::isPhysicalRegister(Reg)) 148 continue; 149 150 // Register operands with a value of 0 (e.g. predicate operands) don't need 151 // to be constrained. 152 if (Reg == 0) 153 continue; 154 155 // If the operand is a vreg, we should constrain its regclass, and only 156 // insert COPYs if that's impossible. 157 // constrainOperandRegClass does that for us. 158 MO.setReg(constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, I.getDesc(), 159 MO, OpI)); 160 161 // Tie uses to defs as indicated in MCInstrDesc if this hasn't already been 162 // done. 163 if (MO.isUse()) { 164 int DefIdx = I.getDesc().getOperandConstraint(OpI, MCOI::TIED_TO); 165 if (DefIdx != -1 && !I.isRegTiedToUseOperand(DefIdx)) 166 I.tieOperands(DefIdx, OpI); 167 } 168 } 169 return true; 170 } 171 172 bool llvm::canReplaceReg(Register DstReg, Register SrcReg, 173 MachineRegisterInfo &MRI) { 174 // Give up if either DstReg or SrcReg is a physical register. 175 if (DstReg.isPhysical() || SrcReg.isPhysical()) 176 return false; 177 // Give up if the types don't match. 178 if (MRI.getType(DstReg) != MRI.getType(SrcReg)) 179 return false; 180 // Replace if either DstReg has no constraints or the register 181 // constraints match. 182 return !MRI.getRegClassOrRegBank(DstReg) || 183 MRI.getRegClassOrRegBank(DstReg) == MRI.getRegClassOrRegBank(SrcReg); 184 } 185 186 bool llvm::isTriviallyDead(const MachineInstr &MI, 187 const MachineRegisterInfo &MRI) { 188 // FIXME: This logical is mostly duplicated with 189 // DeadMachineInstructionElim::isDead. Why is LOCAL_ESCAPE not considered in 190 // MachineInstr::isLabel? 191 192 // Don't delete frame allocation labels. 193 if (MI.getOpcode() == TargetOpcode::LOCAL_ESCAPE) 194 return false; 195 196 // If we can move an instruction, we can remove it. Otherwise, it has 197 // a side-effect of some sort. 198 bool SawStore = false; 199 if (!MI.isSafeToMove(/*AA=*/nullptr, SawStore) && !MI.isPHI()) 200 return false; 201 202 // Instructions without side-effects are dead iff they only define dead vregs. 203 for (auto &MO : MI.operands()) { 204 if (!MO.isReg() || !MO.isDef()) 205 continue; 206 207 Register Reg = MO.getReg(); 208 if (Register::isPhysicalRegister(Reg) || !MRI.use_nodbg_empty(Reg)) 209 return false; 210 } 211 return true; 212 } 213 214 static void reportGISelDiagnostic(DiagnosticSeverity Severity, 215 MachineFunction &MF, 216 const TargetPassConfig &TPC, 217 MachineOptimizationRemarkEmitter &MORE, 218 MachineOptimizationRemarkMissed &R) { 219 bool IsFatal = Severity == DS_Error && 220 TPC.isGlobalISelAbortEnabled(); 221 // Print the function name explicitly if we don't have a debug location (which 222 // makes the diagnostic less useful) or if we're going to emit a raw error. 223 if (!R.getLocation().isValid() || IsFatal) 224 R << (" (in function: " + MF.getName() + ")").str(); 225 226 if (IsFatal) 227 report_fatal_error(R.getMsg()); 228 else 229 MORE.emit(R); 230 } 231 232 void llvm::reportGISelWarning(MachineFunction &MF, const TargetPassConfig &TPC, 233 MachineOptimizationRemarkEmitter &MORE, 234 MachineOptimizationRemarkMissed &R) { 235 reportGISelDiagnostic(DS_Warning, MF, TPC, MORE, R); 236 } 237 238 void llvm::reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, 239 MachineOptimizationRemarkEmitter &MORE, 240 MachineOptimizationRemarkMissed &R) { 241 MF.getProperties().set(MachineFunctionProperties::Property::FailedISel); 242 reportGISelDiagnostic(DS_Error, MF, TPC, MORE, R); 243 } 244 245 void llvm::reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, 246 MachineOptimizationRemarkEmitter &MORE, 247 const char *PassName, StringRef Msg, 248 const MachineInstr &MI) { 249 MachineOptimizationRemarkMissed R(PassName, "GISelFailure: ", 250 MI.getDebugLoc(), MI.getParent()); 251 R << Msg; 252 // Printing MI is expensive; only do it if expensive remarks are enabled. 253 if (TPC.isGlobalISelAbortEnabled() || MORE.allowExtraAnalysis(PassName)) 254 R << ": " << ore::MNV("Inst", MI); 255 reportGISelFailure(MF, TPC, MORE, R); 256 } 257 258 Optional<APInt> llvm::getConstantVRegVal(Register VReg, 259 const MachineRegisterInfo &MRI) { 260 Optional<ValueAndVReg> ValAndVReg = 261 getConstantVRegValWithLookThrough(VReg, MRI, /*LookThroughInstrs*/ false); 262 assert((!ValAndVReg || ValAndVReg->VReg == VReg) && 263 "Value found while looking through instrs"); 264 if (!ValAndVReg) 265 return None; 266 return ValAndVReg->Value; 267 } 268 269 Optional<int64_t> llvm::getConstantVRegSExtVal(Register VReg, 270 const MachineRegisterInfo &MRI) { 271 Optional<APInt> Val = getConstantVRegVal(VReg, MRI); 272 if (Val && Val->getBitWidth() <= 64) 273 return Val->getSExtValue(); 274 return None; 275 } 276 277 Optional<ValueAndVReg> llvm::getConstantVRegValWithLookThrough( 278 Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs, 279 bool HandleFConstant) { 280 SmallVector<std::pair<unsigned, unsigned>, 4> SeenOpcodes; 281 MachineInstr *MI; 282 auto IsConstantOpcode = [HandleFConstant](unsigned Opcode) { 283 return Opcode == TargetOpcode::G_CONSTANT || 284 (HandleFConstant && Opcode == TargetOpcode::G_FCONSTANT); 285 }; 286 auto GetImmediateValue = [HandleFConstant, 287 &MRI](const MachineInstr &MI) -> Optional<APInt> { 288 const MachineOperand &CstVal = MI.getOperand(1); 289 if (!CstVal.isImm() && !CstVal.isCImm() && 290 (!HandleFConstant || !CstVal.isFPImm())) 291 return None; 292 if (!CstVal.isFPImm()) { 293 unsigned BitWidth = 294 MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); 295 APInt Val = CstVal.isImm() ? APInt(BitWidth, CstVal.getImm()) 296 : CstVal.getCImm()->getValue(); 297 assert(Val.getBitWidth() == BitWidth && 298 "Value bitwidth doesn't match definition type"); 299 return Val; 300 } 301 return CstVal.getFPImm()->getValueAPF().bitcastToAPInt(); 302 }; 303 while ((MI = MRI.getVRegDef(VReg)) && !IsConstantOpcode(MI->getOpcode()) && 304 LookThroughInstrs) { 305 switch (MI->getOpcode()) { 306 case TargetOpcode::G_TRUNC: 307 case TargetOpcode::G_SEXT: 308 case TargetOpcode::G_ZEXT: 309 SeenOpcodes.push_back(std::make_pair( 310 MI->getOpcode(), 311 MRI.getType(MI->getOperand(0).getReg()).getSizeInBits())); 312 VReg = MI->getOperand(1).getReg(); 313 break; 314 case TargetOpcode::COPY: 315 VReg = MI->getOperand(1).getReg(); 316 if (Register::isPhysicalRegister(VReg)) 317 return None; 318 break; 319 case TargetOpcode::G_INTTOPTR: 320 VReg = MI->getOperand(1).getReg(); 321 break; 322 default: 323 return None; 324 } 325 } 326 if (!MI || !IsConstantOpcode(MI->getOpcode())) 327 return None; 328 329 Optional<APInt> MaybeVal = GetImmediateValue(*MI); 330 if (!MaybeVal) 331 return None; 332 APInt &Val = *MaybeVal; 333 while (!SeenOpcodes.empty()) { 334 std::pair<unsigned, unsigned> OpcodeAndSize = SeenOpcodes.pop_back_val(); 335 switch (OpcodeAndSize.first) { 336 case TargetOpcode::G_TRUNC: 337 Val = Val.trunc(OpcodeAndSize.second); 338 break; 339 case TargetOpcode::G_SEXT: 340 Val = Val.sext(OpcodeAndSize.second); 341 break; 342 case TargetOpcode::G_ZEXT: 343 Val = Val.zext(OpcodeAndSize.second); 344 break; 345 } 346 } 347 348 return ValueAndVReg{Val, VReg}; 349 } 350 351 const ConstantFP * 352 llvm::getConstantFPVRegVal(Register VReg, const MachineRegisterInfo &MRI) { 353 MachineInstr *MI = MRI.getVRegDef(VReg); 354 if (TargetOpcode::G_FCONSTANT != MI->getOpcode()) 355 return nullptr; 356 return MI->getOperand(1).getFPImm(); 357 } 358 359 Optional<DefinitionAndSourceRegister> 360 llvm::getDefSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI) { 361 Register DefSrcReg = Reg; 362 auto *DefMI = MRI.getVRegDef(Reg); 363 auto DstTy = MRI.getType(DefMI->getOperand(0).getReg()); 364 if (!DstTy.isValid()) 365 return None; 366 while (DefMI->getOpcode() == TargetOpcode::COPY) { 367 Register SrcReg = DefMI->getOperand(1).getReg(); 368 auto SrcTy = MRI.getType(SrcReg); 369 if (!SrcTy.isValid()) 370 break; 371 DefMI = MRI.getVRegDef(SrcReg); 372 DefSrcReg = SrcReg; 373 } 374 return DefinitionAndSourceRegister{DefMI, DefSrcReg}; 375 } 376 377 MachineInstr *llvm::getDefIgnoringCopies(Register Reg, 378 const MachineRegisterInfo &MRI) { 379 Optional<DefinitionAndSourceRegister> DefSrcReg = 380 getDefSrcRegIgnoringCopies(Reg, MRI); 381 return DefSrcReg ? DefSrcReg->MI : nullptr; 382 } 383 384 Register llvm::getSrcRegIgnoringCopies(Register Reg, 385 const MachineRegisterInfo &MRI) { 386 Optional<DefinitionAndSourceRegister> DefSrcReg = 387 getDefSrcRegIgnoringCopies(Reg, MRI); 388 return DefSrcReg ? DefSrcReg->Reg : Register(); 389 } 390 391 MachineInstr *llvm::getOpcodeDef(unsigned Opcode, Register Reg, 392 const MachineRegisterInfo &MRI) { 393 MachineInstr *DefMI = getDefIgnoringCopies(Reg, MRI); 394 return DefMI && DefMI->getOpcode() == Opcode ? DefMI : nullptr; 395 } 396 397 APFloat llvm::getAPFloatFromSize(double Val, unsigned Size) { 398 if (Size == 32) 399 return APFloat(float(Val)); 400 if (Size == 64) 401 return APFloat(Val); 402 if (Size != 16) 403 llvm_unreachable("Unsupported FPConstant size"); 404 bool Ignored; 405 APFloat APF(Val); 406 APF.convert(APFloat::IEEEhalf(), APFloat::rmNearestTiesToEven, &Ignored); 407 return APF; 408 } 409 410 Optional<APInt> llvm::ConstantFoldBinOp(unsigned Opcode, const Register Op1, 411 const Register Op2, 412 const MachineRegisterInfo &MRI) { 413 auto MaybeOp2Cst = getConstantVRegVal(Op2, MRI); 414 if (!MaybeOp2Cst) 415 return None; 416 417 auto MaybeOp1Cst = getConstantVRegVal(Op1, MRI); 418 if (!MaybeOp1Cst) 419 return None; 420 421 const APInt &C1 = *MaybeOp1Cst; 422 const APInt &C2 = *MaybeOp2Cst; 423 switch (Opcode) { 424 default: 425 break; 426 case TargetOpcode::G_ADD: 427 return C1 + C2; 428 case TargetOpcode::G_AND: 429 return C1 & C2; 430 case TargetOpcode::G_ASHR: 431 return C1.ashr(C2); 432 case TargetOpcode::G_LSHR: 433 return C1.lshr(C2); 434 case TargetOpcode::G_MUL: 435 return C1 * C2; 436 case TargetOpcode::G_OR: 437 return C1 | C2; 438 case TargetOpcode::G_SHL: 439 return C1 << C2; 440 case TargetOpcode::G_SUB: 441 return C1 - C2; 442 case TargetOpcode::G_XOR: 443 return C1 ^ C2; 444 case TargetOpcode::G_UDIV: 445 if (!C2.getBoolValue()) 446 break; 447 return C1.udiv(C2); 448 case TargetOpcode::G_SDIV: 449 if (!C2.getBoolValue()) 450 break; 451 return C1.sdiv(C2); 452 case TargetOpcode::G_UREM: 453 if (!C2.getBoolValue()) 454 break; 455 return C1.urem(C2); 456 case TargetOpcode::G_SREM: 457 if (!C2.getBoolValue()) 458 break; 459 return C1.srem(C2); 460 } 461 462 return None; 463 } 464 465 bool llvm::isKnownNeverNaN(Register Val, const MachineRegisterInfo &MRI, 466 bool SNaN) { 467 const MachineInstr *DefMI = MRI.getVRegDef(Val); 468 if (!DefMI) 469 return false; 470 471 const TargetMachine& TM = DefMI->getMF()->getTarget(); 472 if (DefMI->getFlag(MachineInstr::FmNoNans) || TM.Options.NoNaNsFPMath) 473 return true; 474 475 if (SNaN) { 476 // FP operations quiet. For now, just handle the ones inserted during 477 // legalization. 478 switch (DefMI->getOpcode()) { 479 case TargetOpcode::G_FPEXT: 480 case TargetOpcode::G_FPTRUNC: 481 case TargetOpcode::G_FCANONICALIZE: 482 return true; 483 default: 484 return false; 485 } 486 } 487 488 return false; 489 } 490 491 Align llvm::inferAlignFromPtrInfo(MachineFunction &MF, 492 const MachinePointerInfo &MPO) { 493 auto PSV = MPO.V.dyn_cast<const PseudoSourceValue *>(); 494 if (auto FSPV = dyn_cast_or_null<FixedStackPseudoSourceValue>(PSV)) { 495 MachineFrameInfo &MFI = MF.getFrameInfo(); 496 return commonAlignment(MFI.getObjectAlign(FSPV->getFrameIndex()), 497 MPO.Offset); 498 } 499 500 return Align(1); 501 } 502 503 Register llvm::getFunctionLiveInPhysReg(MachineFunction &MF, 504 const TargetInstrInfo &TII, 505 MCRegister PhysReg, 506 const TargetRegisterClass &RC, 507 LLT RegTy) { 508 DebugLoc DL; // FIXME: Is no location the right choice? 509 MachineBasicBlock &EntryMBB = MF.front(); 510 MachineRegisterInfo &MRI = MF.getRegInfo(); 511 Register LiveIn = MRI.getLiveInVirtReg(PhysReg); 512 if (LiveIn) { 513 MachineInstr *Def = MRI.getVRegDef(LiveIn); 514 if (Def) { 515 // FIXME: Should the verifier check this is in the entry block? 516 assert(Def->getParent() == &EntryMBB && "live-in copy not in entry block"); 517 return LiveIn; 518 } 519 520 // It's possible the incoming argument register and copy was added during 521 // lowering, but later deleted due to being/becoming dead. If this happens, 522 // re-insert the copy. 523 } else { 524 // The live in register was not present, so add it. 525 LiveIn = MF.addLiveIn(PhysReg, &RC); 526 if (RegTy.isValid()) 527 MRI.setType(LiveIn, RegTy); 528 } 529 530 BuildMI(EntryMBB, EntryMBB.begin(), DL, TII.get(TargetOpcode::COPY), LiveIn) 531 .addReg(PhysReg); 532 if (!EntryMBB.isLiveIn(PhysReg)) 533 EntryMBB.addLiveIn(PhysReg); 534 return LiveIn; 535 } 536 537 Optional<APInt> llvm::ConstantFoldExtOp(unsigned Opcode, const Register Op1, 538 uint64_t Imm, 539 const MachineRegisterInfo &MRI) { 540 auto MaybeOp1Cst = getConstantVRegVal(Op1, MRI); 541 if (MaybeOp1Cst) { 542 switch (Opcode) { 543 default: 544 break; 545 case TargetOpcode::G_SEXT_INREG: { 546 LLT Ty = MRI.getType(Op1); 547 return MaybeOp1Cst->trunc(Imm).sext(Ty.getScalarSizeInBits()); 548 } 549 } 550 } 551 return None; 552 } 553 554 void llvm::getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU) { 555 AU.addPreserved<StackProtector>(); 556 } 557 558 static unsigned getLCMSize(unsigned OrigSize, unsigned TargetSize) { 559 unsigned Mul = OrigSize * TargetSize; 560 unsigned GCDSize = greatestCommonDivisor(OrigSize, TargetSize); 561 return Mul / GCDSize; 562 } 563 564 LLT llvm::getLCMType(LLT OrigTy, LLT TargetTy) { 565 const unsigned OrigSize = OrigTy.getSizeInBits(); 566 const unsigned TargetSize = TargetTy.getSizeInBits(); 567 568 if (OrigSize == TargetSize) 569 return OrigTy; 570 571 if (OrigTy.isVector()) { 572 const LLT OrigElt = OrigTy.getElementType(); 573 574 if (TargetTy.isVector()) { 575 const LLT TargetElt = TargetTy.getElementType(); 576 577 if (OrigElt.getSizeInBits() == TargetElt.getSizeInBits()) { 578 int GCDElts = greatestCommonDivisor(OrigTy.getNumElements(), 579 TargetTy.getNumElements()); 580 // Prefer the original element type. 581 int Mul = OrigTy.getNumElements() * TargetTy.getNumElements(); 582 return LLT::vector(Mul / GCDElts, OrigTy.getElementType()); 583 } 584 } else { 585 if (OrigElt.getSizeInBits() == TargetSize) 586 return OrigTy; 587 } 588 589 unsigned LCMSize = getLCMSize(OrigSize, TargetSize); 590 return LLT::vector(LCMSize / OrigElt.getSizeInBits(), OrigElt); 591 } 592 593 if (TargetTy.isVector()) { 594 unsigned LCMSize = getLCMSize(OrigSize, TargetSize); 595 return LLT::vector(LCMSize / OrigSize, OrigTy); 596 } 597 598 unsigned LCMSize = getLCMSize(OrigSize, TargetSize); 599 600 // Preserve pointer types. 601 if (LCMSize == OrigSize) 602 return OrigTy; 603 if (LCMSize == TargetSize) 604 return TargetTy; 605 606 return LLT::scalar(LCMSize); 607 } 608 609 LLT llvm::getGCDType(LLT OrigTy, LLT TargetTy) { 610 const unsigned OrigSize = OrigTy.getSizeInBits(); 611 const unsigned TargetSize = TargetTy.getSizeInBits(); 612 613 if (OrigSize == TargetSize) 614 return OrigTy; 615 616 if (OrigTy.isVector()) { 617 LLT OrigElt = OrigTy.getElementType(); 618 if (TargetTy.isVector()) { 619 LLT TargetElt = TargetTy.getElementType(); 620 if (OrigElt.getSizeInBits() == TargetElt.getSizeInBits()) { 621 int GCD = greatestCommonDivisor(OrigTy.getNumElements(), 622 TargetTy.getNumElements()); 623 return LLT::scalarOrVector(GCD, OrigElt); 624 } 625 } else { 626 // If the source is a vector of pointers, return a pointer element. 627 if (OrigElt.getSizeInBits() == TargetSize) 628 return OrigElt; 629 } 630 631 unsigned GCD = greatestCommonDivisor(OrigSize, TargetSize); 632 if (GCD == OrigElt.getSizeInBits()) 633 return OrigElt; 634 635 // If we can't produce the original element type, we have to use a smaller 636 // scalar. 637 if (GCD < OrigElt.getSizeInBits()) 638 return LLT::scalar(GCD); 639 return LLT::vector(GCD / OrigElt.getSizeInBits(), OrigElt); 640 } 641 642 if (TargetTy.isVector()) { 643 // Try to preserve the original element type. 644 LLT TargetElt = TargetTy.getElementType(); 645 if (TargetElt.getSizeInBits() == OrigSize) 646 return OrigTy; 647 } 648 649 unsigned GCD = greatestCommonDivisor(OrigSize, TargetSize); 650 return LLT::scalar(GCD); 651 } 652 653 Optional<int> llvm::getSplatIndex(MachineInstr &MI) { 654 assert(MI.getOpcode() == TargetOpcode::G_SHUFFLE_VECTOR && 655 "Only G_SHUFFLE_VECTOR can have a splat index!"); 656 ArrayRef<int> Mask = MI.getOperand(3).getShuffleMask(); 657 auto FirstDefinedIdx = find_if(Mask, [](int Elt) { return Elt >= 0; }); 658 659 // If all elements are undefined, this shuffle can be considered a splat. 660 // Return 0 for better potential for callers to simplify. 661 if (FirstDefinedIdx == Mask.end()) 662 return 0; 663 664 // Make sure all remaining elements are either undef or the same 665 // as the first non-undef value. 666 int SplatValue = *FirstDefinedIdx; 667 if (any_of(make_range(std::next(FirstDefinedIdx), Mask.end()), 668 [&SplatValue](int Elt) { return Elt >= 0 && Elt != SplatValue; })) 669 return None; 670 671 return SplatValue; 672 } 673 674 static bool isBuildVectorOp(unsigned Opcode) { 675 return Opcode == TargetOpcode::G_BUILD_VECTOR || 676 Opcode == TargetOpcode::G_BUILD_VECTOR_TRUNC; 677 } 678 679 // TODO: Handle mixed undef elements. 680 static bool isBuildVectorConstantSplat(const MachineInstr &MI, 681 const MachineRegisterInfo &MRI, 682 int64_t SplatValue) { 683 if (!isBuildVectorOp(MI.getOpcode())) 684 return false; 685 686 const unsigned NumOps = MI.getNumOperands(); 687 for (unsigned I = 1; I != NumOps; ++I) { 688 Register Element = MI.getOperand(I).getReg(); 689 if (!mi_match(Element, MRI, m_SpecificICst(SplatValue))) 690 return false; 691 } 692 693 return true; 694 } 695 696 Optional<int64_t> 697 llvm::getBuildVectorConstantSplat(const MachineInstr &MI, 698 const MachineRegisterInfo &MRI) { 699 if (!isBuildVectorOp(MI.getOpcode())) 700 return None; 701 702 const unsigned NumOps = MI.getNumOperands(); 703 Optional<int64_t> Scalar; 704 for (unsigned I = 1; I != NumOps; ++I) { 705 Register Element = MI.getOperand(I).getReg(); 706 int64_t ElementValue; 707 if (!mi_match(Element, MRI, m_ICst(ElementValue))) 708 return None; 709 if (!Scalar) 710 Scalar = ElementValue; 711 else if (*Scalar != ElementValue) 712 return None; 713 } 714 715 return Scalar; 716 } 717 718 bool llvm::isBuildVectorAllZeros(const MachineInstr &MI, 719 const MachineRegisterInfo &MRI) { 720 return isBuildVectorConstantSplat(MI, MRI, 0); 721 } 722 723 bool llvm::isBuildVectorAllOnes(const MachineInstr &MI, 724 const MachineRegisterInfo &MRI) { 725 return isBuildVectorConstantSplat(MI, MRI, -1); 726 } 727 728 bool llvm::isConstTrueVal(const TargetLowering &TLI, int64_t Val, bool IsVector, 729 bool IsFP) { 730 switch (TLI.getBooleanContents(IsVector, IsFP)) { 731 case TargetLowering::UndefinedBooleanContent: 732 return Val & 0x1; 733 case TargetLowering::ZeroOrOneBooleanContent: 734 return Val == 1; 735 case TargetLowering::ZeroOrNegativeOneBooleanContent: 736 return Val == -1; 737 } 738 llvm_unreachable("Invalid boolean contents"); 739 } 740 741 int64_t llvm::getICmpTrueVal(const TargetLowering &TLI, bool IsVector, 742 bool IsFP) { 743 switch (TLI.getBooleanContents(IsVector, IsFP)) { 744 case TargetLowering::UndefinedBooleanContent: 745 case TargetLowering::ZeroOrOneBooleanContent: 746 return 1; 747 case TargetLowering::ZeroOrNegativeOneBooleanContent: 748 return -1; 749 } 750 llvm_unreachable("Invalid boolean contents"); 751 } 752