1 //===- llvm/CodeGen/GlobalISel/Utils.cpp -------------------------*- C++ -*-==// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file This file implements the utility functions used by the GlobalISel 9 /// pipeline. 10 //===----------------------------------------------------------------------===// 11 12 #include "llvm/CodeGen/GlobalISel/Utils.h" 13 #include "llvm/ADT/APFloat.h" 14 #include "llvm/ADT/APInt.h" 15 #include "llvm/ADT/Optional.h" 16 #include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h" 17 #include "llvm/CodeGen/GlobalISel/GISelKnownBits.h" 18 #include "llvm/CodeGen/GlobalISel/MIPatternMatch.h" 19 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h" 20 #include "llvm/CodeGen/MachineInstr.h" 21 #include "llvm/CodeGen/MachineInstrBuilder.h" 22 #include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h" 23 #include "llvm/CodeGen/MachineRegisterInfo.h" 24 #include "llvm/CodeGen/StackProtector.h" 25 #include "llvm/CodeGen/TargetInstrInfo.h" 26 #include "llvm/CodeGen/TargetLowering.h" 27 #include "llvm/CodeGen/TargetPassConfig.h" 28 #include "llvm/CodeGen/TargetRegisterInfo.h" 29 #include "llvm/IR/Constants.h" 30 #include "llvm/Target/TargetMachine.h" 31 32 #define DEBUG_TYPE "globalisel-utils" 33 34 using namespace llvm; 35 using namespace MIPatternMatch; 36 37 Register llvm::constrainRegToClass(MachineRegisterInfo &MRI, 38 const TargetInstrInfo &TII, 39 const RegisterBankInfo &RBI, Register Reg, 40 const TargetRegisterClass &RegClass) { 41 if (!RBI.constrainGenericRegister(Reg, RegClass, MRI)) 42 return MRI.createVirtualRegister(&RegClass); 43 44 return Reg; 45 } 46 47 Register llvm::constrainOperandRegClass( 48 const MachineFunction &MF, const TargetRegisterInfo &TRI, 49 MachineRegisterInfo &MRI, const TargetInstrInfo &TII, 50 const RegisterBankInfo &RBI, MachineInstr &InsertPt, 51 const TargetRegisterClass &RegClass, MachineOperand &RegMO) { 52 Register Reg = RegMO.getReg(); 53 // Assume physical registers are properly constrained. 54 assert(Register::isVirtualRegister(Reg) && "PhysReg not implemented"); 55 56 Register ConstrainedReg = constrainRegToClass(MRI, TII, RBI, Reg, RegClass); 57 // If we created a new virtual register because the class is not compatible 58 // then create a copy between the new and the old register. 59 if (ConstrainedReg != Reg) { 60 MachineBasicBlock::iterator InsertIt(&InsertPt); 61 MachineBasicBlock &MBB = *InsertPt.getParent(); 62 if (RegMO.isUse()) { 63 BuildMI(MBB, InsertIt, InsertPt.getDebugLoc(), 64 TII.get(TargetOpcode::COPY), ConstrainedReg) 65 .addReg(Reg); 66 } else { 67 assert(RegMO.isDef() && "Must be a definition"); 68 BuildMI(MBB, std::next(InsertIt), InsertPt.getDebugLoc(), 69 TII.get(TargetOpcode::COPY), Reg) 70 .addReg(ConstrainedReg); 71 } 72 if (GISelChangeObserver *Observer = MF.getObserver()) { 73 Observer->changingInstr(*RegMO.getParent()); 74 } 75 RegMO.setReg(ConstrainedReg); 76 if (GISelChangeObserver *Observer = MF.getObserver()) { 77 Observer->changedInstr(*RegMO.getParent()); 78 } 79 } else { 80 if (GISelChangeObserver *Observer = MF.getObserver()) { 81 if (!RegMO.isDef()) { 82 MachineInstr *RegDef = MRI.getVRegDef(Reg); 83 Observer->changedInstr(*RegDef); 84 } 85 Observer->changingAllUsesOfReg(MRI, Reg); 86 Observer->finishedChangingAllUsesOfReg(); 87 } 88 } 89 return ConstrainedReg; 90 } 91 92 Register llvm::constrainOperandRegClass( 93 const MachineFunction &MF, const TargetRegisterInfo &TRI, 94 MachineRegisterInfo &MRI, const TargetInstrInfo &TII, 95 const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II, 96 MachineOperand &RegMO, unsigned OpIdx) { 97 Register Reg = RegMO.getReg(); 98 // Assume physical registers are properly constrained. 99 assert(Register::isVirtualRegister(Reg) && "PhysReg not implemented"); 100 101 const TargetRegisterClass *RegClass = TII.getRegClass(II, OpIdx, &TRI, MF); 102 // Some of the target independent instructions, like COPY, may not impose any 103 // register class constraints on some of their operands: If it's a use, we can 104 // skip constraining as the instruction defining the register would constrain 105 // it. 106 107 // We can't constrain unallocatable register classes, because we can't create 108 // virtual registers for these classes, so we need to let targets handled this 109 // case. 110 if (RegClass && !RegClass->isAllocatable()) 111 RegClass = TRI.getConstrainedRegClassForOperand(RegMO, MRI); 112 113 if (!RegClass) { 114 assert((!isTargetSpecificOpcode(II.getOpcode()) || RegMO.isUse()) && 115 "Register class constraint is required unless either the " 116 "instruction is target independent or the operand is a use"); 117 // FIXME: Just bailing out like this here could be not enough, unless we 118 // expect the users of this function to do the right thing for PHIs and 119 // COPY: 120 // v1 = COPY v0 121 // v2 = COPY v1 122 // v1 here may end up not being constrained at all. Please notice that to 123 // reproduce the issue we likely need a destination pattern of a selection 124 // rule producing such extra copies, not just an input GMIR with them as 125 // every existing target using selectImpl handles copies before calling it 126 // and they never reach this function. 127 return Reg; 128 } 129 return constrainOperandRegClass(MF, TRI, MRI, TII, RBI, InsertPt, *RegClass, 130 RegMO); 131 } 132 133 bool llvm::constrainSelectedInstRegOperands(MachineInstr &I, 134 const TargetInstrInfo &TII, 135 const TargetRegisterInfo &TRI, 136 const RegisterBankInfo &RBI) { 137 assert(!isPreISelGenericOpcode(I.getOpcode()) && 138 "A selected instruction is expected"); 139 MachineBasicBlock &MBB = *I.getParent(); 140 MachineFunction &MF = *MBB.getParent(); 141 MachineRegisterInfo &MRI = MF.getRegInfo(); 142 143 for (unsigned OpI = 0, OpE = I.getNumExplicitOperands(); OpI != OpE; ++OpI) { 144 MachineOperand &MO = I.getOperand(OpI); 145 146 // There's nothing to be done on non-register operands. 147 if (!MO.isReg()) 148 continue; 149 150 LLVM_DEBUG(dbgs() << "Converting operand: " << MO << '\n'); 151 assert(MO.isReg() && "Unsupported non-reg operand"); 152 153 Register Reg = MO.getReg(); 154 // Physical registers don't need to be constrained. 155 if (Register::isPhysicalRegister(Reg)) 156 continue; 157 158 // Register operands with a value of 0 (e.g. predicate operands) don't need 159 // to be constrained. 160 if (Reg == 0) 161 continue; 162 163 // If the operand is a vreg, we should constrain its regclass, and only 164 // insert COPYs if that's impossible. 165 // constrainOperandRegClass does that for us. 166 constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, I.getDesc(), MO, OpI); 167 168 // Tie uses to defs as indicated in MCInstrDesc if this hasn't already been 169 // done. 170 if (MO.isUse()) { 171 int DefIdx = I.getDesc().getOperandConstraint(OpI, MCOI::TIED_TO); 172 if (DefIdx != -1 && !I.isRegTiedToUseOperand(DefIdx)) 173 I.tieOperands(DefIdx, OpI); 174 } 175 } 176 return true; 177 } 178 179 bool llvm::canReplaceReg(Register DstReg, Register SrcReg, 180 MachineRegisterInfo &MRI) { 181 // Give up if either DstReg or SrcReg is a physical register. 182 if (DstReg.isPhysical() || SrcReg.isPhysical()) 183 return false; 184 // Give up if the types don't match. 185 if (MRI.getType(DstReg) != MRI.getType(SrcReg)) 186 return false; 187 // Replace if either DstReg has no constraints or the register 188 // constraints match. 189 return !MRI.getRegClassOrRegBank(DstReg) || 190 MRI.getRegClassOrRegBank(DstReg) == MRI.getRegClassOrRegBank(SrcReg); 191 } 192 193 bool llvm::isTriviallyDead(const MachineInstr &MI, 194 const MachineRegisterInfo &MRI) { 195 // FIXME: This logical is mostly duplicated with 196 // DeadMachineInstructionElim::isDead. Why is LOCAL_ESCAPE not considered in 197 // MachineInstr::isLabel? 198 199 // Don't delete frame allocation labels. 200 if (MI.getOpcode() == TargetOpcode::LOCAL_ESCAPE) 201 return false; 202 203 // If we can move an instruction, we can remove it. Otherwise, it has 204 // a side-effect of some sort. 205 bool SawStore = false; 206 if (!MI.isSafeToMove(/*AA=*/nullptr, SawStore) && !MI.isPHI()) 207 return false; 208 209 // Instructions without side-effects are dead iff they only define dead vregs. 210 for (auto &MO : MI.operands()) { 211 if (!MO.isReg() || !MO.isDef()) 212 continue; 213 214 Register Reg = MO.getReg(); 215 if (Register::isPhysicalRegister(Reg) || !MRI.use_nodbg_empty(Reg)) 216 return false; 217 } 218 return true; 219 } 220 221 static void reportGISelDiagnostic(DiagnosticSeverity Severity, 222 MachineFunction &MF, 223 const TargetPassConfig &TPC, 224 MachineOptimizationRemarkEmitter &MORE, 225 MachineOptimizationRemarkMissed &R) { 226 bool IsFatal = Severity == DS_Error && 227 TPC.isGlobalISelAbortEnabled(); 228 // Print the function name explicitly if we don't have a debug location (which 229 // makes the diagnostic less useful) or if we're going to emit a raw error. 230 if (!R.getLocation().isValid() || IsFatal) 231 R << (" (in function: " + MF.getName() + ")").str(); 232 233 if (IsFatal) 234 report_fatal_error(R.getMsg()); 235 else 236 MORE.emit(R); 237 } 238 239 void llvm::reportGISelWarning(MachineFunction &MF, const TargetPassConfig &TPC, 240 MachineOptimizationRemarkEmitter &MORE, 241 MachineOptimizationRemarkMissed &R) { 242 reportGISelDiagnostic(DS_Warning, MF, TPC, MORE, R); 243 } 244 245 void llvm::reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, 246 MachineOptimizationRemarkEmitter &MORE, 247 MachineOptimizationRemarkMissed &R) { 248 MF.getProperties().set(MachineFunctionProperties::Property::FailedISel); 249 reportGISelDiagnostic(DS_Error, MF, TPC, MORE, R); 250 } 251 252 void llvm::reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, 253 MachineOptimizationRemarkEmitter &MORE, 254 const char *PassName, StringRef Msg, 255 const MachineInstr &MI) { 256 MachineOptimizationRemarkMissed R(PassName, "GISelFailure: ", 257 MI.getDebugLoc(), MI.getParent()); 258 R << Msg; 259 // Printing MI is expensive; only do it if expensive remarks are enabled. 260 if (TPC.isGlobalISelAbortEnabled() || MORE.allowExtraAnalysis(PassName)) 261 R << ": " << ore::MNV("Inst", MI); 262 reportGISelFailure(MF, TPC, MORE, R); 263 } 264 265 Optional<APInt> llvm::getConstantVRegVal(Register VReg, 266 const MachineRegisterInfo &MRI) { 267 Optional<ValueAndVReg> ValAndVReg = 268 getConstantVRegValWithLookThrough(VReg, MRI, /*LookThroughInstrs*/ false); 269 assert((!ValAndVReg || ValAndVReg->VReg == VReg) && 270 "Value found while looking through instrs"); 271 if (!ValAndVReg) 272 return None; 273 return ValAndVReg->Value; 274 } 275 276 Optional<int64_t> llvm::getConstantVRegSExtVal(Register VReg, 277 const MachineRegisterInfo &MRI) { 278 Optional<APInt> Val = getConstantVRegVal(VReg, MRI); 279 if (Val && Val->getBitWidth() <= 64) 280 return Val->getSExtValue(); 281 return None; 282 } 283 284 Optional<ValueAndVReg> llvm::getConstantVRegValWithLookThrough( 285 Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs, 286 bool HandleFConstant) { 287 SmallVector<std::pair<unsigned, unsigned>, 4> SeenOpcodes; 288 MachineInstr *MI; 289 auto IsConstantOpcode = [HandleFConstant](unsigned Opcode) { 290 return Opcode == TargetOpcode::G_CONSTANT || 291 (HandleFConstant && Opcode == TargetOpcode::G_FCONSTANT); 292 }; 293 auto GetImmediateValue = [HandleFConstant, 294 &MRI](const MachineInstr &MI) -> Optional<APInt> { 295 const MachineOperand &CstVal = MI.getOperand(1); 296 if (!CstVal.isImm() && !CstVal.isCImm() && 297 (!HandleFConstant || !CstVal.isFPImm())) 298 return None; 299 if (!CstVal.isFPImm()) { 300 unsigned BitWidth = 301 MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); 302 APInt Val = CstVal.isImm() ? APInt(BitWidth, CstVal.getImm()) 303 : CstVal.getCImm()->getValue(); 304 assert(Val.getBitWidth() == BitWidth && 305 "Value bitwidth doesn't match definition type"); 306 return Val; 307 } 308 return CstVal.getFPImm()->getValueAPF().bitcastToAPInt(); 309 }; 310 while ((MI = MRI.getVRegDef(VReg)) && !IsConstantOpcode(MI->getOpcode()) && 311 LookThroughInstrs) { 312 switch (MI->getOpcode()) { 313 case TargetOpcode::G_TRUNC: 314 case TargetOpcode::G_SEXT: 315 case TargetOpcode::G_ZEXT: 316 SeenOpcodes.push_back(std::make_pair( 317 MI->getOpcode(), 318 MRI.getType(MI->getOperand(0).getReg()).getSizeInBits())); 319 VReg = MI->getOperand(1).getReg(); 320 break; 321 case TargetOpcode::COPY: 322 VReg = MI->getOperand(1).getReg(); 323 if (Register::isPhysicalRegister(VReg)) 324 return None; 325 break; 326 case TargetOpcode::G_INTTOPTR: 327 VReg = MI->getOperand(1).getReg(); 328 break; 329 default: 330 return None; 331 } 332 } 333 if (!MI || !IsConstantOpcode(MI->getOpcode())) 334 return None; 335 336 Optional<APInt> MaybeVal = GetImmediateValue(*MI); 337 if (!MaybeVal) 338 return None; 339 APInt &Val = *MaybeVal; 340 while (!SeenOpcodes.empty()) { 341 std::pair<unsigned, unsigned> OpcodeAndSize = SeenOpcodes.pop_back_val(); 342 switch (OpcodeAndSize.first) { 343 case TargetOpcode::G_TRUNC: 344 Val = Val.trunc(OpcodeAndSize.second); 345 break; 346 case TargetOpcode::G_SEXT: 347 Val = Val.sext(OpcodeAndSize.second); 348 break; 349 case TargetOpcode::G_ZEXT: 350 Val = Val.zext(OpcodeAndSize.second); 351 break; 352 } 353 } 354 355 return ValueAndVReg{Val, VReg}; 356 } 357 358 const ConstantFP * 359 llvm::getConstantFPVRegVal(Register VReg, const MachineRegisterInfo &MRI) { 360 MachineInstr *MI = MRI.getVRegDef(VReg); 361 if (TargetOpcode::G_FCONSTANT != MI->getOpcode()) 362 return nullptr; 363 return MI->getOperand(1).getFPImm(); 364 } 365 366 Optional<DefinitionAndSourceRegister> 367 llvm::getDefSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI) { 368 Register DefSrcReg = Reg; 369 auto *DefMI = MRI.getVRegDef(Reg); 370 auto DstTy = MRI.getType(DefMI->getOperand(0).getReg()); 371 if (!DstTy.isValid()) 372 return None; 373 while (DefMI->getOpcode() == TargetOpcode::COPY) { 374 Register SrcReg = DefMI->getOperand(1).getReg(); 375 auto SrcTy = MRI.getType(SrcReg); 376 if (!SrcTy.isValid()) 377 break; 378 DefMI = MRI.getVRegDef(SrcReg); 379 DefSrcReg = SrcReg; 380 } 381 return DefinitionAndSourceRegister{DefMI, DefSrcReg}; 382 } 383 384 MachineInstr *llvm::getDefIgnoringCopies(Register Reg, 385 const MachineRegisterInfo &MRI) { 386 Optional<DefinitionAndSourceRegister> DefSrcReg = 387 getDefSrcRegIgnoringCopies(Reg, MRI); 388 return DefSrcReg ? DefSrcReg->MI : nullptr; 389 } 390 391 Register llvm::getSrcRegIgnoringCopies(Register Reg, 392 const MachineRegisterInfo &MRI) { 393 Optional<DefinitionAndSourceRegister> DefSrcReg = 394 getDefSrcRegIgnoringCopies(Reg, MRI); 395 return DefSrcReg ? DefSrcReg->Reg : Register(); 396 } 397 398 MachineInstr *llvm::getOpcodeDef(unsigned Opcode, Register Reg, 399 const MachineRegisterInfo &MRI) { 400 MachineInstr *DefMI = getDefIgnoringCopies(Reg, MRI); 401 return DefMI && DefMI->getOpcode() == Opcode ? DefMI : nullptr; 402 } 403 404 APFloat llvm::getAPFloatFromSize(double Val, unsigned Size) { 405 if (Size == 32) 406 return APFloat(float(Val)); 407 if (Size == 64) 408 return APFloat(Val); 409 if (Size != 16) 410 llvm_unreachable("Unsupported FPConstant size"); 411 bool Ignored; 412 APFloat APF(Val); 413 APF.convert(APFloat::IEEEhalf(), APFloat::rmNearestTiesToEven, &Ignored); 414 return APF; 415 } 416 417 Optional<APInt> llvm::ConstantFoldBinOp(unsigned Opcode, const Register Op1, 418 const Register Op2, 419 const MachineRegisterInfo &MRI) { 420 auto MaybeOp2Cst = getConstantVRegVal(Op2, MRI); 421 if (!MaybeOp2Cst) 422 return None; 423 424 auto MaybeOp1Cst = getConstantVRegVal(Op1, MRI); 425 if (!MaybeOp1Cst) 426 return None; 427 428 const APInt &C1 = *MaybeOp1Cst; 429 const APInt &C2 = *MaybeOp2Cst; 430 switch (Opcode) { 431 default: 432 break; 433 case TargetOpcode::G_ADD: 434 return C1 + C2; 435 case TargetOpcode::G_AND: 436 return C1 & C2; 437 case TargetOpcode::G_ASHR: 438 return C1.ashr(C2); 439 case TargetOpcode::G_LSHR: 440 return C1.lshr(C2); 441 case TargetOpcode::G_MUL: 442 return C1 * C2; 443 case TargetOpcode::G_OR: 444 return C1 | C2; 445 case TargetOpcode::G_SHL: 446 return C1 << C2; 447 case TargetOpcode::G_SUB: 448 return C1 - C2; 449 case TargetOpcode::G_XOR: 450 return C1 ^ C2; 451 case TargetOpcode::G_UDIV: 452 if (!C2.getBoolValue()) 453 break; 454 return C1.udiv(C2); 455 case TargetOpcode::G_SDIV: 456 if (!C2.getBoolValue()) 457 break; 458 return C1.sdiv(C2); 459 case TargetOpcode::G_UREM: 460 if (!C2.getBoolValue()) 461 break; 462 return C1.urem(C2); 463 case TargetOpcode::G_SREM: 464 if (!C2.getBoolValue()) 465 break; 466 return C1.srem(C2); 467 } 468 469 return None; 470 } 471 472 bool llvm::isKnownNeverNaN(Register Val, const MachineRegisterInfo &MRI, 473 bool SNaN) { 474 const MachineInstr *DefMI = MRI.getVRegDef(Val); 475 if (!DefMI) 476 return false; 477 478 const TargetMachine& TM = DefMI->getMF()->getTarget(); 479 if (DefMI->getFlag(MachineInstr::FmNoNans) || TM.Options.NoNaNsFPMath) 480 return true; 481 482 if (SNaN) { 483 // FP operations quiet. For now, just handle the ones inserted during 484 // legalization. 485 switch (DefMI->getOpcode()) { 486 case TargetOpcode::G_FPEXT: 487 case TargetOpcode::G_FPTRUNC: 488 case TargetOpcode::G_FCANONICALIZE: 489 return true; 490 default: 491 return false; 492 } 493 } 494 495 return false; 496 } 497 498 Align llvm::inferAlignFromPtrInfo(MachineFunction &MF, 499 const MachinePointerInfo &MPO) { 500 auto PSV = MPO.V.dyn_cast<const PseudoSourceValue *>(); 501 if (auto FSPV = dyn_cast_or_null<FixedStackPseudoSourceValue>(PSV)) { 502 MachineFrameInfo &MFI = MF.getFrameInfo(); 503 return commonAlignment(MFI.getObjectAlign(FSPV->getFrameIndex()), 504 MPO.Offset); 505 } 506 507 return Align(1); 508 } 509 510 Register llvm::getFunctionLiveInPhysReg(MachineFunction &MF, 511 const TargetInstrInfo &TII, 512 MCRegister PhysReg, 513 const TargetRegisterClass &RC, 514 LLT RegTy) { 515 DebugLoc DL; // FIXME: Is no location the right choice? 516 MachineBasicBlock &EntryMBB = MF.front(); 517 MachineRegisterInfo &MRI = MF.getRegInfo(); 518 Register LiveIn = MRI.getLiveInVirtReg(PhysReg); 519 if (LiveIn) { 520 MachineInstr *Def = MRI.getVRegDef(LiveIn); 521 if (Def) { 522 // FIXME: Should the verifier check this is in the entry block? 523 assert(Def->getParent() == &EntryMBB && "live-in copy not in entry block"); 524 return LiveIn; 525 } 526 527 // It's possible the incoming argument register and copy was added during 528 // lowering, but later deleted due to being/becoming dead. If this happens, 529 // re-insert the copy. 530 } else { 531 // The live in register was not present, so add it. 532 LiveIn = MF.addLiveIn(PhysReg, &RC); 533 if (RegTy.isValid()) 534 MRI.setType(LiveIn, RegTy); 535 } 536 537 BuildMI(EntryMBB, EntryMBB.begin(), DL, TII.get(TargetOpcode::COPY), LiveIn) 538 .addReg(PhysReg); 539 if (!EntryMBB.isLiveIn(PhysReg)) 540 EntryMBB.addLiveIn(PhysReg); 541 return LiveIn; 542 } 543 544 Optional<APInt> llvm::ConstantFoldExtOp(unsigned Opcode, const Register Op1, 545 uint64_t Imm, 546 const MachineRegisterInfo &MRI) { 547 auto MaybeOp1Cst = getConstantVRegVal(Op1, MRI); 548 if (MaybeOp1Cst) { 549 switch (Opcode) { 550 default: 551 break; 552 case TargetOpcode::G_SEXT_INREG: { 553 LLT Ty = MRI.getType(Op1); 554 return MaybeOp1Cst->trunc(Imm).sext(Ty.getScalarSizeInBits()); 555 } 556 } 557 } 558 return None; 559 } 560 561 bool llvm::isKnownToBeAPowerOfTwo(Register Reg, const MachineRegisterInfo &MRI, 562 GISelKnownBits *KB) { 563 Optional<DefinitionAndSourceRegister> DefSrcReg = 564 getDefSrcRegIgnoringCopies(Reg, MRI); 565 if (!DefSrcReg) 566 return false; 567 568 const MachineInstr &MI = *DefSrcReg->MI; 569 const LLT Ty = MRI.getType(Reg); 570 571 switch (MI.getOpcode()) { 572 case TargetOpcode::G_CONSTANT: { 573 unsigned BitWidth = Ty.getScalarSizeInBits(); 574 const ConstantInt *CI = MI.getOperand(1).getCImm(); 575 return CI->getValue().zextOrTrunc(BitWidth).isPowerOf2(); 576 } 577 case TargetOpcode::G_SHL: { 578 // A left-shift of a constant one will have exactly one bit set because 579 // shifting the bit off the end is undefined. 580 581 // TODO: Constant splat 582 if (auto ConstLHS = getConstantVRegVal(MI.getOperand(1).getReg(), MRI)) { 583 if (*ConstLHS == 1) 584 return true; 585 } 586 587 break; 588 } 589 case TargetOpcode::G_LSHR: { 590 if (auto ConstLHS = getConstantVRegVal(MI.getOperand(1).getReg(), MRI)) { 591 if (ConstLHS->isSignMask()) 592 return true; 593 } 594 595 break; 596 } 597 default: 598 break; 599 } 600 601 // TODO: Are all operands of a build vector constant powers of two? 602 if (!KB) 603 return false; 604 605 // More could be done here, though the above checks are enough 606 // to handle some common cases. 607 608 // Fall back to computeKnownBits to catch other known cases. 609 KnownBits Known = KB->getKnownBits(Reg); 610 return (Known.countMaxPopulation() == 1) && (Known.countMinPopulation() == 1); 611 } 612 613 void llvm::getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU) { 614 AU.addPreserved<StackProtector>(); 615 } 616 617 static unsigned getLCMSize(unsigned OrigSize, unsigned TargetSize) { 618 unsigned Mul = OrigSize * TargetSize; 619 unsigned GCDSize = greatestCommonDivisor(OrigSize, TargetSize); 620 return Mul / GCDSize; 621 } 622 623 LLT llvm::getLCMType(LLT OrigTy, LLT TargetTy) { 624 const unsigned OrigSize = OrigTy.getSizeInBits(); 625 const unsigned TargetSize = TargetTy.getSizeInBits(); 626 627 if (OrigSize == TargetSize) 628 return OrigTy; 629 630 if (OrigTy.isVector()) { 631 const LLT OrigElt = OrigTy.getElementType(); 632 633 if (TargetTy.isVector()) { 634 const LLT TargetElt = TargetTy.getElementType(); 635 636 if (OrigElt.getSizeInBits() == TargetElt.getSizeInBits()) { 637 int GCDElts = greatestCommonDivisor(OrigTy.getNumElements(), 638 TargetTy.getNumElements()); 639 // Prefer the original element type. 640 int Mul = OrigTy.getNumElements() * TargetTy.getNumElements(); 641 return LLT::vector(Mul / GCDElts, OrigTy.getElementType()); 642 } 643 } else { 644 if (OrigElt.getSizeInBits() == TargetSize) 645 return OrigTy; 646 } 647 648 unsigned LCMSize = getLCMSize(OrigSize, TargetSize); 649 return LLT::vector(LCMSize / OrigElt.getSizeInBits(), OrigElt); 650 } 651 652 if (TargetTy.isVector()) { 653 unsigned LCMSize = getLCMSize(OrigSize, TargetSize); 654 return LLT::vector(LCMSize / OrigSize, OrigTy); 655 } 656 657 unsigned LCMSize = getLCMSize(OrigSize, TargetSize); 658 659 // Preserve pointer types. 660 if (LCMSize == OrigSize) 661 return OrigTy; 662 if (LCMSize == TargetSize) 663 return TargetTy; 664 665 return LLT::scalar(LCMSize); 666 } 667 668 LLT llvm::getGCDType(LLT OrigTy, LLT TargetTy) { 669 const unsigned OrigSize = OrigTy.getSizeInBits(); 670 const unsigned TargetSize = TargetTy.getSizeInBits(); 671 672 if (OrigSize == TargetSize) 673 return OrigTy; 674 675 if (OrigTy.isVector()) { 676 LLT OrigElt = OrigTy.getElementType(); 677 if (TargetTy.isVector()) { 678 LLT TargetElt = TargetTy.getElementType(); 679 if (OrigElt.getSizeInBits() == TargetElt.getSizeInBits()) { 680 int GCD = greatestCommonDivisor(OrigTy.getNumElements(), 681 TargetTy.getNumElements()); 682 return LLT::scalarOrVector(GCD, OrigElt); 683 } 684 } else { 685 // If the source is a vector of pointers, return a pointer element. 686 if (OrigElt.getSizeInBits() == TargetSize) 687 return OrigElt; 688 } 689 690 unsigned GCD = greatestCommonDivisor(OrigSize, TargetSize); 691 if (GCD == OrigElt.getSizeInBits()) 692 return OrigElt; 693 694 // If we can't produce the original element type, we have to use a smaller 695 // scalar. 696 if (GCD < OrigElt.getSizeInBits()) 697 return LLT::scalar(GCD); 698 return LLT::vector(GCD / OrigElt.getSizeInBits(), OrigElt); 699 } 700 701 if (TargetTy.isVector()) { 702 // Try to preserve the original element type. 703 LLT TargetElt = TargetTy.getElementType(); 704 if (TargetElt.getSizeInBits() == OrigSize) 705 return OrigTy; 706 } 707 708 unsigned GCD = greatestCommonDivisor(OrigSize, TargetSize); 709 return LLT::scalar(GCD); 710 } 711 712 Optional<int> llvm::getSplatIndex(MachineInstr &MI) { 713 assert(MI.getOpcode() == TargetOpcode::G_SHUFFLE_VECTOR && 714 "Only G_SHUFFLE_VECTOR can have a splat index!"); 715 ArrayRef<int> Mask = MI.getOperand(3).getShuffleMask(); 716 auto FirstDefinedIdx = find_if(Mask, [](int Elt) { return Elt >= 0; }); 717 718 // If all elements are undefined, this shuffle can be considered a splat. 719 // Return 0 for better potential for callers to simplify. 720 if (FirstDefinedIdx == Mask.end()) 721 return 0; 722 723 // Make sure all remaining elements are either undef or the same 724 // as the first non-undef value. 725 int SplatValue = *FirstDefinedIdx; 726 if (any_of(make_range(std::next(FirstDefinedIdx), Mask.end()), 727 [&SplatValue](int Elt) { return Elt >= 0 && Elt != SplatValue; })) 728 return None; 729 730 return SplatValue; 731 } 732 733 static bool isBuildVectorOp(unsigned Opcode) { 734 return Opcode == TargetOpcode::G_BUILD_VECTOR || 735 Opcode == TargetOpcode::G_BUILD_VECTOR_TRUNC; 736 } 737 738 // TODO: Handle mixed undef elements. 739 static bool isBuildVectorConstantSplat(const MachineInstr &MI, 740 const MachineRegisterInfo &MRI, 741 int64_t SplatValue) { 742 if (!isBuildVectorOp(MI.getOpcode())) 743 return false; 744 745 const unsigned NumOps = MI.getNumOperands(); 746 for (unsigned I = 1; I != NumOps; ++I) { 747 Register Element = MI.getOperand(I).getReg(); 748 if (!mi_match(Element, MRI, m_SpecificICst(SplatValue))) 749 return false; 750 } 751 752 return true; 753 } 754 755 Optional<int64_t> 756 llvm::getBuildVectorConstantSplat(const MachineInstr &MI, 757 const MachineRegisterInfo &MRI) { 758 if (!isBuildVectorOp(MI.getOpcode())) 759 return None; 760 761 const unsigned NumOps = MI.getNumOperands(); 762 Optional<int64_t> Scalar; 763 for (unsigned I = 1; I != NumOps; ++I) { 764 Register Element = MI.getOperand(I).getReg(); 765 int64_t ElementValue; 766 if (!mi_match(Element, MRI, m_ICst(ElementValue))) 767 return None; 768 if (!Scalar) 769 Scalar = ElementValue; 770 else if (*Scalar != ElementValue) 771 return None; 772 } 773 774 return Scalar; 775 } 776 777 bool llvm::isBuildVectorAllZeros(const MachineInstr &MI, 778 const MachineRegisterInfo &MRI) { 779 return isBuildVectorConstantSplat(MI, MRI, 0); 780 } 781 782 bool llvm::isBuildVectorAllOnes(const MachineInstr &MI, 783 const MachineRegisterInfo &MRI) { 784 return isBuildVectorConstantSplat(MI, MRI, -1); 785 } 786 787 bool llvm::isConstTrueVal(const TargetLowering &TLI, int64_t Val, bool IsVector, 788 bool IsFP) { 789 switch (TLI.getBooleanContents(IsVector, IsFP)) { 790 case TargetLowering::UndefinedBooleanContent: 791 return Val & 0x1; 792 case TargetLowering::ZeroOrOneBooleanContent: 793 return Val == 1; 794 case TargetLowering::ZeroOrNegativeOneBooleanContent: 795 return Val == -1; 796 } 797 llvm_unreachable("Invalid boolean contents"); 798 } 799 800 int64_t llvm::getICmpTrueVal(const TargetLowering &TLI, bool IsVector, 801 bool IsFP) { 802 switch (TLI.getBooleanContents(IsVector, IsFP)) { 803 case TargetLowering::UndefinedBooleanContent: 804 case TargetLowering::ZeroOrOneBooleanContent: 805 return 1; 806 case TargetLowering::ZeroOrNegativeOneBooleanContent: 807 return -1; 808 } 809 llvm_unreachable("Invalid boolean contents"); 810 } 811