1 //===- llvm/CodeGen/GlobalISel/InstructionSelector.cpp --------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 /// \file 11 /// This file implements the InstructionSelector class. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h" 16 #include "llvm/CodeGen/GlobalISel/Utils.h" 17 #include "llvm/CodeGen/MachineBasicBlock.h" 18 #include "llvm/CodeGen/MachineFunction.h" 19 #include "llvm/CodeGen/MachineInstr.h" 20 #include "llvm/CodeGen/MachineOperand.h" 21 #include "llvm/MC/MCInstrDesc.h" 22 #include "llvm/Support/Debug.h" 23 #include "llvm/Support/raw_ostream.h" 24 #include "llvm/Target/TargetRegisterInfo.h" 25 #include <cassert> 26 27 #define DEBUG_TYPE "instructionselector" 28 29 using namespace llvm; 30 31 InstructionSelector::MatcherState::MatcherState(unsigned MaxRenderers) 32 : Renderers(MaxRenderers, nullptr), MIs() {} 33 34 InstructionSelector::InstructionSelector() = default; 35 36 bool InstructionSelector::constrainOperandRegToRegClass( 37 MachineInstr &I, unsigned OpIdx, const TargetRegisterClass &RC, 38 const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, 39 const RegisterBankInfo &RBI) const { 40 MachineBasicBlock &MBB = *I.getParent(); 41 MachineFunction &MF = *MBB.getParent(); 42 MachineRegisterInfo &MRI = MF.getRegInfo(); 43 44 return 45 constrainRegToClass(MRI, TII, RBI, I, I.getOperand(OpIdx).getReg(), RC); 46 } 47 48 bool InstructionSelector::constrainSelectedInstRegOperands( 49 MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, 50 const RegisterBankInfo &RBI) const { 51 MachineBasicBlock &MBB = *I.getParent(); 52 MachineFunction &MF = *MBB.getParent(); 53 MachineRegisterInfo &MRI = MF.getRegInfo(); 54 55 for (unsigned OpI = 0, OpE = I.getNumExplicitOperands(); OpI != OpE; ++OpI) { 56 MachineOperand &MO = I.getOperand(OpI); 57 58 // There's nothing to be done on non-register operands. 59 if (!MO.isReg()) 60 continue; 61 62 DEBUG(dbgs() << "Converting operand: " << MO << '\n'); 63 assert(MO.isReg() && "Unsupported non-reg operand"); 64 65 unsigned Reg = MO.getReg(); 66 // Physical registers don't need to be constrained. 67 if (TRI.isPhysicalRegister(Reg)) 68 continue; 69 70 // Register operands with a value of 0 (e.g. predicate operands) don't need 71 // to be constrained. 72 if (Reg == 0) 73 continue; 74 75 // If the operand is a vreg, we should constrain its regclass, and only 76 // insert COPYs if that's impossible. 77 // constrainOperandRegClass does that for us. 78 MO.setReg(constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, I.getDesc(), 79 Reg, OpI)); 80 81 // Tie uses to defs as indicated in MCInstrDesc if this hasn't already been 82 // done. 83 if (MO.isUse()) { 84 int DefIdx = I.getDesc().getOperandConstraint(OpI, MCOI::TIED_TO); 85 if (DefIdx != -1 && !I.isRegTiedToUseOperand(DefIdx)) 86 I.tieOperands(DefIdx, OpI); 87 } 88 } 89 return true; 90 } 91 92 bool InstructionSelector::isOperandImmEqual( 93 const MachineOperand &MO, int64_t Value, 94 const MachineRegisterInfo &MRI) const { 95 if (MO.isReg() && MO.getReg()) 96 if (auto VRegVal = getConstantVRegVal(MO.getReg(), MRI)) 97 return *VRegVal == Value; 98 return false; 99 } 100 101 bool InstructionSelector::isObviouslySafeToFold(MachineInstr &MI) const { 102 return !MI.mayLoadOrStore() && !MI.hasUnmodeledSideEffects() && 103 MI.implicit_operands().begin() == MI.implicit_operands().end(); 104 } 105