1 //===- llvm/CodeGen/GlobalISel/InstructionSelector.cpp --------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 /// \file 11 /// This file implements the InstructionSelector class. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h" 16 #include "llvm/CodeGen/GlobalISel/Utils.h" 17 #include "llvm/CodeGen/MachineBasicBlock.h" 18 #include "llvm/CodeGen/MachineFunction.h" 19 #include "llvm/CodeGen/MachineInstr.h" 20 #include "llvm/CodeGen/MachineOperand.h" 21 #include "llvm/CodeGen/MachineRegisterInfo.h" 22 #include "llvm/CodeGen/TargetRegisterInfo.h" 23 #include "llvm/MC/MCInstrDesc.h" 24 #include "llvm/Support/Debug.h" 25 #include "llvm/Support/raw_ostream.h" 26 #include <cassert> 27 28 #define DEBUG_TYPE "instructionselector" 29 30 using namespace llvm; 31 32 InstructionSelector::MatcherState::MatcherState(unsigned MaxRenderers) 33 : Renderers(MaxRenderers), MIs() {} 34 35 InstructionSelector::InstructionSelector() = default; 36 37 bool InstructionSelector::constrainOperandRegToRegClass( 38 MachineInstr &I, unsigned OpIdx, const TargetRegisterClass &RC, 39 const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, 40 const RegisterBankInfo &RBI) const { 41 MachineBasicBlock &MBB = *I.getParent(); 42 MachineFunction &MF = *MBB.getParent(); 43 MachineRegisterInfo &MRI = MF.getRegInfo(); 44 45 return 46 constrainRegToClass(MRI, TII, RBI, I, I.getOperand(OpIdx).getReg(), RC); 47 } 48 49 bool InstructionSelector::constrainSelectedInstRegOperands( 50 MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, 51 const RegisterBankInfo &RBI) const { 52 MachineBasicBlock &MBB = *I.getParent(); 53 MachineFunction &MF = *MBB.getParent(); 54 MachineRegisterInfo &MRI = MF.getRegInfo(); 55 56 for (unsigned OpI = 0, OpE = I.getNumExplicitOperands(); OpI != OpE; ++OpI) { 57 MachineOperand &MO = I.getOperand(OpI); 58 59 // There's nothing to be done on non-register operands. 60 if (!MO.isReg()) 61 continue; 62 63 DEBUG(dbgs() << "Converting operand: " << MO << '\n'); 64 assert(MO.isReg() && "Unsupported non-reg operand"); 65 66 unsigned Reg = MO.getReg(); 67 // Physical registers don't need to be constrained. 68 if (TRI.isPhysicalRegister(Reg)) 69 continue; 70 71 // Register operands with a value of 0 (e.g. predicate operands) don't need 72 // to be constrained. 73 if (Reg == 0) 74 continue; 75 76 // If the operand is a vreg, we should constrain its regclass, and only 77 // insert COPYs if that's impossible. 78 // constrainOperandRegClass does that for us. 79 MO.setReg(constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, I.getDesc(), 80 Reg, OpI)); 81 82 // Tie uses to defs as indicated in MCInstrDesc if this hasn't already been 83 // done. 84 if (MO.isUse()) { 85 int DefIdx = I.getDesc().getOperandConstraint(OpI, MCOI::TIED_TO); 86 if (DefIdx != -1 && !I.isRegTiedToUseOperand(DefIdx)) 87 I.tieOperands(DefIdx, OpI); 88 } 89 } 90 return true; 91 } 92 93 bool InstructionSelector::isOperandImmEqual( 94 const MachineOperand &MO, int64_t Value, 95 const MachineRegisterInfo &MRI) const { 96 if (MO.isReg() && MO.getReg()) 97 if (auto VRegVal = getConstantVRegVal(MO.getReg(), MRI)) 98 return *VRegVal == Value; 99 return false; 100 } 101 102 bool InstructionSelector::isBaseWithConstantOffset( 103 const MachineOperand &Root, const MachineRegisterInfo &MRI) const { 104 if (!Root.isReg()) 105 return false; 106 107 MachineInstr *RootI = MRI.getVRegDef(Root.getReg()); 108 if (RootI->getOpcode() != TargetOpcode::G_GEP) 109 return false; 110 111 MachineOperand &RHS = RootI->getOperand(2); 112 MachineInstr *RHSI = MRI.getVRegDef(RHS.getReg()); 113 if (RHSI->getOpcode() != TargetOpcode::G_CONSTANT) 114 return false; 115 116 return true; 117 } 118 119 bool InstructionSelector::isObviouslySafeToFold(MachineInstr &MI, 120 MachineInstr &IntoMI) const { 121 // Immediate neighbours are already folded. 122 if (MI.getParent() == IntoMI.getParent() && 123 std::next(MI.getIterator()) == IntoMI.getIterator()) 124 return true; 125 126 return !MI.mayLoadOrStore() && !MI.hasUnmodeledSideEffects() && 127 MI.implicit_operands().begin() == MI.implicit_operands().end(); 128 } 129