1 //===-- lib/CodeGen/GlobalISel/CallLowering.cpp - Call lowering -----------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 /// 10 /// \file 11 /// This file implements some simple delegations needed for call lowering. 12 /// 13 //===----------------------------------------------------------------------===// 14 15 #include "llvm/CodeGen/GlobalISel/CallLowering.h" 16 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h" 17 #include "llvm/CodeGen/MachineOperand.h" 18 #include "llvm/CodeGen/MachineRegisterInfo.h" 19 #include "llvm/CodeGen/TargetLowering.h" 20 #include "llvm/IR/DataLayout.h" 21 #include "llvm/IR/Instructions.h" 22 #include "llvm/IR/Module.h" 23 24 using namespace llvm; 25 26 void CallLowering::anchor() {} 27 28 bool CallLowering::lowerCall( 29 MachineIRBuilder &MIRBuilder, ImmutableCallSite CS, unsigned ResReg, 30 ArrayRef<unsigned> ArgRegs, std::function<unsigned()> GetCalleeReg) const { 31 auto &DL = CS.getParent()->getParent()->getParent()->getDataLayout(); 32 33 // First step is to marshall all the function's parameters into the correct 34 // physregs and memory locations. Gather the sequence of argument types that 35 // we'll pass to the assigner function. 36 SmallVector<ArgInfo, 8> OrigArgs; 37 unsigned i = 0; 38 unsigned NumFixedArgs = CS.getFunctionType()->getNumParams(); 39 for (auto &Arg : CS.args()) { 40 ArgInfo OrigArg{ArgRegs[i], Arg->getType(), ISD::ArgFlagsTy{}, 41 i < NumFixedArgs}; 42 setArgFlags(OrigArg, i + AttributeList::FirstArgIndex, DL, CS); 43 // We don't currently support swifterror or swiftself args. 44 if (OrigArg.Flags.isSwiftError() || OrigArg.Flags.isSwiftSelf()) 45 return false; 46 OrigArgs.push_back(OrigArg); 47 ++i; 48 } 49 50 MachineOperand Callee = MachineOperand::CreateImm(0); 51 if (const Function *F = CS.getCalledFunction()) 52 Callee = MachineOperand::CreateGA(F, 0); 53 else 54 Callee = MachineOperand::CreateReg(GetCalleeReg(), false); 55 56 ArgInfo OrigRet{ResReg, CS.getType(), ISD::ArgFlagsTy{}}; 57 if (!OrigRet.Ty->isVoidTy()) 58 setArgFlags(OrigRet, AttributeList::ReturnIndex, DL, CS); 59 60 return lowerCall(MIRBuilder, CS.getCallingConv(), Callee, OrigRet, OrigArgs); 61 } 62 63 template <typename FuncInfoTy> 64 void CallLowering::setArgFlags(CallLowering::ArgInfo &Arg, unsigned OpIdx, 65 const DataLayout &DL, 66 const FuncInfoTy &FuncInfo) const { 67 const AttributeList &Attrs = FuncInfo.getAttributes(); 68 if (Attrs.hasAttribute(OpIdx, Attribute::ZExt)) 69 Arg.Flags.setZExt(); 70 if (Attrs.hasAttribute(OpIdx, Attribute::SExt)) 71 Arg.Flags.setSExt(); 72 if (Attrs.hasAttribute(OpIdx, Attribute::InReg)) 73 Arg.Flags.setInReg(); 74 if (Attrs.hasAttribute(OpIdx, Attribute::StructRet)) 75 Arg.Flags.setSRet(); 76 if (Attrs.hasAttribute(OpIdx, Attribute::SwiftSelf)) 77 Arg.Flags.setSwiftSelf(); 78 if (Attrs.hasAttribute(OpIdx, Attribute::SwiftError)) 79 Arg.Flags.setSwiftError(); 80 if (Attrs.hasAttribute(OpIdx, Attribute::ByVal)) 81 Arg.Flags.setByVal(); 82 if (Attrs.hasAttribute(OpIdx, Attribute::InAlloca)) 83 Arg.Flags.setInAlloca(); 84 85 if (Arg.Flags.isByVal() || Arg.Flags.isInAlloca()) { 86 Type *ElementTy = cast<PointerType>(Arg.Ty)->getElementType(); 87 Arg.Flags.setByValSize(DL.getTypeAllocSize(ElementTy)); 88 // For ByVal, alignment should be passed from FE. BE will guess if 89 // this info is not there but there are cases it cannot get right. 90 unsigned FrameAlign; 91 if (FuncInfo.getParamAlignment(OpIdx - 2)) 92 FrameAlign = FuncInfo.getParamAlignment(OpIdx - 2); 93 else 94 FrameAlign = getTLI()->getByValTypeAlignment(ElementTy, DL); 95 Arg.Flags.setByValAlign(FrameAlign); 96 } 97 if (Attrs.hasAttribute(OpIdx, Attribute::Nest)) 98 Arg.Flags.setNest(); 99 Arg.Flags.setOrigAlign(DL.getABITypeAlignment(Arg.Ty)); 100 } 101 102 template void 103 CallLowering::setArgFlags<Function>(CallLowering::ArgInfo &Arg, unsigned OpIdx, 104 const DataLayout &DL, 105 const Function &FuncInfo) const; 106 107 template void 108 CallLowering::setArgFlags<CallInst>(CallLowering::ArgInfo &Arg, unsigned OpIdx, 109 const DataLayout &DL, 110 const CallInst &FuncInfo) const; 111 112 bool CallLowering::handleAssignments(MachineIRBuilder &MIRBuilder, 113 ArrayRef<ArgInfo> Args, 114 ValueHandler &Handler) const { 115 MachineFunction &MF = MIRBuilder.getMF(); 116 const Function &F = MF.getFunction(); 117 const DataLayout &DL = F.getParent()->getDataLayout(); 118 119 SmallVector<CCValAssign, 16> ArgLocs; 120 CCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs, F.getContext()); 121 122 unsigned NumArgs = Args.size(); 123 for (unsigned i = 0; i != NumArgs; ++i) { 124 MVT CurVT = MVT::getVT(Args[i].Ty); 125 if (Handler.assignArg(i, CurVT, CurVT, CCValAssign::Full, Args[i], CCInfo)) 126 return false; 127 } 128 129 for (unsigned i = 0, e = Args.size(), j = 0; i != e; ++i, ++j) { 130 assert(j < ArgLocs.size() && "Skipped too many arg locs"); 131 132 CCValAssign &VA = ArgLocs[j]; 133 assert(VA.getValNo() == i && "Location doesn't correspond to current arg"); 134 135 if (VA.needsCustom()) { 136 j += Handler.assignCustomValue(Args[i], makeArrayRef(ArgLocs).slice(j)); 137 continue; 138 } 139 140 if (VA.isRegLoc()) 141 Handler.assignValueToReg(Args[i].Reg, VA.getLocReg(), VA); 142 else if (VA.isMemLoc()) { 143 unsigned Size = VA.getValVT() == MVT::iPTR 144 ? DL.getPointerSize() 145 : alignTo(VA.getValVT().getSizeInBits(), 8) / 8; 146 unsigned Offset = VA.getLocMemOffset(); 147 MachinePointerInfo MPO; 148 unsigned StackAddr = Handler.getStackAddress(Size, Offset, MPO); 149 Handler.assignValueToAddress(Args[i].Reg, StackAddr, Size, MPO, VA); 150 } else { 151 // FIXME: Support byvals and other weirdness 152 return false; 153 } 154 } 155 return true; 156 } 157 158 unsigned CallLowering::ValueHandler::extendRegister(unsigned ValReg, 159 CCValAssign &VA) { 160 LLT LocTy{VA.getLocVT()}; 161 switch (VA.getLocInfo()) { 162 default: break; 163 case CCValAssign::Full: 164 case CCValAssign::BCvt: 165 // FIXME: bitconverting between vector types may or may not be a 166 // nop in big-endian situations. 167 return ValReg; 168 case CCValAssign::AExt: { 169 auto MIB = MIRBuilder.buildAnyExt(LocTy, ValReg); 170 return MIB->getOperand(0).getReg(); 171 } 172 case CCValAssign::SExt: { 173 unsigned NewReg = MRI.createGenericVirtualRegister(LocTy); 174 MIRBuilder.buildSExt(NewReg, ValReg); 175 return NewReg; 176 } 177 case CCValAssign::ZExt: { 178 unsigned NewReg = MRI.createGenericVirtualRegister(LocTy); 179 MIRBuilder.buildZExt(NewReg, ValReg); 180 return NewReg; 181 } 182 } 183 llvm_unreachable("unable to extend register"); 184 } 185 186 void CallLowering::ValueHandler::anchor() {} 187