1 //===-- lib/CodeGen/GlobalISel/CallLowering.cpp - Call lowering -----------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// 9 /// \file 10 /// This file implements some simple delegations needed for call lowering. 11 /// 12 //===----------------------------------------------------------------------===// 13 14 #include "llvm/CodeGen/Analysis.h" 15 #include "llvm/CodeGen/GlobalISel/CallLowering.h" 16 #include "llvm/CodeGen/GlobalISel/Utils.h" 17 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h" 18 #include "llvm/CodeGen/MachineOperand.h" 19 #include "llvm/CodeGen/MachineRegisterInfo.h" 20 #include "llvm/CodeGen/TargetLowering.h" 21 #include "llvm/IR/DataLayout.h" 22 #include "llvm/IR/Instructions.h" 23 #include "llvm/IR/LLVMContext.h" 24 #include "llvm/IR/Module.h" 25 #include "llvm/Target/TargetMachine.h" 26 27 #define DEBUG_TYPE "call-lowering" 28 29 using namespace llvm; 30 31 void CallLowering::anchor() {} 32 33 /// Helper function which updates \p Flags when \p AttrFn returns true. 34 static void 35 addFlagsUsingAttrFn(ISD::ArgFlagsTy &Flags, 36 const std::function<bool(Attribute::AttrKind)> &AttrFn) { 37 if (AttrFn(Attribute::SExt)) 38 Flags.setSExt(); 39 if (AttrFn(Attribute::ZExt)) 40 Flags.setZExt(); 41 if (AttrFn(Attribute::InReg)) 42 Flags.setInReg(); 43 if (AttrFn(Attribute::StructRet)) 44 Flags.setSRet(); 45 if (AttrFn(Attribute::Nest)) 46 Flags.setNest(); 47 if (AttrFn(Attribute::ByVal)) 48 Flags.setByVal(); 49 if (AttrFn(Attribute::Preallocated)) 50 Flags.setPreallocated(); 51 if (AttrFn(Attribute::InAlloca)) 52 Flags.setInAlloca(); 53 if (AttrFn(Attribute::Returned)) 54 Flags.setReturned(); 55 if (AttrFn(Attribute::SwiftSelf)) 56 Flags.setSwiftSelf(); 57 if (AttrFn(Attribute::SwiftError)) 58 Flags.setSwiftError(); 59 } 60 61 ISD::ArgFlagsTy CallLowering::getAttributesForArgIdx(const CallBase &Call, 62 unsigned ArgIdx) const { 63 ISD::ArgFlagsTy Flags; 64 addFlagsUsingAttrFn(Flags, [&Call, &ArgIdx](Attribute::AttrKind Attr) { 65 return Call.paramHasAttr(ArgIdx, Attr); 66 }); 67 return Flags; 68 } 69 70 void CallLowering::addArgFlagsFromAttributes(ISD::ArgFlagsTy &Flags, 71 const AttributeList &Attrs, 72 unsigned OpIdx) const { 73 addFlagsUsingAttrFn(Flags, [&Attrs, &OpIdx](Attribute::AttrKind Attr) { 74 return Attrs.hasAttribute(OpIdx, Attr); 75 }); 76 } 77 78 bool CallLowering::lowerCall(MachineIRBuilder &MIRBuilder, const CallBase &CB, 79 ArrayRef<Register> ResRegs, 80 ArrayRef<ArrayRef<Register>> ArgRegs, 81 Register SwiftErrorVReg, 82 std::function<unsigned()> GetCalleeReg) const { 83 CallLoweringInfo Info; 84 const DataLayout &DL = MIRBuilder.getDataLayout(); 85 MachineFunction &MF = MIRBuilder.getMF(); 86 bool CanBeTailCalled = CB.isTailCall() && 87 isInTailCallPosition(CB, MF.getTarget()) && 88 (MF.getFunction() 89 .getFnAttribute("disable-tail-calls") 90 .getValueAsString() != "true"); 91 92 // First step is to marshall all the function's parameters into the correct 93 // physregs and memory locations. Gather the sequence of argument types that 94 // we'll pass to the assigner function. 95 unsigned i = 0; 96 unsigned NumFixedArgs = CB.getFunctionType()->getNumParams(); 97 for (auto &Arg : CB.args()) { 98 ArgInfo OrigArg{ArgRegs[i], Arg->getType(), getAttributesForArgIdx(CB, i), 99 i < NumFixedArgs}; 100 setArgFlags(OrigArg, i + AttributeList::FirstArgIndex, DL, CB); 101 102 // If we have an explicit sret argument that is an Instruction, (i.e., it 103 // might point to function-local memory), we can't meaningfully tail-call. 104 if (OrigArg.Flags[0].isSRet() && isa<Instruction>(&Arg)) 105 CanBeTailCalled = false; 106 107 Info.OrigArgs.push_back(OrigArg); 108 ++i; 109 } 110 111 // Try looking through a bitcast from one function type to another. 112 // Commonly happens with calls to objc_msgSend(). 113 const Value *CalleeV = CB.getCalledOperand()->stripPointerCasts(); 114 if (const Function *F = dyn_cast<Function>(CalleeV)) 115 Info.Callee = MachineOperand::CreateGA(F, 0); 116 else 117 Info.Callee = MachineOperand::CreateReg(GetCalleeReg(), false); 118 119 Info.OrigRet = ArgInfo{ResRegs, CB.getType(), ISD::ArgFlagsTy{}}; 120 if (!Info.OrigRet.Ty->isVoidTy()) 121 setArgFlags(Info.OrigRet, AttributeList::ReturnIndex, DL, CB); 122 123 Info.KnownCallees = CB.getMetadata(LLVMContext::MD_callees); 124 Info.CallConv = CB.getCallingConv(); 125 Info.SwiftErrorVReg = SwiftErrorVReg; 126 Info.IsMustTailCall = CB.isMustTailCall(); 127 Info.IsTailCall = CanBeTailCalled; 128 Info.IsVarArg = CB.getFunctionType()->isVarArg(); 129 return lowerCall(MIRBuilder, Info); 130 } 131 132 template <typename FuncInfoTy> 133 void CallLowering::setArgFlags(CallLowering::ArgInfo &Arg, unsigned OpIdx, 134 const DataLayout &DL, 135 const FuncInfoTy &FuncInfo) const { 136 auto &Flags = Arg.Flags[0]; 137 const AttributeList &Attrs = FuncInfo.getAttributes(); 138 addArgFlagsFromAttributes(Flags, Attrs, OpIdx); 139 140 if (Flags.isByVal() || Flags.isInAlloca() || Flags.isPreallocated()) { 141 Type *ElementTy = cast<PointerType>(Arg.Ty)->getElementType(); 142 143 auto Ty = Attrs.getAttribute(OpIdx, Attribute::ByVal).getValueAsType(); 144 Flags.setByValSize(DL.getTypeAllocSize(Ty ? Ty : ElementTy)); 145 146 // For ByVal, alignment should be passed from FE. BE will guess if 147 // this info is not there but there are cases it cannot get right. 148 Align FrameAlign; 149 if (auto ParamAlign = FuncInfo.getParamAlign(OpIdx - 2)) 150 FrameAlign = *ParamAlign; 151 else 152 FrameAlign = Align(getTLI()->getByValTypeAlignment(ElementTy, DL)); 153 Flags.setByValAlign(FrameAlign); 154 } 155 Flags.setOrigAlign(DL.getABITypeAlign(Arg.Ty)); 156 } 157 158 template void 159 CallLowering::setArgFlags<Function>(CallLowering::ArgInfo &Arg, unsigned OpIdx, 160 const DataLayout &DL, 161 const Function &FuncInfo) const; 162 163 template void 164 CallLowering::setArgFlags<CallBase>(CallLowering::ArgInfo &Arg, unsigned OpIdx, 165 const DataLayout &DL, 166 const CallBase &FuncInfo) const; 167 168 Register CallLowering::packRegs(ArrayRef<Register> SrcRegs, Type *PackedTy, 169 MachineIRBuilder &MIRBuilder) const { 170 assert(SrcRegs.size() > 1 && "Nothing to pack"); 171 172 const DataLayout &DL = MIRBuilder.getMF().getDataLayout(); 173 MachineRegisterInfo *MRI = MIRBuilder.getMRI(); 174 175 LLT PackedLLT = getLLTForType(*PackedTy, DL); 176 177 SmallVector<LLT, 8> LLTs; 178 SmallVector<uint64_t, 8> Offsets; 179 computeValueLLTs(DL, *PackedTy, LLTs, &Offsets); 180 assert(LLTs.size() == SrcRegs.size() && "Regs / types mismatch"); 181 182 Register Dst = MRI->createGenericVirtualRegister(PackedLLT); 183 MIRBuilder.buildUndef(Dst); 184 for (unsigned i = 0; i < SrcRegs.size(); ++i) { 185 Register NewDst = MRI->createGenericVirtualRegister(PackedLLT); 186 MIRBuilder.buildInsert(NewDst, Dst, SrcRegs[i], Offsets[i]); 187 Dst = NewDst; 188 } 189 190 return Dst; 191 } 192 193 void CallLowering::unpackRegs(ArrayRef<Register> DstRegs, Register SrcReg, 194 Type *PackedTy, 195 MachineIRBuilder &MIRBuilder) const { 196 assert(DstRegs.size() > 1 && "Nothing to unpack"); 197 198 const DataLayout &DL = MIRBuilder.getDataLayout(); 199 200 SmallVector<LLT, 8> LLTs; 201 SmallVector<uint64_t, 8> Offsets; 202 computeValueLLTs(DL, *PackedTy, LLTs, &Offsets); 203 assert(LLTs.size() == DstRegs.size() && "Regs / types mismatch"); 204 205 for (unsigned i = 0; i < DstRegs.size(); ++i) 206 MIRBuilder.buildExtract(DstRegs[i], SrcReg, Offsets[i]); 207 } 208 209 bool CallLowering::handleAssignments(MachineIRBuilder &MIRBuilder, 210 SmallVectorImpl<ArgInfo> &Args, 211 ValueHandler &Handler) const { 212 MachineFunction &MF = MIRBuilder.getMF(); 213 const Function &F = MF.getFunction(); 214 SmallVector<CCValAssign, 16> ArgLocs; 215 CCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs, F.getContext()); 216 return handleAssignments(CCInfo, ArgLocs, MIRBuilder, Args, Handler); 217 } 218 219 bool CallLowering::handleAssignments(CCState &CCInfo, 220 SmallVectorImpl<CCValAssign> &ArgLocs, 221 MachineIRBuilder &MIRBuilder, 222 SmallVectorImpl<ArgInfo> &Args, 223 ValueHandler &Handler) const { 224 MachineFunction &MF = MIRBuilder.getMF(); 225 const Function &F = MF.getFunction(); 226 const DataLayout &DL = F.getParent()->getDataLayout(); 227 228 unsigned NumArgs = Args.size(); 229 for (unsigned i = 0; i != NumArgs; ++i) { 230 EVT CurVT = EVT::getEVT(Args[i].Ty); 231 if (CurVT.isSimple() && 232 !Handler.assignArg(i, CurVT.getSimpleVT(), CurVT.getSimpleVT(), 233 CCValAssign::Full, Args[i], Args[i].Flags[0], 234 CCInfo)) 235 continue; 236 237 MVT NewVT = TLI->getRegisterTypeForCallingConv( 238 F.getContext(), F.getCallingConv(), EVT(CurVT)); 239 240 // If we need to split the type over multiple regs, check it's a scenario 241 // we currently support. 242 unsigned NumParts = TLI->getNumRegistersForCallingConv( 243 F.getContext(), F.getCallingConv(), CurVT); 244 if (NumParts > 1) { 245 // For now only handle exact splits. 246 if (NewVT.getSizeInBits() * NumParts != CurVT.getSizeInBits()) 247 return false; 248 } 249 250 // For incoming arguments (physregs to vregs), we could have values in 251 // physregs (or memlocs) which we want to extract and copy to vregs. 252 // During this, we might have to deal with the LLT being split across 253 // multiple regs, so we have to record this information for later. 254 // 255 // If we have outgoing args, then we have the opposite case. We have a 256 // vreg with an LLT which we want to assign to a physical location, and 257 // we might have to record that the value has to be split later. 258 if (Handler.isIncomingArgumentHandler()) { 259 if (NumParts == 1) { 260 // Try to use the register type if we couldn't assign the VT. 261 if (Handler.assignArg(i, NewVT, NewVT, CCValAssign::Full, Args[i], 262 Args[i].Flags[0], CCInfo)) 263 return false; 264 } else { 265 // We're handling an incoming arg which is split over multiple regs. 266 // E.g. passing an s128 on AArch64. 267 ISD::ArgFlagsTy OrigFlags = Args[i].Flags[0]; 268 Args[i].OrigRegs.push_back(Args[i].Regs[0]); 269 Args[i].Regs.clear(); 270 Args[i].Flags.clear(); 271 LLT NewLLT = getLLTForMVT(NewVT); 272 // For each split register, create and assign a vreg that will store 273 // the incoming component of the larger value. These will later be 274 // merged to form the final vreg. 275 for (unsigned Part = 0; Part < NumParts; ++Part) { 276 Register Reg = 277 MIRBuilder.getMRI()->createGenericVirtualRegister(NewLLT); 278 ISD::ArgFlagsTy Flags = OrigFlags; 279 if (Part == 0) { 280 Flags.setSplit(); 281 } else { 282 Flags.setOrigAlign(Align(1)); 283 if (Part == NumParts - 1) 284 Flags.setSplitEnd(); 285 } 286 Args[i].Regs.push_back(Reg); 287 Args[i].Flags.push_back(Flags); 288 if (Handler.assignArg(i, NewVT, NewVT, CCValAssign::Full, 289 Args[i], Args[i].Flags[Part], CCInfo)) { 290 // Still couldn't assign this smaller part type for some reason. 291 return false; 292 } 293 } 294 } 295 } else { 296 // Handling an outgoing arg that might need to be split. 297 if (NumParts < 2) 298 return false; // Don't know how to deal with this type combination. 299 300 // This type is passed via multiple registers in the calling convention. 301 // We need to extract the individual parts. 302 Register LargeReg = Args[i].Regs[0]; 303 LLT SmallTy = LLT::scalar(NewVT.getSizeInBits()); 304 auto Unmerge = MIRBuilder.buildUnmerge(SmallTy, LargeReg); 305 assert(Unmerge->getNumOperands() == NumParts + 1); 306 ISD::ArgFlagsTy OrigFlags = Args[i].Flags[0]; 307 // We're going to replace the regs and flags with the split ones. 308 Args[i].Regs.clear(); 309 Args[i].Flags.clear(); 310 for (unsigned PartIdx = 0; PartIdx < NumParts; ++PartIdx) { 311 ISD::ArgFlagsTy Flags = OrigFlags; 312 if (PartIdx == 0) { 313 Flags.setSplit(); 314 } else { 315 Flags.setOrigAlign(Align(1)); 316 if (PartIdx == NumParts - 1) 317 Flags.setSplitEnd(); 318 } 319 Args[i].Regs.push_back(Unmerge.getReg(PartIdx)); 320 Args[i].Flags.push_back(Flags); 321 if (Handler.assignArg(i, NewVT, NewVT, CCValAssign::Full, 322 Args[i], Args[i].Flags[PartIdx], CCInfo)) 323 return false; 324 } 325 } 326 } 327 328 for (unsigned i = 0, e = Args.size(), j = 0; i != e; ++i, ++j) { 329 assert(j < ArgLocs.size() && "Skipped too many arg locs"); 330 331 CCValAssign &VA = ArgLocs[j]; 332 assert(VA.getValNo() == i && "Location doesn't correspond to current arg"); 333 334 if (VA.needsCustom()) { 335 unsigned NumArgRegs = 336 Handler.assignCustomValue(Args[i], makeArrayRef(ArgLocs).slice(j)); 337 if (!NumArgRegs) 338 return false; 339 j += NumArgRegs; 340 continue; 341 } 342 343 // FIXME: Pack registers if we have more than one. 344 Register ArgReg = Args[i].Regs[0]; 345 346 EVT OrigVT = EVT::getEVT(Args[i].Ty); 347 EVT VAVT = VA.getValVT(); 348 const LLT OrigTy = getLLTForType(*Args[i].Ty, DL); 349 350 // Expected to be multiple regs for a single incoming arg. 351 // There should be Regs.size() ArgLocs per argument. 352 unsigned NumArgRegs = Args[i].Regs.size(); 353 354 assert((j + (NumArgRegs - 1)) < ArgLocs.size() && 355 "Too many regs for number of args"); 356 for (unsigned Part = 0; Part < NumArgRegs; ++Part) { 357 // There should be Regs.size() ArgLocs per argument. 358 VA = ArgLocs[j + Part]; 359 if (VA.isMemLoc()) { 360 // Don't currently support loading/storing a type that needs to be split 361 // to the stack. Should be easy, just not implemented yet. 362 if (NumArgRegs > 1) { 363 LLVM_DEBUG( 364 dbgs() 365 << "Load/store a split arg to/from the stack not implemented yet\n"); 366 return false; 367 } 368 369 // FIXME: Use correct address space for pointer size 370 EVT LocVT = VA.getValVT(); 371 unsigned MemSize = LocVT == MVT::iPTR ? DL.getPointerSize() 372 : LocVT.getStoreSize(); 373 unsigned Offset = VA.getLocMemOffset(); 374 MachinePointerInfo MPO; 375 Register StackAddr = Handler.getStackAddress(MemSize, Offset, MPO); 376 Handler.assignValueToAddress(Args[i], StackAddr, 377 MemSize, MPO, VA); 378 continue; 379 } 380 381 assert(VA.isRegLoc() && "custom loc should have been handled already"); 382 383 // GlobalISel does not currently work for scalable vectors. 384 if (OrigVT.getFixedSizeInBits() >= VAVT.getFixedSizeInBits() || 385 !Handler.isIncomingArgumentHandler()) { 386 // This is an argument that might have been split. There should be 387 // Regs.size() ArgLocs per argument. 388 389 // Insert the argument copies. If VAVT < OrigVT, we'll insert the merge 390 // to the original register after handling all of the parts. 391 Handler.assignValueToReg(Args[i].Regs[Part], VA.getLocReg(), VA); 392 continue; 393 } 394 395 // This ArgLoc covers multiple pieces, so we need to split it. 396 const LLT VATy(VAVT.getSimpleVT()); 397 Register NewReg = 398 MIRBuilder.getMRI()->createGenericVirtualRegister(VATy); 399 Handler.assignValueToReg(NewReg, VA.getLocReg(), VA); 400 // If it's a vector type, we either need to truncate the elements 401 // or do an unmerge to get the lower block of elements. 402 if (VATy.isVector() && 403 VATy.getNumElements() > OrigVT.getVectorNumElements()) { 404 // Just handle the case where the VA type is 2 * original type. 405 if (VATy.getNumElements() != OrigVT.getVectorNumElements() * 2) { 406 LLVM_DEBUG(dbgs() 407 << "Incoming promoted vector arg has too many elts"); 408 return false; 409 } 410 auto Unmerge = MIRBuilder.buildUnmerge({OrigTy, OrigTy}, {NewReg}); 411 MIRBuilder.buildCopy(ArgReg, Unmerge.getReg(0)); 412 } else { 413 MIRBuilder.buildTrunc(ArgReg, {NewReg}).getReg(0); 414 } 415 } 416 417 // Now that all pieces have been handled, re-pack any arguments into any 418 // wider, original registers. 419 if (Handler.isIncomingArgumentHandler()) { 420 if (VAVT.getFixedSizeInBits() < OrigVT.getFixedSizeInBits()) { 421 assert(NumArgRegs >= 2); 422 423 // Merge the split registers into the expected larger result vreg 424 // of the original call. 425 MIRBuilder.buildMerge(Args[i].OrigRegs[0], Args[i].Regs); 426 } 427 } 428 429 j += NumArgRegs - 1; 430 } 431 432 return true; 433 } 434 435 bool CallLowering::analyzeArgInfo(CCState &CCState, 436 SmallVectorImpl<ArgInfo> &Args, 437 CCAssignFn &AssignFnFixed, 438 CCAssignFn &AssignFnVarArg) const { 439 for (unsigned i = 0, e = Args.size(); i < e; ++i) { 440 MVT VT = MVT::getVT(Args[i].Ty); 441 CCAssignFn &Fn = Args[i].IsFixed ? AssignFnFixed : AssignFnVarArg; 442 if (Fn(i, VT, VT, CCValAssign::Full, Args[i].Flags[0], CCState)) { 443 // Bail out on anything we can't handle. 444 LLVM_DEBUG(dbgs() << "Cannot analyze " << EVT(VT).getEVTString() 445 << " (arg number = " << i << "\n"); 446 return false; 447 } 448 } 449 return true; 450 } 451 452 bool CallLowering::resultsCompatible(CallLoweringInfo &Info, 453 MachineFunction &MF, 454 SmallVectorImpl<ArgInfo> &InArgs, 455 CCAssignFn &CalleeAssignFnFixed, 456 CCAssignFn &CalleeAssignFnVarArg, 457 CCAssignFn &CallerAssignFnFixed, 458 CCAssignFn &CallerAssignFnVarArg) const { 459 const Function &F = MF.getFunction(); 460 CallingConv::ID CalleeCC = Info.CallConv; 461 CallingConv::ID CallerCC = F.getCallingConv(); 462 463 if (CallerCC == CalleeCC) 464 return true; 465 466 SmallVector<CCValAssign, 16> ArgLocs1; 467 CCState CCInfo1(CalleeCC, false, MF, ArgLocs1, F.getContext()); 468 if (!analyzeArgInfo(CCInfo1, InArgs, CalleeAssignFnFixed, 469 CalleeAssignFnVarArg)) 470 return false; 471 472 SmallVector<CCValAssign, 16> ArgLocs2; 473 CCState CCInfo2(CallerCC, false, MF, ArgLocs2, F.getContext()); 474 if (!analyzeArgInfo(CCInfo2, InArgs, CallerAssignFnFixed, 475 CalleeAssignFnVarArg)) 476 return false; 477 478 // We need the argument locations to match up exactly. If there's more in 479 // one than the other, then we are done. 480 if (ArgLocs1.size() != ArgLocs2.size()) 481 return false; 482 483 // Make sure that each location is passed in exactly the same way. 484 for (unsigned i = 0, e = ArgLocs1.size(); i < e; ++i) { 485 const CCValAssign &Loc1 = ArgLocs1[i]; 486 const CCValAssign &Loc2 = ArgLocs2[i]; 487 488 // We need both of them to be the same. So if one is a register and one 489 // isn't, we're done. 490 if (Loc1.isRegLoc() != Loc2.isRegLoc()) 491 return false; 492 493 if (Loc1.isRegLoc()) { 494 // If they don't have the same register location, we're done. 495 if (Loc1.getLocReg() != Loc2.getLocReg()) 496 return false; 497 498 // They matched, so we can move to the next ArgLoc. 499 continue; 500 } 501 502 // Loc1 wasn't a RegLoc, so they both must be MemLocs. Check if they match. 503 if (Loc1.getLocMemOffset() != Loc2.getLocMemOffset()) 504 return false; 505 } 506 507 return true; 508 } 509 510 Register CallLowering::ValueHandler::extendRegister(Register ValReg, 511 CCValAssign &VA, 512 unsigned MaxSizeBits) { 513 LLT LocTy{VA.getLocVT()}; 514 LLT ValTy = MRI.getType(ValReg); 515 if (LocTy.getSizeInBits() == ValTy.getSizeInBits()) 516 return ValReg; 517 518 if (LocTy.isScalar() && MaxSizeBits && MaxSizeBits < LocTy.getSizeInBits()) { 519 if (MaxSizeBits <= ValTy.getSizeInBits()) 520 return ValReg; 521 LocTy = LLT::scalar(MaxSizeBits); 522 } 523 524 switch (VA.getLocInfo()) { 525 default: break; 526 case CCValAssign::Full: 527 case CCValAssign::BCvt: 528 // FIXME: bitconverting between vector types may or may not be a 529 // nop in big-endian situations. 530 return ValReg; 531 case CCValAssign::AExt: { 532 auto MIB = MIRBuilder.buildAnyExt(LocTy, ValReg); 533 return MIB.getReg(0); 534 } 535 case CCValAssign::SExt: { 536 Register NewReg = MRI.createGenericVirtualRegister(LocTy); 537 MIRBuilder.buildSExt(NewReg, ValReg); 538 return NewReg; 539 } 540 case CCValAssign::ZExt: { 541 Register NewReg = MRI.createGenericVirtualRegister(LocTy); 542 MIRBuilder.buildZExt(NewReg, ValReg); 543 return NewReg; 544 } 545 } 546 llvm_unreachable("unable to extend register"); 547 } 548 549 void CallLowering::ValueHandler::anchor() {} 550