1 //===-- lib/CodeGen/GlobalISel/CallLowering.cpp - Call lowering -----------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 /// 10 /// \file 11 /// This file implements some simple delegations needed for call lowering. 12 /// 13 //===----------------------------------------------------------------------===// 14 15 #include "llvm/CodeGen/GlobalISel/CallLowering.h" 16 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h" 17 #include "llvm/CodeGen/MachineOperand.h" 18 #include "llvm/CodeGen/MachineRegisterInfo.h" 19 #include "llvm/IR/DataLayout.h" 20 #include "llvm/IR/Instructions.h" 21 #include "llvm/IR/Module.h" 22 #include "llvm/Target/TargetLowering.h" 23 24 using namespace llvm; 25 26 template<typename CallInstTy> 27 bool CallLowering::lowerCall( 28 MachineIRBuilder &MIRBuilder, const CallInstTy &CI, unsigned ResReg, 29 ArrayRef<unsigned> ArgRegs, std::function<unsigned()> GetCalleeReg) const { 30 auto &DL = CI.getParent()->getParent()->getParent()->getDataLayout(); 31 32 // First step is to marshall all the function's parameters into the correct 33 // physregs and memory locations. Gather the sequence of argument types that 34 // we'll pass to the assigner function. 35 SmallVector<ArgInfo, 8> OrigArgs; 36 unsigned i = 0; 37 unsigned NumFixedArgs = CI.getFunctionType()->getNumParams(); 38 for (auto &Arg : CI.arg_operands()) { 39 ArgInfo OrigArg{ArgRegs[i], Arg->getType(), ISD::ArgFlagsTy{}, 40 i < NumFixedArgs}; 41 setArgFlags(OrigArg, i + 1, DL, CI); 42 OrigArgs.push_back(OrigArg); 43 ++i; 44 } 45 46 MachineOperand Callee = MachineOperand::CreateImm(0); 47 if (Function *F = CI.getCalledFunction()) 48 Callee = MachineOperand::CreateGA(F, 0); 49 else 50 Callee = MachineOperand::CreateReg(GetCalleeReg(), false); 51 52 ArgInfo OrigRet{ResReg, CI.getType(), ISD::ArgFlagsTy{}}; 53 if (!OrigRet.Ty->isVoidTy()) 54 setArgFlags(OrigRet, AttributeSet::ReturnIndex, DL, CI); 55 56 return lowerCall(MIRBuilder, Callee, OrigRet, OrigArgs); 57 } 58 59 template bool 60 CallLowering::lowerCall(MachineIRBuilder &MIRBuilder, const CallInst &CI, 61 unsigned ResReg, ArrayRef<unsigned> ArgRegs, 62 std::function<unsigned()> GetCalleeReg) const; 63 64 template bool 65 CallLowering::lowerCall(MachineIRBuilder &MIRBuilder, const InvokeInst &CI, 66 unsigned ResReg, ArrayRef<unsigned> ArgRegs, 67 std::function<unsigned()> GetCalleeReg) const; 68 69 template <typename FuncInfoTy> 70 void CallLowering::setArgFlags(CallLowering::ArgInfo &Arg, unsigned OpIdx, 71 const DataLayout &DL, 72 const FuncInfoTy &FuncInfo) const { 73 const AttributeSet &Attrs = FuncInfo.getAttributes(); 74 if (Attrs.hasAttribute(OpIdx, Attribute::ZExt)) 75 Arg.Flags.setZExt(); 76 if (Attrs.hasAttribute(OpIdx, Attribute::SExt)) 77 Arg.Flags.setSExt(); 78 if (Attrs.hasAttribute(OpIdx, Attribute::InReg)) 79 Arg.Flags.setInReg(); 80 if (Attrs.hasAttribute(OpIdx, Attribute::StructRet)) 81 Arg.Flags.setSRet(); 82 if (Attrs.hasAttribute(OpIdx, Attribute::SwiftSelf)) 83 Arg.Flags.setSwiftSelf(); 84 if (Attrs.hasAttribute(OpIdx, Attribute::SwiftError)) 85 Arg.Flags.setSwiftError(); 86 if (Attrs.hasAttribute(OpIdx, Attribute::ByVal)) 87 Arg.Flags.setByVal(); 88 if (Attrs.hasAttribute(OpIdx, Attribute::InAlloca)) 89 Arg.Flags.setInAlloca(); 90 91 if (Arg.Flags.isByVal() || Arg.Flags.isInAlloca()) { 92 Type *ElementTy = cast<PointerType>(Arg.Ty)->getElementType(); 93 Arg.Flags.setByValSize(DL.getTypeAllocSize(ElementTy)); 94 // For ByVal, alignment should be passed from FE. BE will guess if 95 // this info is not there but there are cases it cannot get right. 96 unsigned FrameAlign; 97 if (FuncInfo.getParamAlignment(OpIdx)) 98 FrameAlign = FuncInfo.getParamAlignment(OpIdx); 99 else 100 FrameAlign = getTLI()->getByValTypeAlignment(ElementTy, DL); 101 Arg.Flags.setByValAlign(FrameAlign); 102 } 103 if (Attrs.hasAttribute(OpIdx, Attribute::Nest)) 104 Arg.Flags.setNest(); 105 Arg.Flags.setOrigAlign(DL.getABITypeAlignment(Arg.Ty)); 106 } 107 108 template void 109 CallLowering::setArgFlags<Function>(CallLowering::ArgInfo &Arg, unsigned OpIdx, 110 const DataLayout &DL, 111 const Function &FuncInfo) const; 112 113 template void 114 CallLowering::setArgFlags<CallInst>(CallLowering::ArgInfo &Arg, unsigned OpIdx, 115 const DataLayout &DL, 116 const CallInst &FuncInfo) const; 117 118 bool CallLowering::handleAssignments(MachineIRBuilder &MIRBuilder, 119 ArrayRef<ArgInfo> Args, 120 ValueHandler &Handler) const { 121 MachineFunction &MF = MIRBuilder.getMF(); 122 const Function &F = *MF.getFunction(); 123 const DataLayout &DL = F.getParent()->getDataLayout(); 124 125 SmallVector<CCValAssign, 16> ArgLocs; 126 CCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs, F.getContext()); 127 128 unsigned NumArgs = Args.size(); 129 for (unsigned i = 0; i != NumArgs; ++i) { 130 MVT CurVT = MVT::getVT(Args[i].Ty); 131 if (Handler.assignArg(i, CurVT, CurVT, CCValAssign::Full, Args[i], CCInfo)) 132 return false; 133 } 134 135 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 136 CCValAssign &VA = ArgLocs[i]; 137 138 if (VA.isRegLoc()) 139 Handler.assignValueToReg(Args[i].Reg, VA.getLocReg(), VA); 140 else if (VA.isMemLoc()) { 141 unsigned Size = VA.getValVT() == MVT::iPTR 142 ? DL.getPointerSize() 143 : alignTo(VA.getValVT().getSizeInBits(), 8) / 8; 144 unsigned Offset = VA.getLocMemOffset(); 145 MachinePointerInfo MPO; 146 unsigned StackAddr = Handler.getStackAddress(Size, Offset, MPO); 147 Handler.assignValueToAddress(Args[i].Reg, StackAddr, Size, MPO, VA); 148 } else { 149 // FIXME: Support byvals and other weirdness 150 return false; 151 } 152 } 153 return true; 154 } 155 156 unsigned CallLowering::ValueHandler::extendRegister(unsigned ValReg, 157 CCValAssign &VA) { 158 LLT LocTy{VA.getLocVT()}; 159 switch (VA.getLocInfo()) { 160 default: break; 161 case CCValAssign::Full: 162 case CCValAssign::BCvt: 163 // FIXME: bitconverting between vector types may or may not be a 164 // nop in big-endian situations. 165 return ValReg; 166 case CCValAssign::AExt: 167 assert(!VA.getLocVT().isVector() && "unexpected vector extend"); 168 // Otherwise, it's a nop. 169 return ValReg; 170 case CCValAssign::SExt: { 171 unsigned NewReg = MRI.createGenericVirtualRegister(LocTy); 172 MIRBuilder.buildSExt(NewReg, ValReg); 173 return NewReg; 174 } 175 case CCValAssign::ZExt: { 176 unsigned NewReg = MRI.createGenericVirtualRegister(LocTy); 177 MIRBuilder.buildZExt(NewReg, ValReg); 178 return NewReg; 179 } 180 } 181 llvm_unreachable("unable to extend register"); 182 } 183