xref: /llvm-project/lldb/test/API/functionalities/gdb_remote_client/TestTargetXMLArch.py (revision c4cdf865698eae06affbf762baf38e6ca95b4785)
1from __future__ import print_function
2import lldb
3from lldbsuite.test.lldbtest import *
4from lldbsuite.test.decorators import *
5from lldbsuite.test.gdbclientutils import *
6from lldbsuite.test.lldbgdbclient import GDBRemoteTestBase
7
8class MyResponder(MockGDBServerResponder):
9    def qXferRead(self, obj, annex, offset, length):
10        if annex == "target.xml":
11            return """<?xml version="1.0"?>
12                <target version="1.0">
13                  <architecture>i386:x86-64</architecture>
14                  <feature name="org.gnu.gdb.i386.core">
15
16                 <flags id="i386_eflags" size="4">
17                 <field name="CF" start="0" end="0"/>
18                 <field name="" start="1" end="1"/>
19                 <field name="PF" start="2" end="2"/>
20                 <field name="AF" start="4" end="4"/>
21                 <field name="ZF" start="6" end="6"/>
22                 <field name="SF" start="7" end="7"/>
23                 <field name="TF" start="8" end="8"/>
24                 <field name="IF" start="9" end="9"/>
25                 <field name="DF" start="10" end="10"/>
26                 <field name="OF" start="11" end="11"/>
27                 <field name="NT" start="14" end="14"/>
28                 <field name="RF" start="16" end="16"/>
29                 <field name="VM" start="17" end="17"/>
30                 <field name="AC" start="18" end="18"/>
31                 <field name="VIF" start="19" end="19"/>
32                 <field name="VIP" start="20" end="20"/>
33                 <field name="ID" start="21" end="21"/>
34                 </flags>
35
36                    <reg name="rax" bitsize="64" regnum="0" type="int" group="general"/>
37                    <reg name="rbx" bitsize="64" regnum="1" type="int" group="general"/>
38                    <reg name="rcx" bitsize="64" regnum="2" type="int" group="general"/>
39                    <reg name="rdx" bitsize="64" regnum="3" type="int" group="general"/>
40                    <reg name="rsi" bitsize="64" regnum="4" type="int" group="general"/>
41                    <reg name="rdi" bitsize="64" regnum="5" type="int" group="general"/>
42                    <reg name="rbp" bitsize="64" regnum="6" type="data_ptr" group="general"/>
43                    <reg name="rsp" bitsize="64" regnum="7" type="data_ptr" group="general"/>
44                    <reg name="r8" bitsize="64"  regnum="8" type="int" group="general"/>
45                    <reg name="r9" bitsize="64"  regnum="9" type="int" group="general"/>
46                    <reg name="r10" bitsize="64" regnum="10" type="int" group="general"/>
47                    <reg name="r11" bitsize="64" regnum="11" type="int" group="general"/>
48                    <reg name="r12" bitsize="64" regnum="12" type="int" group="general"/>
49                    <reg name="r13" bitsize="64" regnum="13" type="int" group="general"/>
50                    <reg name="r14" bitsize="64" regnum="14" type="int" group="general"/>
51                    <reg name="r15" bitsize="64" regnum="15" type="int" group="general"/>
52                    <reg name="rip" bitsize="64" regnum="16" type="code_ptr" group="general"/>
53                    <reg name="eflags" bitsize="32" regnum="17" type="i386_eflags" group="general"/>
54
55                    <reg name="cs" bitsize="32" regnum="18" type="int" group="general"/>
56                    <reg name="ss" bitsize="32" regnum="19" type="int" group="general"/>
57                    <reg name="ds" bitsize="32" regnum="20" type="int" group="general"/>
58                    <reg name="es" bitsize="32" regnum="21" type="int" group="general"/>
59                    <reg name="fs" bitsize="32" regnum="22" type="int" group="general"/>
60                    <reg name="gs" bitsize="32" regnum="23" type="int" group="general"/>
61
62                    <reg name="st0" bitsize="80" regnum="24" type="i387_ext" group="float"/>
63                    <reg name="st1" bitsize="80" regnum="25" type="i387_ext" group="float"/>
64                    <reg name="st2" bitsize="80" regnum="26" type="i387_ext" group="float"/>
65                    <reg name="st3" bitsize="80" regnum="27" type="i387_ext" group="float"/>
66                    <reg name="st4" bitsize="80" regnum="28" type="i387_ext" group="float"/>
67                    <reg name="st5" bitsize="80" regnum="29" type="i387_ext" group="float"/>
68                    <reg name="st6" bitsize="80" regnum="30" type="i387_ext" group="float"/>
69                    <reg name="st7" bitsize="80" regnum="31" type="i387_ext" group="float"/>
70
71                    <reg name="fctrl" bitsize="32" regnum="32" type="int" group="float"/>
72                    <reg name="fstat" bitsize="32" regnum="33" type="int" group="float"/>
73                    <reg name="ftag"  bitsize="32" regnum="34" type="int" group="float"/>
74                    <reg name="fiseg" bitsize="32" regnum="35" type="int" group="float"/>
75                    <reg name="fioff" bitsize="32" regnum="36" type="int" group="float"/>
76                    <reg name="foseg" bitsize="32" regnum="37" type="int" group="float"/>
77                    <reg name="fooff" bitsize="32" regnum="38" type="int" group="float"/>
78                    <reg name="fop"   bitsize="32" regnum="39" type="int" group="float"/>
79                  </feature>
80                </target>""", False
81        else:
82            return None, False
83
84    def qC(self):
85        return "QC1"
86
87    def haltReason(self):
88        return "T05thread:00000001;06:9038d60f00700000;07:98b4062680ffffff;10:c0d7bf1b80ffffff;"
89
90    def readRegister(self, register):
91        regs = {0x0: "00b0060000610000",
92                0xa: "68fe471c80ffffff",
93                0xc: "60574a1c80ffffff",
94                0xd: "18f3042680ffffff",
95                0xe: "be8a4d7142000000",
96                0xf: "50df471c80ffffff",
97                0x10: "c0d7bf1b80ffffff" }
98        if register in regs:
99            return regs[register]
100        else:
101            return "0000000000000000"
102
103class TestTargetXMLArch(GDBRemoteTestBase):
104
105    mydir = TestBase.compute_mydir(__file__)
106
107    @skipIfXmlSupportMissing
108    @expectedFailureAll(archs=["i386"])
109    @skipIfRemote
110    def test(self):
111        """
112        Test lldb's parsing of the <architecture> tag in the target.xml register
113        description packet.
114        """
115        self.server.responder = MyResponder()
116        interp = self.dbg.GetCommandInterpreter()
117        result = lldb.SBCommandReturnObject()
118        if self.TraceOn():
119            self.runCmd("log enable gdb-remote packets")
120            self.addTearDownHook(
121                    lambda: self.runCmd("log disable gdb-remote packets"))
122
123        target = self.dbg.CreateTarget('')
124        self.assertEqual('', target.GetTriple())
125        process = self.connect(target)
126        if self.TraceOn():
127            interp.HandleCommand("target list", result)
128            print(result.GetOutput())
129        self.assertTrue(target.GetTriple().startswith('x86_64-unknown-unknown'))
130
131    @skipIfXmlSupportMissing
132    @skipIfRemote
133    @skipIfLLVMTargetMissing("X86")
134    def test_register_augmentation(self):
135        """
136        Test that we correctly associate the register info with the eh_frame
137        register numbers.
138        """
139
140        target = self.createTarget("basic_eh_frame.yaml")
141        self.server.responder = MyResponder()
142
143        process = self.connect(target)
144        lldbutil.expect_state_changes(self, self.dbg.GetListener(), process,
145                [lldb.eStateStopped])
146        self.filecheck("image show-unwind -n foo", __file__,
147            "--check-prefix=UNWIND")
148# UNWIND: eh_frame UnwindPlan:
149# UNWIND: row[0]:    0: CFA=rsp+128 => rip=[CFA-8]
150