1from __future__ import print_function 2import lldb 3from lldbsuite.test.lldbtest import * 4from lldbsuite.test.decorators import * 5from gdbclientutils import * 6 7 8class TestGDBServerTargetXML(GDBRemoteTestBase): 9 @skipIfXmlSupportMissing 10 @skipIfRemote 11 @skipIfLLVMTargetMissing("X86") 12 def test_x86_64_regs(self): 13 """Test grabbing various x86_64 registers from gdbserver.""" 14 class MyResponder(MockGDBServerResponder): 15 reg_data = ( 16 "0102030405060708" # rcx 17 "1112131415161718" # rdx 18 "2122232425262728" # rsi 19 "3132333435363738" # rdi 20 "4142434445464748" # rbp 21 "5152535455565758" # rsp 22 "6162636465666768" # r8 23 "7172737475767778" # r9 24 "8182838485868788" # rip 25 "91929394" # eflags 26 "0102030405060708090a" # st0 27 "1112131415161718191a" # st1 28 ) + 6 * ( 29 "2122232425262728292a" # st2..st7 30 ) + ( 31 "8182838485868788898a8b8c8d8e8f90" # xmm0 32 "9192939495969798999a9b9c9d9e9fa0" # xmm1 33 ) + 14 * ( 34 "a1a2a3a4a5a6a7a8a9aaabacadaeafb0" # xmm2..xmm15 35 ) + ( 36 "00000000" # mxcsr 37 ) + ( 38 "b1b2b3b4b5b6b7b8b9babbbcbdbebfc0" # ymm0h 39 "c1c2c3c4c5c6c7c8c9cacbcccdcecfd0" # ymm1h 40 ) + 14 * ( 41 "d1d2d3d4d5d6d7d8d9dadbdcdddedfe0" # ymm2h..ymm15h 42 ) 43 44 def qXferRead(self, obj, annex, offset, length): 45 if annex == "target.xml": 46 return """<?xml version="1.0"?> 47 <!DOCTYPE feature SYSTEM "gdb-target.dtd"> 48 <target> 49 <architecture>i386:x86-64</architecture> 50 <osabi>GNU/Linux</osabi> 51 <feature name="org.gnu.gdb.i386.core"> 52 <reg name="rcx" bitsize="64" type="int64" regnum="2"/> 53 <reg name="rdx" bitsize="64" type="int64" regnum="3"/> 54 <reg name="rsi" bitsize="64" type="int64" regnum="4"/> 55 <reg name="rdi" bitsize="64" type="int64" regnum="5"/> 56 <reg name="rbp" bitsize="64" type="data_ptr" regnum="6"/> 57 <reg name="rsp" bitsize="64" type="data_ptr" regnum="7"/> 58 <reg name="r8" bitsize="64" type="int64" regnum="8"/> 59 <reg name="r9" bitsize="64" type="int64" regnum="9"/> 60 <reg name="rip" bitsize="64" type="code_ptr" regnum="16"/> 61 <reg name="eflags" bitsize="32" type="i386_eflags" regnum="17"/> 62 <reg name="st0" bitsize="80" type="i387_ext" regnum="24"/> 63 <reg name="st1" bitsize="80" type="i387_ext" regnum="25"/> 64 <reg name="st2" bitsize="80" type="i387_ext" regnum="26"/> 65 <reg name="st3" bitsize="80" type="i387_ext" regnum="27"/> 66 <reg name="st4" bitsize="80" type="i387_ext" regnum="28"/> 67 <reg name="st5" bitsize="80" type="i387_ext" regnum="29"/> 68 <reg name="st6" bitsize="80" type="i387_ext" regnum="30"/> 69 <reg name="st7" bitsize="80" type="i387_ext" regnum="31"/> 70 </feature> 71 <feature name="org.gnu.gdb.i386.sse"> 72 <reg name="xmm0" bitsize="128" type="vec128" regnum="40"/> 73 <reg name="xmm1" bitsize="128" type="vec128" regnum="41"/> 74 <reg name="xmm2" bitsize="128" type="vec128" regnum="42"/> 75 <reg name="xmm3" bitsize="128" type="vec128" regnum="43"/> 76 <reg name="xmm4" bitsize="128" type="vec128" regnum="44"/> 77 <reg name="xmm5" bitsize="128" type="vec128" regnum="45"/> 78 <reg name="xmm6" bitsize="128" type="vec128" regnum="46"/> 79 <reg name="xmm7" bitsize="128" type="vec128" regnum="47"/> 80 <reg name="xmm8" bitsize="128" type="vec128" regnum="48"/> 81 <reg name="xmm9" bitsize="128" type="vec128" regnum="49"/> 82 <reg name="xmm10" bitsize="128" type="vec128" regnum="50"/> 83 <reg name="xmm11" bitsize="128" type="vec128" regnum="51"/> 84 <reg name="xmm12" bitsize="128" type="vec128" regnum="52"/> 85 <reg name="xmm13" bitsize="128" type="vec128" regnum="53"/> 86 <reg name="xmm14" bitsize="128" type="vec128" regnum="54"/> 87 <reg name="xmm15" bitsize="128" type="vec128" regnum="55"/> 88 <reg name="mxcsr" bitsize="32" type="i386_mxcsr" regnum="56" group="vector"/> 89 </feature> 90 <feature name="org.gnu.gdb.i386.avx"> 91 <reg name="ymm0h" bitsize="128" type="uint128" regnum="60"/> 92 <reg name="ymm1h" bitsize="128" type="uint128" regnum="61"/> 93 <reg name="ymm2h" bitsize="128" type="uint128" regnum="62"/> 94 <reg name="ymm3h" bitsize="128" type="uint128" regnum="63"/> 95 <reg name="ymm4h" bitsize="128" type="uint128" regnum="64"/> 96 <reg name="ymm5h" bitsize="128" type="uint128" regnum="65"/> 97 <reg name="ymm6h" bitsize="128" type="uint128" regnum="66"/> 98 <reg name="ymm7h" bitsize="128" type="uint128" regnum="67"/> 99 <reg name="ymm8h" bitsize="128" type="uint128" regnum="68"/> 100 <reg name="ymm9h" bitsize="128" type="uint128" regnum="69"/> 101 <reg name="ymm10h" bitsize="128" type="uint128" regnum="70"/> 102 <reg name="ymm11h" bitsize="128" type="uint128" regnum="71"/> 103 <reg name="ymm12h" bitsize="128" type="uint128" regnum="72"/> 104 <reg name="ymm13h" bitsize="128" type="uint128" regnum="73"/> 105 <reg name="ymm14h" bitsize="128" type="uint128" regnum="74"/> 106 <reg name="ymm15h" bitsize="128" type="uint128" regnum="75"/> 107 </feature> 108 </target>""", False 109 else: 110 return None, False 111 112 def readRegister(self, regnum): 113 return "" 114 115 def readRegisters(self): 116 return self.reg_data 117 118 def writeRegisters(self, reg_hex): 119 self.reg_data = reg_hex 120 return "OK" 121 122 def haltReason(self): 123 return "T02thread:1ff0d;threads:1ff0d;thread-pcs:000000010001bc00;07:0102030405060708;10:1112131415161718;" 124 125 self.server.responder = MyResponder() 126 127 target = self.createTarget("basic_eh_frame.yaml") 128 process = self.connect(target) 129 lldbutil.expect_state_changes(self, self.dbg.GetListener(), process, 130 [lldb.eStateStopped]) 131 132 # test generic aliases 133 self.match("register read arg4", 134 ["rcx = 0x0807060504030201"]) 135 self.match("register read arg3", 136 ["rdx = 0x1817161514131211"]) 137 self.match("register read arg2", 138 ["rsi = 0x2827262524232221"]) 139 self.match("register read arg1", 140 ["rdi = 0x3837363534333231"]) 141 self.match("register read fp", 142 ["rbp = 0x4847464544434241"]) 143 self.match("register read sp", 144 ["rsp = 0x5857565554535251"]) 145 self.match("register read arg5", 146 ["r8 = 0x6867666564636261"]) 147 self.match("register read arg6", 148 ["r9 = 0x7877767574737271"]) 149 self.match("register read pc", 150 ["rip = 0x8887868584838281"]) 151 self.match("register read flags", 152 ["eflags = 0x94939291"]) 153 154 # both stX and xmmX should be displayed as vectors 155 self.match("register read st0", 156 ["st0 = {0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a}"]) 157 self.match("register read st1", 158 ["st1 = {0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a}"]) 159 self.match("register read xmm0", 160 ["xmm0 = {0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 " 161 "0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90}"]) 162 self.match("register read xmm1", 163 ["xmm1 = {0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 " 164 "0x99 0x9a 0x9b 0x9c 0x9d 0x9e 0x9f 0xa0}"]) 165 166 # test pseudo-registers 167 self.filecheck("register read --all", 168 os.path.join(os.path.dirname(__file__), 169 "amd64-partial-regs.FileCheck")) 170 171 # test writing into pseudo-registers 172 self.runCmd("register write ecx 0xfffefdfc") 173 self.match("register read rcx", 174 ["rcx = 0x08070605fffefdfc"]) 175 176 self.runCmd("register write cx 0xfbfa") 177 self.match("register read ecx", 178 ["ecx = 0xfffefbfa"]) 179 self.match("register read rcx", 180 ["rcx = 0x08070605fffefbfa"]) 181 182 self.runCmd("register write ch 0xf9") 183 self.match("register read cx", 184 ["cx = 0xf9fa"]) 185 self.match("register read ecx", 186 ["ecx = 0xfffef9fa"]) 187 self.match("register read rcx", 188 ["rcx = 0x08070605fffef9fa"]) 189 190 self.runCmd("register write cl 0xf8") 191 self.match("register read cx", 192 ["cx = 0xf9f8"]) 193 self.match("register read ecx", 194 ["ecx = 0xfffef9f8"]) 195 self.match("register read rcx", 196 ["rcx = 0x08070605fffef9f8"]) 197 198 self.runCmd("register write mm0 0xfffefdfcfbfaf9f8") 199 self.match("register read st0", 200 ["st0 = {0xf8 0xf9 0xfa 0xfb 0xfc 0xfd 0xfe 0xff 0x09 0x0a}"]) 201 202 @skipIfXmlSupportMissing 203 @skipIfRemote 204 @skipIfLLVMTargetMissing("X86") 205 def test_i386_regs(self): 206 """Test grabbing various i386 registers from gdbserver.""" 207 class MyResponder(MockGDBServerResponder): 208 reg_data = ( 209 "01020304" # eax 210 "11121314" # ecx 211 "21222324" # edx 212 "31323334" # ebx 213 "41424344" # esp 214 "51525354" # ebp 215 "61626364" # esi 216 "71727374" # edi 217 "81828384" # eip 218 "91929394" # eflags 219 "0102030405060708090a" # st0 220 "1112131415161718191a" # st1 221 ) + 6 * ( 222 "2122232425262728292a" # st2..st7 223 ) + ( 224 "8182838485868788898a8b8c8d8e8f90" # xmm0 225 "9192939495969798999a9b9c9d9e9fa0" # xmm1 226 ) + 6 * ( 227 "a1a2a3a4a5a6a7a8a9aaabacadaeafb0" # xmm2..xmm7 228 ) + ( 229 "00000000" # mxcsr 230 ) + ( 231 "b1b2b3b4b5b6b7b8b9babbbcbdbebfc0" # ymm0h 232 "c1c2c3c4c5c6c7c8c9cacbcccdcecfd0" # ymm1h 233 ) + 6 * ( 234 "d1d2d3d4d5d6d7d8d9dadbdcdddedfe0" # ymm2h..ymm7h 235 ) 236 237 def qXferRead(self, obj, annex, offset, length): 238 if annex == "target.xml": 239 return """<?xml version="1.0"?> 240 <!DOCTYPE feature SYSTEM "gdb-target.dtd"> 241 <target> 242 <architecture>i386</architecture> 243 <osabi>GNU/Linux</osabi> 244 <feature name="org.gnu.gdb.i386.core"> 245 <reg name="eax" bitsize="32" type="int32" regnum="0"/> 246 <reg name="ecx" bitsize="32" type="int32" regnum="1"/> 247 <reg name="edx" bitsize="32" type="int32" regnum="2"/> 248 <reg name="ebx" bitsize="32" type="int32" regnum="3"/> 249 <reg name="esp" bitsize="32" type="data_ptr" regnum="4"/> 250 <reg name="ebp" bitsize="32" type="data_ptr" regnum="5"/> 251 <reg name="esi" bitsize="32" type="int32" regnum="6"/> 252 <reg name="edi" bitsize="32" type="int32" regnum="7"/> 253 <reg name="eip" bitsize="32" type="code_ptr" regnum="8"/> 254 <reg name="eflags" bitsize="32" type="i386_eflags" regnum="9"/> 255 <reg name="st0" bitsize="80" type="i387_ext" regnum="16"/> 256 <reg name="st1" bitsize="80" type="i387_ext" regnum="17"/> 257 <reg name="st2" bitsize="80" type="i387_ext" regnum="18"/> 258 <reg name="st3" bitsize="80" type="i387_ext" regnum="19"/> 259 <reg name="st4" bitsize="80" type="i387_ext" regnum="20"/> 260 <reg name="st5" bitsize="80" type="i387_ext" regnum="21"/> 261 <reg name="st6" bitsize="80" type="i387_ext" regnum="22"/> 262 <reg name="st7" bitsize="80" type="i387_ext" regnum="23"/> 263 </feature> 264 <feature name="org.gnu.gdb.i386.sse"> 265 <reg name="xmm0" bitsize="128" type="vec128" regnum="32"/> 266 <reg name="xmm1" bitsize="128" type="vec128" regnum="33"/> 267 <reg name="xmm2" bitsize="128" type="vec128" regnum="34"/> 268 <reg name="xmm3" bitsize="128" type="vec128" regnum="35"/> 269 <reg name="xmm4" bitsize="128" type="vec128" regnum="36"/> 270 <reg name="xmm5" bitsize="128" type="vec128" regnum="37"/> 271 <reg name="xmm6" bitsize="128" type="vec128" regnum="38"/> 272 <reg name="xmm7" bitsize="128" type="vec128" regnum="39"/> 273 <reg name="mxcsr" bitsize="32" type="i386_mxcsr" regnum="40" group="vector"/> 274 </feature> 275 <feature name="org.gnu.gdb.i386.avx"> 276 <reg name="ymm0h" bitsize="128" type="uint128" regnum="42"/> 277 <reg name="ymm1h" bitsize="128" type="uint128" regnum="43"/> 278 <reg name="ymm2h" bitsize="128" type="uint128" regnum="44"/> 279 <reg name="ymm3h" bitsize="128" type="uint128" regnum="45"/> 280 <reg name="ymm4h" bitsize="128" type="uint128" regnum="46"/> 281 <reg name="ymm5h" bitsize="128" type="uint128" regnum="47"/> 282 <reg name="ymm6h" bitsize="128" type="uint128" regnum="48"/> 283 <reg name="ymm7h" bitsize="128" type="uint128" regnum="49"/> 284 </feature> 285 </target>""", False 286 else: 287 return None, False 288 289 def readRegister(self, regnum): 290 return "" 291 292 def readRegisters(self): 293 return self.reg_data 294 295 def writeRegisters(self, reg_hex): 296 self.reg_data = reg_hex 297 return "OK" 298 299 def haltReason(self): 300 return "T02thread:1ff0d;threads:1ff0d;thread-pcs:000000010001bc00;07:0102030405060708;10:1112131415161718;" 301 302 self.server.responder = MyResponder() 303 304 target = self.createTarget("basic_eh_frame-i386.yaml") 305 process = self.connect(target) 306 lldbutil.expect_state_changes(self, self.dbg.GetListener(), process, 307 [lldb.eStateStopped]) 308 309 # test generic aliases 310 self.match("register read fp", 311 ["ebp = 0x54535251"]) 312 self.match("register read sp", 313 ["esp = 0x44434241"]) 314 self.match("register read pc", 315 ["eip = 0x84838281"]) 316 self.match("register read flags", 317 ["eflags = 0x94939291"]) 318 319 # test pseudo-registers 320 self.match("register read cx", 321 ["cx = 0x1211"]) 322 self.match("register read ch", 323 ["ch = 0x12"]) 324 self.match("register read cl", 325 ["cl = 0x11"]) 326 self.match("register read mm0", 327 ["mm0 = 0x0807060504030201"]) 328 self.match("register read mm1", 329 ["mm1 = 0x1817161514131211"]) 330 331 # both stX and xmmX should be displayed as vectors 332 self.match("register read st0", 333 ["st0 = {0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a}"]) 334 self.match("register read st1", 335 ["st1 = {0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a}"]) 336 self.match("register read xmm0", 337 ["xmm0 = {0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 " 338 "0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90}"]) 339 self.match("register read xmm1", 340 ["xmm1 = {0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 " 341 "0x99 0x9a 0x9b 0x9c 0x9d 0x9e 0x9f 0xa0}"]) 342 343 # test writing into pseudo-registers 344 self.runCmd("register write cx 0xfbfa") 345 self.match("register read ecx", 346 ["ecx = 0x1413fbfa"]) 347 348 self.runCmd("register write ch 0xf9") 349 self.match("register read cx", 350 ["cx = 0xf9fa"]) 351 self.match("register read ecx", 352 ["ecx = 0x1413f9fa"]) 353 354 self.runCmd("register write cl 0xf8") 355 self.match("register read cx", 356 ["cx = 0xf9f8"]) 357 self.match("register read ecx", 358 ["ecx = 0x1413f9f8"]) 359 360 self.runCmd("register write mm0 0xfffefdfcfbfaf9f8") 361 self.match("register read st0", 362 ["st0 = {0xf8 0xf9 0xfa 0xfb 0xfc 0xfd 0xfe 0xff 0x09 0x0a}"]) 363 364 @skipIfXmlSupportMissing 365 @skipIfRemote 366 @skipIfLLVMTargetMissing("AArch64") 367 def test_aarch64_regs(self): 368 """Test grabbing various aarch64 registers from gdbserver.""" 369 class MyResponder(MockGDBServerResponder): 370 reg_data = ( 371 "0102030405060708" # x0 372 "1112131415161718" # x1 373 ) + 27 * ( 374 "2122232425262728" # x2..x28 375 ) + ( 376 "3132333435363738" # x29 (fp) 377 "4142434445464748" # x30 (lr) 378 "5152535455565758" # x31 (sp) 379 "6162636465666768" # pc 380 "71727374" # cpsr 381 "8182838485868788898a8b8c8d8e8f90" # v0 382 "9192939495969798999a9b9c9d9e9fa0" # v1 383 ) + 30 * ( 384 "a1a2a3a4a5a6a7a8a9aaabacadaeafb0" # v2..v31 385 ) + ( 386 "00000000" # fpsr 387 "00000000" # fpcr 388 ) 389 390 def qXferRead(self, obj, annex, offset, length): 391 if annex == "target.xml": 392 return """<?xml version="1.0"?> 393 <!DOCTYPE feature SYSTEM "gdb-target.dtd"> 394 <target> 395 <architecture>aarch64</architecture> 396 <feature name="org.gnu.gdb.aarch64.core"> 397 <reg name="x0" bitsize="64" type="int" regnum="0"/> 398 <reg name="x1" bitsize="64" type="int" regnum="1"/> 399 <reg name="x2" bitsize="64" type="int" regnum="2"/> 400 <reg name="x3" bitsize="64" type="int" regnum="3"/> 401 <reg name="x4" bitsize="64" type="int" regnum="4"/> 402 <reg name="x5" bitsize="64" type="int" regnum="5"/> 403 <reg name="x6" bitsize="64" type="int" regnum="6"/> 404 <reg name="x7" bitsize="64" type="int" regnum="7"/> 405 <reg name="x8" bitsize="64" type="int" regnum="8"/> 406 <reg name="x9" bitsize="64" type="int" regnum="9"/> 407 <reg name="x10" bitsize="64" type="int" regnum="10"/> 408 <reg name="x11" bitsize="64" type="int" regnum="11"/> 409 <reg name="x12" bitsize="64" type="int" regnum="12"/> 410 <reg name="x13" bitsize="64" type="int" regnum="13"/> 411 <reg name="x14" bitsize="64" type="int" regnum="14"/> 412 <reg name="x15" bitsize="64" type="int" regnum="15"/> 413 <reg name="x16" bitsize="64" type="int" regnum="16"/> 414 <reg name="x17" bitsize="64" type="int" regnum="17"/> 415 <reg name="x18" bitsize="64" type="int" regnum="18"/> 416 <reg name="x19" bitsize="64" type="int" regnum="19"/> 417 <reg name="x20" bitsize="64" type="int" regnum="20"/> 418 <reg name="x21" bitsize="64" type="int" regnum="21"/> 419 <reg name="x22" bitsize="64" type="int" regnum="22"/> 420 <reg name="x23" bitsize="64" type="int" regnum="23"/> 421 <reg name="x24" bitsize="64" type="int" regnum="24"/> 422 <reg name="x25" bitsize="64" type="int" regnum="25"/> 423 <reg name="x26" bitsize="64" type="int" regnum="26"/> 424 <reg name="x27" bitsize="64" type="int" regnum="27"/> 425 <reg name="x28" bitsize="64" type="int" regnum="28"/> 426 <reg name="x29" bitsize="64" type="int" regnum="29"/> 427 <reg name="x30" bitsize="64" type="int" regnum="30"/> 428 <reg name="sp" bitsize="64" type="data_ptr" regnum="31"/> 429 <reg name="pc" bitsize="64" type="code_ptr" regnum="32"/> 430 <reg name="cpsr" bitsize="32" type="cpsr_flags" regnum="33"/> 431 </feature> 432 <feature name="org.gnu.gdb.aarch64.fpu"> 433 <reg name="v0" bitsize="128" type="aarch64v" regnum="34"/> 434 <reg name="v1" bitsize="128" type="aarch64v" regnum="35"/> 435 <reg name="v2" bitsize="128" type="aarch64v" regnum="36"/> 436 <reg name="v3" bitsize="128" type="aarch64v" regnum="37"/> 437 <reg name="v4" bitsize="128" type="aarch64v" regnum="38"/> 438 <reg name="v5" bitsize="128" type="aarch64v" regnum="39"/> 439 <reg name="v6" bitsize="128" type="aarch64v" regnum="40"/> 440 <reg name="v7" bitsize="128" type="aarch64v" regnum="41"/> 441 <reg name="v8" bitsize="128" type="aarch64v" regnum="42"/> 442 <reg name="v9" bitsize="128" type="aarch64v" regnum="43"/> 443 <reg name="v10" bitsize="128" type="aarch64v" regnum="44"/> 444 <reg name="v11" bitsize="128" type="aarch64v" regnum="45"/> 445 <reg name="v12" bitsize="128" type="aarch64v" regnum="46"/> 446 <reg name="v13" bitsize="128" type="aarch64v" regnum="47"/> 447 <reg name="v14" bitsize="128" type="aarch64v" regnum="48"/> 448 <reg name="v15" bitsize="128" type="aarch64v" regnum="49"/> 449 <reg name="v16" bitsize="128" type="aarch64v" regnum="50"/> 450 <reg name="v17" bitsize="128" type="aarch64v" regnum="51"/> 451 <reg name="v18" bitsize="128" type="aarch64v" regnum="52"/> 452 <reg name="v19" bitsize="128" type="aarch64v" regnum="53"/> 453 <reg name="v20" bitsize="128" type="aarch64v" regnum="54"/> 454 <reg name="v21" bitsize="128" type="aarch64v" regnum="55"/> 455 <reg name="v22" bitsize="128" type="aarch64v" regnum="56"/> 456 <reg name="v23" bitsize="128" type="aarch64v" regnum="57"/> 457 <reg name="v24" bitsize="128" type="aarch64v" regnum="58"/> 458 <reg name="v25" bitsize="128" type="aarch64v" regnum="59"/> 459 <reg name="v26" bitsize="128" type="aarch64v" regnum="60"/> 460 <reg name="v27" bitsize="128" type="aarch64v" regnum="61"/> 461 <reg name="v28" bitsize="128" type="aarch64v" regnum="62"/> 462 <reg name="v29" bitsize="128" type="aarch64v" regnum="63"/> 463 <reg name="v30" bitsize="128" type="aarch64v" regnum="64"/> 464 <reg name="v31" bitsize="128" type="aarch64v" regnum="65"/> 465 <reg name="fpsr" bitsize="32" type="int" regnum="66"/> 466 <reg name="fpcr" bitsize="32" type="int" regnum="67"/> 467 </feature> 468 </target>""", False 469 else: 470 return None, False 471 472 def readRegister(self, regnum): 473 return "" 474 475 def readRegisters(self): 476 return self.reg_data 477 478 def writeRegisters(self, reg_hex): 479 self.reg_data = reg_hex 480 return "OK" 481 482 def haltReason(self): 483 return "T02thread:1ff0d;threads:1ff0d;thread-pcs:000000010001bc00;07:0102030405060708;10:1112131415161718;" 484 485 self.server.responder = MyResponder() 486 487 target = self.createTarget("basic_eh_frame-aarch64.yaml") 488 process = self.connect(target) 489 lldbutil.expect_state_changes(self, self.dbg.GetListener(), process, 490 [lldb.eStateStopped]) 491 492 # test GPRs 493 self.match("register read x0", 494 ["x0 = 0x0807060504030201"]) 495 self.match("register read x1", 496 ["x1 = 0x1817161514131211"]) 497 self.match("register read x29", 498 ["x29 = 0x3837363534333231"]) 499 self.match("register read x30", 500 ["x30 = 0x4847464544434241"]) 501 self.match("register read x31", 502 ["sp = 0x5857565554535251"]) 503 self.match("register read sp", 504 ["sp = 0x5857565554535251"]) 505 self.match("register read pc", 506 ["pc = 0x6867666564636261"]) 507 self.match("register read cpsr", 508 ["cpsr = 0x74737271"]) 509 510 # test generic aliases 511 self.match("register read arg1", 512 ["x0 = 0x0807060504030201"]) 513 self.match("register read arg2", 514 ["x1 = 0x1817161514131211"]) 515 self.match("register read fp", 516 ["x29 = 0x3837363534333231"]) 517 self.match("register read lr", 518 ["x30 = 0x4847464544434241"]) 519 self.match("register read ra", 520 ["x30 = 0x4847464544434241"]) 521 self.match("register read flags", 522 ["cpsr = 0x74737271"]) 523 524 # test vector registers 525 self.match("register read v0", 526 ["v0 = {0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90}"]) 527 self.match("register read v31", 528 ["v31 = {0xa1 0xa2 0xa3 0xa4 0xa5 0xa6 0xa7 0xa8 0xa9 0xaa 0xab 0xac 0xad 0xae 0xaf 0xb0}"]) 529 530 # test partial registers 531 self.match("register read w0", 532 ["w0 = 0x04030201"]) 533 self.runCmd("register write w0 0xfffefdfc") 534 self.match("register read x0", 535 ["x0 = 0x08070605fffefdfc"]) 536 537 self.match("register read w1", 538 ["w1 = 0x14131211"]) 539 self.runCmd("register write w1 0xefeeedec") 540 self.match("register read x1", 541 ["x1 = 0x18171615efeeedec"]) 542 543 self.match("register read w30", 544 ["w30 = 0x44434241"]) 545 self.runCmd("register write w30 0xdfdedddc") 546 self.match("register read x30", 547 ["x30 = 0x48474645dfdedddc"]) 548 549 self.match("register read w31", 550 ["w31 = 0x54535251"]) 551 self.runCmd("register write w31 0xcfcecdcc") 552 self.match("register read x31", 553 ["sp = 0x58575655cfcecdcc"]) 554 555 # test FPU registers (overlapping with vector registers) 556 self.runCmd("register write d0 16") 557 self.match("register read v0", 558 ["v0 = {0x00 0x00 0x00 0x00 0x00 0x00 0x30 0x40 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90}"]) 559 self.runCmd("register write v31 '{0x00 0x00 0x00 0x00 0x00 0x00 0x50 0x40 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff}'") 560 self.match("register read d31", 561 ["d31 = 64"]) 562 563 self.runCmd("register write s0 32") 564 self.match("register read v0", 565 ["v0 = {0x00 0x00 0x00 0x42 0x00 0x00 0x30 0x40 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90}"]) 566 self.runCmd("register write v31 '{0x00 0x00 0x00 0x43 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff}'") 567 self.match("register read s31", 568 ["s31 = 128"]) 569 570 @skipIfXmlSupportMissing 571 @skipIfRemote 572 @skipIfLLVMTargetMissing("X86") 573 def test_x86_64_no_duplicate_subregs(self): 574 """Test that duplicate subregisters are not added (on x86_64).""" 575 class MyResponder(MockGDBServerResponder): 576 reg_data = ( 577 "0102030405060708" # rcx 578 "1112131415161718" # rdx 579 "2122232425262728" # rsi 580 "3132333435363738" # rdi 581 "4142434445464748" # rbp 582 "5152535455565758" # rsp 583 "6162636465666768" # r8 584 "7172737475767778" # r9 585 "8182838485868788" # rip 586 "91929394" # eflags 587 ) 588 589 def qXferRead(self, obj, annex, offset, length): 590 if annex == "target.xml": 591 return """<?xml version="1.0"?> 592 <!DOCTYPE feature SYSTEM "gdb-target.dtd"> 593 <target> 594 <architecture>i386:x86-64</architecture> 595 <osabi>GNU/Linux</osabi> 596 <feature name="org.gnu.gdb.i386.core"> 597 <reg name="rcx" bitsize="64" type="int64" regnum="2"/> 598 <reg name="rdx" bitsize="64" type="int64" regnum="3"/> 599 <reg name="rsi" bitsize="64" type="int64" regnum="4"/> 600 <reg name="rdi" bitsize="64" type="int64" regnum="5"/> 601 <reg name="rbp" bitsize="64" type="data_ptr" regnum="6"/> 602 <reg name="rsp" bitsize="64" type="data_ptr" regnum="7"/> 603 <reg name="r8" bitsize="64" type="int64" regnum="8"/> 604 <reg name="r9" bitsize="64" type="int64" regnum="9"/> 605 <reg name="rip" bitsize="64" type="code_ptr" regnum="16"/> 606 <reg name="eflags" bitsize="32" type="i386_eflags" regnum="17"/> 607 <reg name="ecx" bitsize="32" type="int" regnum="18" value_regnums="2"/> 608 </feature> 609 </target>""", False 610 else: 611 return None, False 612 613 def readRegister(self, regnum): 614 return "" 615 616 def readRegisters(self): 617 return self.reg_data 618 619 def haltReason(self): 620 return "T02thread:1ff0d;threads:1ff0d;thread-pcs:000000010001bc00;07:0102030405060708;10:1112131415161718;" 621 622 self.server.responder = MyResponder() 623 624 target = self.createTarget("basic_eh_frame.yaml") 625 process = self.connect(target) 626 lldbutil.expect_state_changes(self, self.dbg.GetListener(), process, 627 [lldb.eStateStopped]) 628 629 self.match("register read rcx", 630 ["rcx = 0x0807060504030201"]) 631 # ecx is supplied via target.xml 632 self.match("register read ecx", 633 ["ecx = 0x04030201"]) 634 self.match("register read rdx", 635 ["rdx = 0x1817161514131211"]) 636 # edx should not be added 637 self.match("register read edx", 638 ["error: Invalid register name 'edx'."], 639 error=True) 640 641 @skipIfXmlSupportMissing 642 @skipIfRemote 643 @skipIfLLVMTargetMissing("X86") 644 def test_i386_no_duplicate_subregs(self): 645 """Test that duplicate subregisters are not added (on i386).""" 646 class MyResponder(MockGDBServerResponder): 647 reg_data = ( 648 "01020304" # eax 649 "11121314" # ecx 650 "21222324" # edx 651 "31323334" # ebx 652 "41424344" # esp 653 "51525354" # ebp 654 "61626364" # esi 655 "71727374" # edi 656 "81828384" # eip 657 "91929394" # eflags 658 ) 659 660 def qXferRead(self, obj, annex, offset, length): 661 if annex == "target.xml": 662 return """<?xml version="1.0"?> 663 <!DOCTYPE feature SYSTEM "gdb-target.dtd"> 664 <target> 665 <architecture>i386</architecture> 666 <osabi>GNU/Linux</osabi> 667 <feature name="org.gnu.gdb.i386.core"> 668 <reg name="eax" bitsize="32" type="int32" regnum="0"/> 669 <reg name="ecx" bitsize="32" type="int32" regnum="1"/> 670 <reg name="edx" bitsize="32" type="int32" regnum="2"/> 671 <reg name="ebx" bitsize="32" type="int32" regnum="3"/> 672 <reg name="esp" bitsize="32" type="data_ptr" regnum="4"/> 673 <reg name="ebp" bitsize="32" type="data_ptr" regnum="5"/> 674 <reg name="esi" bitsize="32" type="int32" regnum="6"/> 675 <reg name="edi" bitsize="32" type="int32" regnum="7"/> 676 <reg name="eip" bitsize="32" type="code_ptr" regnum="8"/> 677 <reg name="eflags" bitsize="32" type="i386_eflags" regnum="9"/> 678 <reg name="ax" bitsize="16" type="int" regnum="10" value_regnums="0"/> 679 </feature> 680 </target>""", False 681 else: 682 return None, False 683 684 def readRegister(self, regnum): 685 return "" 686 687 def readRegisters(self): 688 return self.reg_data 689 690 def haltReason(self): 691 return "T02thread:1ff0d;threads:1ff0d;thread-pcs:000000010001bc00;07:0102030405060708;10:1112131415161718;" 692 693 self.server.responder = MyResponder() 694 695 target = self.createTarget("basic_eh_frame-i386.yaml") 696 process = self.connect(target) 697 lldbutil.expect_state_changes(self, self.dbg.GetListener(), process, 698 [lldb.eStateStopped]) 699 700 self.match("register read eax", 701 ["eax = 0x04030201"]) 702 # cx is supplied via target.xml 703 self.match("register read ax", 704 ["ax = 0x0201"]) 705 self.match("register read ecx", 706 ["ecx = 0x14131211"]) 707 # dx should not be added 708 self.match("register read cx", 709 ["error: Invalid register name 'cx'."], 710 error=True) 711 712 @skipIfXmlSupportMissing 713 @skipIfRemote 714 @skipIfLLVMTargetMissing("AArch64") 715 def test_aarch64_no_duplicate_subregs(self): 716 """Test that duplicate subregisters are not added.""" 717 class MyResponder(MockGDBServerResponder): 718 reg_data = ( 719 "0102030405060708" # x0 720 "1112131415161718" # x1 721 ) + 27 * ( 722 "2122232425262728" # x2..x28 723 ) + ( 724 "3132333435363738" # x29 (fp) 725 "4142434445464748" # x30 (lr) 726 "5152535455565758" # x31 (sp) 727 "6162636465666768" # pc 728 "71727374" # cpsr 729 ) 730 731 def qXferRead(self, obj, annex, offset, length): 732 if annex == "target.xml": 733 return """<?xml version="1.0"?> 734 <!DOCTYPE feature SYSTEM "gdb-target.dtd"> 735 <target> 736 <architecture>aarch64</architecture> 737 <feature name="org.gnu.gdb.aarch64.core"> 738 <reg name="x0" bitsize="64" type="int" regnum="0"/> 739 <reg name="x1" bitsize="64" type="int" regnum="1"/> 740 <reg name="x2" bitsize="64" type="int" regnum="2"/> 741 <reg name="x3" bitsize="64" type="int" regnum="3"/> 742 <reg name="x4" bitsize="64" type="int" regnum="4"/> 743 <reg name="x5" bitsize="64" type="int" regnum="5"/> 744 <reg name="x6" bitsize="64" type="int" regnum="6"/> 745 <reg name="x7" bitsize="64" type="int" regnum="7"/> 746 <reg name="x8" bitsize="64" type="int" regnum="8"/> 747 <reg name="x9" bitsize="64" type="int" regnum="9"/> 748 <reg name="x10" bitsize="64" type="int" regnum="10"/> 749 <reg name="x11" bitsize="64" type="int" regnum="11"/> 750 <reg name="x12" bitsize="64" type="int" regnum="12"/> 751 <reg name="x13" bitsize="64" type="int" regnum="13"/> 752 <reg name="x14" bitsize="64" type="int" regnum="14"/> 753 <reg name="x15" bitsize="64" type="int" regnum="15"/> 754 <reg name="x16" bitsize="64" type="int" regnum="16"/> 755 <reg name="x17" bitsize="64" type="int" regnum="17"/> 756 <reg name="x18" bitsize="64" type="int" regnum="18"/> 757 <reg name="x19" bitsize="64" type="int" regnum="19"/> 758 <reg name="x20" bitsize="64" type="int" regnum="20"/> 759 <reg name="x21" bitsize="64" type="int" regnum="21"/> 760 <reg name="x22" bitsize="64" type="int" regnum="22"/> 761 <reg name="x23" bitsize="64" type="int" regnum="23"/> 762 <reg name="x24" bitsize="64" type="int" regnum="24"/> 763 <reg name="x25" bitsize="64" type="int" regnum="25"/> 764 <reg name="x26" bitsize="64" type="int" regnum="26"/> 765 <reg name="x27" bitsize="64" type="int" regnum="27"/> 766 <reg name="x28" bitsize="64" type="int" regnum="28"/> 767 <reg name="x29" bitsize="64" type="int" regnum="29"/> 768 <reg name="x30" bitsize="64" type="int" regnum="30"/> 769 <reg name="sp" bitsize="64" type="data_ptr" regnum="31"/> 770 <reg name="pc" bitsize="64" type="code_ptr" regnum="32"/> 771 <reg name="cpsr" bitsize="32" type="cpsr_flags" regnum="33"/> 772 <reg name="w0" bitsize="32" type="int" regnum="34" value_regnums="0"/> 773 </feature> 774 </target>""", False 775 else: 776 return None, False 777 778 def readRegister(self, regnum): 779 return "" 780 781 def readRegisters(self): 782 return self.reg_data 783 784 def haltReason(self): 785 return "T02thread:1ff0d;threads:1ff0d;thread-pcs:000000010001bc00;07:0102030405060708;10:1112131415161718;" 786 787 self.server.responder = MyResponder() 788 789 target = self.createTarget("basic_eh_frame-aarch64.yaml") 790 process = self.connect(target) 791 lldbutil.expect_state_changes(self, self.dbg.GetListener(), process, 792 [lldb.eStateStopped]) 793 794 self.match("register read x0", 795 ["x0 = 0x0807060504030201"]) 796 # w0 comes from target.xml 797 self.match("register read w0", 798 ["w0 = 0x04030201"]) 799 self.match("register read x1", 800 ["x1 = 0x1817161514131211"]) 801 # w1 should not be added 802 self.match("register read w1", 803 ["error: Invalid register name 'w1'."], 804 error=True) 805