1from __future__ import print_function 2import lldb 3from lldbsuite.test.lldbtest import * 4from lldbsuite.test.decorators import * 5from gdbclientutils import * 6 7 8class TestGDBServerTargetXML(GDBRemoteTestBase): 9 10 @skipIfXmlSupportMissing 11 @skipIfRemote 12 @skipIfLLVMTargetMissing("X86") 13 def test_x86_64_regs(self): 14 """Test grabbing various x86_64 registers from gdbserver.""" 15 reg_data = [ 16 "0102030405060708", # rcx 17 "1112131415161718", # rdx 18 "2122232425262728", # rsi 19 "3132333435363738", # rdi 20 "4142434445464748", # rbp 21 "5152535455565758", # rsp 22 "6162636465666768", # r8 23 "7172737475767778", # r9 24 "8182838485868788", # rip 25 "91929394", # eflags 26 "0102030405060708090a", # st0 27 "1112131415161718191a", # st1 28 ] + 6 * [ 29 "2122232425262728292a" # st2..st7 30 ] + [ 31 "8182838485868788898a8b8c8d8e8f90", # xmm0 32 "9192939495969798999a9b9c9d9e9fa0", # xmm1 33 ] + 14 * [ 34 "a1a2a3a4a5a6a7a8a9aaabacadaeafb0", # xmm2..xmm15 35 ] + [ 36 "00000000", # mxcsr 37 ] + [ 38 "b1b2b3b4b5b6b7b8b9babbbcbdbebfc0", # ymm0h 39 "c1c2c3c4c5c6c7c8c9cacbcccdcecfd0", # ymm1h 40 ] + 14 * [ 41 "d1d2d3d4d5d6d7d8d9dadbdcdddedfe0", # ymm2h..ymm15h 42 ] 43 44 class MyResponder(MockGDBServerResponder): 45 def qXferRead(self, obj, annex, offset, length): 46 if annex == "target.xml": 47 return """<?xml version="1.0"?> 48 <!DOCTYPE feature SYSTEM "gdb-target.dtd"> 49 <target> 50 <architecture>i386:x86-64</architecture> 51 <osabi>GNU/Linux</osabi> 52 <feature name="org.gnu.gdb.i386.core"> 53 <reg name="rcx" bitsize="64" type="int64" regnum="2"/> 54 <reg name="rdx" bitsize="64" type="int64" regnum="3"/> 55 <reg name="rsi" bitsize="64" type="int64" regnum="4"/> 56 <reg name="rdi" bitsize="64" type="int64" regnum="5"/> 57 <reg name="rbp" bitsize="64" type="data_ptr" regnum="6"/> 58 <reg name="rsp" bitsize="64" type="data_ptr" regnum="7"/> 59 <reg name="r8" bitsize="64" type="int64" regnum="8"/> 60 <reg name="r9" bitsize="64" type="int64" regnum="9"/> 61 <reg name="rip" bitsize="64" type="code_ptr" regnum="16"/> 62 <reg name="eflags" bitsize="32" type="i386_eflags" regnum="17"/> 63 <reg name="st0" bitsize="80" type="i387_ext" regnum="24"/> 64 <reg name="st1" bitsize="80" type="i387_ext" regnum="25"/> 65 <reg name="st2" bitsize="80" type="i387_ext" regnum="26"/> 66 <reg name="st3" bitsize="80" type="i387_ext" regnum="27"/> 67 <reg name="st4" bitsize="80" type="i387_ext" regnum="28"/> 68 <reg name="st5" bitsize="80" type="i387_ext" regnum="29"/> 69 <reg name="st6" bitsize="80" type="i387_ext" regnum="30"/> 70 <reg name="st7" bitsize="80" type="i387_ext" regnum="31"/> 71 </feature> 72 <feature name="org.gnu.gdb.i386.sse"> 73 <reg name="xmm0" bitsize="128" type="vec128" regnum="40"/> 74 <reg name="xmm1" bitsize="128" type="vec128" regnum="41"/> 75 <reg name="xmm2" bitsize="128" type="vec128" regnum="42"/> 76 <reg name="xmm3" bitsize="128" type="vec128" regnum="43"/> 77 <reg name="xmm4" bitsize="128" type="vec128" regnum="44"/> 78 <reg name="xmm5" bitsize="128" type="vec128" regnum="45"/> 79 <reg name="xmm6" bitsize="128" type="vec128" regnum="46"/> 80 <reg name="xmm7" bitsize="128" type="vec128" regnum="47"/> 81 <reg name="xmm8" bitsize="128" type="vec128" regnum="48"/> 82 <reg name="xmm9" bitsize="128" type="vec128" regnum="49"/> 83 <reg name="xmm10" bitsize="128" type="vec128" regnum="50"/> 84 <reg name="xmm11" bitsize="128" type="vec128" regnum="51"/> 85 <reg name="xmm12" bitsize="128" type="vec128" regnum="52"/> 86 <reg name="xmm13" bitsize="128" type="vec128" regnum="53"/> 87 <reg name="xmm14" bitsize="128" type="vec128" regnum="54"/> 88 <reg name="xmm15" bitsize="128" type="vec128" regnum="55"/> 89 <reg name="mxcsr" bitsize="32" type="i386_mxcsr" regnum="56" group="vector"/> 90 </feature> 91 <feature name="org.gnu.gdb.i386.avx"> 92 <reg name="ymm0h" bitsize="128" type="uint128" regnum="60"/> 93 <reg name="ymm1h" bitsize="128" type="uint128" regnum="61"/> 94 <reg name="ymm2h" bitsize="128" type="uint128" regnum="62"/> 95 <reg name="ymm3h" bitsize="128" type="uint128" regnum="63"/> 96 <reg name="ymm4h" bitsize="128" type="uint128" regnum="64"/> 97 <reg name="ymm5h" bitsize="128" type="uint128" regnum="65"/> 98 <reg name="ymm6h" bitsize="128" type="uint128" regnum="66"/> 99 <reg name="ymm7h" bitsize="128" type="uint128" regnum="67"/> 100 <reg name="ymm8h" bitsize="128" type="uint128" regnum="68"/> 101 <reg name="ymm9h" bitsize="128" type="uint128" regnum="69"/> 102 <reg name="ymm10h" bitsize="128" type="uint128" regnum="70"/> 103 <reg name="ymm11h" bitsize="128" type="uint128" regnum="71"/> 104 <reg name="ymm12h" bitsize="128" type="uint128" regnum="72"/> 105 <reg name="ymm13h" bitsize="128" type="uint128" regnum="73"/> 106 <reg name="ymm14h" bitsize="128" type="uint128" regnum="74"/> 107 <reg name="ymm15h" bitsize="128" type="uint128" regnum="75"/> 108 </feature> 109 </target>""", False 110 else: 111 return None, False 112 113 def readRegister(self, regnum): 114 return "" 115 116 def readRegisters(self): 117 return "".join(reg_data) 118 119 def writeRegisters(self, reg_hex): 120 return "OK" 121 122 def haltReason(self): 123 return "T02thread:1ff0d;threads:1ff0d;thread-pcs:000000010001bc00;07:0102030405060708;10:1112131415161718;" 124 125 self.server.responder = MyResponder() 126 127 target = self.createTarget("basic_eh_frame.yaml") 128 process = self.connect(target) 129 lldbutil.expect_state_changes(self, self.dbg.GetListener(), process, 130 [lldb.eStateStopped]) 131 132 # test generic aliases 133 self.match("register read arg4", 134 ["rcx = 0x0807060504030201"]) 135 self.match("register read arg3", 136 ["rdx = 0x1817161514131211"]) 137 self.match("register read arg2", 138 ["rsi = 0x2827262524232221"]) 139 self.match("register read arg1", 140 ["rdi = 0x3837363534333231"]) 141 self.match("register read fp", 142 ["rbp = 0x4847464544434241"]) 143 self.match("register read sp", 144 ["rsp = 0x5857565554535251"]) 145 self.match("register read arg5", 146 ["r8 = 0x6867666564636261"]) 147 self.match("register read arg6", 148 ["r9 = 0x7877767574737271"]) 149 self.match("register read pc", 150 ["rip = 0x8887868584838281"]) 151 self.match("register read flags", 152 ["eflags = 0x94939291"]) 153 154 @skipIfXmlSupportMissing 155 @skipIfRemote 156 @skipIfLLVMTargetMissing("X86") 157 def test_i386_regs(self): 158 """Test grabbing various i386 registers from gdbserver.""" 159 reg_data = [ 160 "01020304", # eax 161 "11121314", # ecx 162 "21222324", # edx 163 "31323334", # ebx 164 "41424344", # esp 165 "51525354", # ebp 166 "61626364", # esi 167 "71727374", # edi 168 "81828384", # eip 169 "91929394", # eflags 170 "0102030405060708090a", # st0 171 "1112131415161718191a", # st1 172 ] + 6 * [ 173 "2122232425262728292a" # st2..st7 174 ] + [ 175 "8182838485868788898a8b8c8d8e8f90", # xmm0 176 "9192939495969798999a9b9c9d9e9fa0", # xmm1 177 ] + 6 * [ 178 "a1a2a3a4a5a6a7a8a9aaabacadaeafb0", # xmm2..xmm7 179 ] + [ 180 "00000000", # mxcsr 181 ] + [ 182 "b1b2b3b4b5b6b7b8b9babbbcbdbebfc0", # ymm0h 183 "c1c2c3c4c5c6c7c8c9cacbcccdcecfd0", # ymm1h 184 ] + 6 * [ 185 "d1d2d3d4d5d6d7d8d9dadbdcdddedfe0", # ymm2h..ymm7h 186 ] 187 188 class MyResponder(MockGDBServerResponder): 189 def qXferRead(self, obj, annex, offset, length): 190 if annex == "target.xml": 191 return """<?xml version="1.0"?> 192 <!DOCTYPE feature SYSTEM "gdb-target.dtd"> 193 <target> 194 <architecture>i386</architecture> 195 <osabi>GNU/Linux</osabi> 196 <feature name="org.gnu.gdb.i386.core"> 197 <reg name="eax" bitsize="32" type="int32" regnum="0"/> 198 <reg name="ecx" bitsize="32" type="int32" regnum="1"/> 199 <reg name="edx" bitsize="32" type="int32" regnum="2"/> 200 <reg name="ebx" bitsize="32" type="int32" regnum="3"/> 201 <reg name="esp" bitsize="32" type="data_ptr" regnum="4"/> 202 <reg name="ebp" bitsize="32" type="data_ptr" regnum="5"/> 203 <reg name="esi" bitsize="32" type="int32" regnum="6"/> 204 <reg name="edi" bitsize="32" type="int32" regnum="7"/> 205 <reg name="eip" bitsize="32" type="code_ptr" regnum="8"/> 206 <reg name="eflags" bitsize="32" type="i386_eflags" regnum="9"/> 207 <reg name="st0" bitsize="80" type="i387_ext" regnum="16"/> 208 <reg name="st1" bitsize="80" type="i387_ext" regnum="17"/> 209 <reg name="st2" bitsize="80" type="i387_ext" regnum="18"/> 210 <reg name="st3" bitsize="80" type="i387_ext" regnum="19"/> 211 <reg name="st4" bitsize="80" type="i387_ext" regnum="20"/> 212 <reg name="st5" bitsize="80" type="i387_ext" regnum="21"/> 213 <reg name="st6" bitsize="80" type="i387_ext" regnum="22"/> 214 <reg name="st7" bitsize="80" type="i387_ext" regnum="23"/> 215 </feature> 216 <feature name="org.gnu.gdb.i386.sse"> 217 <reg name="xmm0" bitsize="128" type="vec128" regnum="32"/> 218 <reg name="xmm1" bitsize="128" type="vec128" regnum="33"/> 219 <reg name="xmm2" bitsize="128" type="vec128" regnum="34"/> 220 <reg name="xmm3" bitsize="128" type="vec128" regnum="35"/> 221 <reg name="xmm4" bitsize="128" type="vec128" regnum="36"/> 222 <reg name="xmm5" bitsize="128" type="vec128" regnum="37"/> 223 <reg name="xmm6" bitsize="128" type="vec128" regnum="38"/> 224 <reg name="xmm7" bitsize="128" type="vec128" regnum="39"/> 225 <reg name="mxcsr" bitsize="32" type="i386_mxcsr" regnum="40" group="vector"/> 226 </feature> 227 <feature name="org.gnu.gdb.i386.avx"> 228 <reg name="ymm0h" bitsize="128" type="uint128" regnum="42"/> 229 <reg name="ymm1h" bitsize="128" type="uint128" regnum="43"/> 230 <reg name="ymm2h" bitsize="128" type="uint128" regnum="44"/> 231 <reg name="ymm3h" bitsize="128" type="uint128" regnum="45"/> 232 <reg name="ymm4h" bitsize="128" type="uint128" regnum="46"/> 233 <reg name="ymm5h" bitsize="128" type="uint128" regnum="47"/> 234 <reg name="ymm6h" bitsize="128" type="uint128" regnum="48"/> 235 <reg name="ymm7h" bitsize="128" type="uint128" regnum="49"/> 236 </feature> 237 </target>""", False 238 else: 239 return None, False 240 241 def readRegister(self, regnum): 242 return "" 243 244 def readRegisters(self): 245 return "".join(reg_data) 246 247 def writeRegisters(self, reg_hex): 248 return "OK" 249 250 def haltReason(self): 251 return "T02thread:1ff0d;threads:1ff0d;thread-pcs:000000010001bc00;07:0102030405060708;10:1112131415161718;" 252 253 self.server.responder = MyResponder() 254 255 target = self.createTarget("basic_eh_frame-i386.yaml") 256 process = self.connect(target) 257 lldbutil.expect_state_changes(self, self.dbg.GetListener(), process, 258 [lldb.eStateStopped]) 259 260 # test generic aliases 261 self.match("register read fp", 262 ["ebp = 0x54535251"]) 263 self.match("register read pc", 264 ["eip = 0x84838281"]) 265 self.match("register read flags", 266 ["eflags = 0x94939291"]) 267 268 @skipIfXmlSupportMissing 269 @skipIfRemote 270 @skipIfLLVMTargetMissing("AArch64") 271 def test_aarch64_regs(self): 272 """Test grabbing various aarch64 registers from gdbserver.""" 273 class MyResponder(MockGDBServerResponder): 274 reg_data = ( 275 "0102030405060708" # x0 276 "1112131415161718" # x1 277 ) + 27 * ( 278 "2122232425262728" # x2..x28 279 ) + ( 280 "3132333435363738" # x29 (fp) 281 "4142434445464748" # x30 (lr) 282 "5152535455565758" # x31 (sp) 283 "6162636465666768" # pc 284 "71727374" # cpsr 285 "8182838485868788898a8b8c8d8e8f90" # v0 286 "9192939495969798999a9b9c9d9e9fa0" # v1 287 ) + 30 * ( 288 "a1a2a3a4a5a6a7a8a9aaabacadaeafb0" # v2..v31 289 ) + ( 290 "00000000" # fpsr 291 "00000000" # fpcr 292 ) 293 294 def qXferRead(self, obj, annex, offset, length): 295 if annex == "target.xml": 296 return """<?xml version="1.0"?> 297 <!DOCTYPE feature SYSTEM "gdb-target.dtd"> 298 <target> 299 <architecture>aarch64</architecture> 300 <feature name="org.gnu.gdb.aarch64.core"> 301 <reg name="x0" bitsize="64" type="int" regnum="0"/> 302 <reg name="x1" bitsize="64" type="int" regnum="1"/> 303 <reg name="x2" bitsize="64" type="int" regnum="2"/> 304 <reg name="x3" bitsize="64" type="int" regnum="3"/> 305 <reg name="x4" bitsize="64" type="int" regnum="4"/> 306 <reg name="x5" bitsize="64" type="int" regnum="5"/> 307 <reg name="x6" bitsize="64" type="int" regnum="6"/> 308 <reg name="x7" bitsize="64" type="int" regnum="7"/> 309 <reg name="x8" bitsize="64" type="int" regnum="8"/> 310 <reg name="x9" bitsize="64" type="int" regnum="9"/> 311 <reg name="x10" bitsize="64" type="int" regnum="10"/> 312 <reg name="x11" bitsize="64" type="int" regnum="11"/> 313 <reg name="x12" bitsize="64" type="int" regnum="12"/> 314 <reg name="x13" bitsize="64" type="int" regnum="13"/> 315 <reg name="x14" bitsize="64" type="int" regnum="14"/> 316 <reg name="x15" bitsize="64" type="int" regnum="15"/> 317 <reg name="x16" bitsize="64" type="int" regnum="16"/> 318 <reg name="x17" bitsize="64" type="int" regnum="17"/> 319 <reg name="x18" bitsize="64" type="int" regnum="18"/> 320 <reg name="x19" bitsize="64" type="int" regnum="19"/> 321 <reg name="x20" bitsize="64" type="int" regnum="20"/> 322 <reg name="x21" bitsize="64" type="int" regnum="21"/> 323 <reg name="x22" bitsize="64" type="int" regnum="22"/> 324 <reg name="x23" bitsize="64" type="int" regnum="23"/> 325 <reg name="x24" bitsize="64" type="int" regnum="24"/> 326 <reg name="x25" bitsize="64" type="int" regnum="25"/> 327 <reg name="x26" bitsize="64" type="int" regnum="26"/> 328 <reg name="x27" bitsize="64" type="int" regnum="27"/> 329 <reg name="x28" bitsize="64" type="int" regnum="28"/> 330 <reg name="x29" bitsize="64" type="int" regnum="29"/> 331 <reg name="x30" bitsize="64" type="int" regnum="30"/> 332 <reg name="sp" bitsize="64" type="data_ptr" regnum="31"/> 333 <reg name="pc" bitsize="64" type="code_ptr" regnum="32"/> 334 <reg name="cpsr" bitsize="32" type="cpsr_flags" regnum="33"/> 335 </feature> 336 <feature name="org.gnu.gdb.aarch64.fpu"> 337 <reg name="v0" bitsize="128" type="aarch64v" regnum="34"/> 338 <reg name="v1" bitsize="128" type="aarch64v" regnum="35"/> 339 <reg name="v2" bitsize="128" type="aarch64v" regnum="36"/> 340 <reg name="v3" bitsize="128" type="aarch64v" regnum="37"/> 341 <reg name="v4" bitsize="128" type="aarch64v" regnum="38"/> 342 <reg name="v5" bitsize="128" type="aarch64v" regnum="39"/> 343 <reg name="v6" bitsize="128" type="aarch64v" regnum="40"/> 344 <reg name="v7" bitsize="128" type="aarch64v" regnum="41"/> 345 <reg name="v8" bitsize="128" type="aarch64v" regnum="42"/> 346 <reg name="v9" bitsize="128" type="aarch64v" regnum="43"/> 347 <reg name="v10" bitsize="128" type="aarch64v" regnum="44"/> 348 <reg name="v11" bitsize="128" type="aarch64v" regnum="45"/> 349 <reg name="v12" bitsize="128" type="aarch64v" regnum="46"/> 350 <reg name="v13" bitsize="128" type="aarch64v" regnum="47"/> 351 <reg name="v14" bitsize="128" type="aarch64v" regnum="48"/> 352 <reg name="v15" bitsize="128" type="aarch64v" regnum="49"/> 353 <reg name="v16" bitsize="128" type="aarch64v" regnum="50"/> 354 <reg name="v17" bitsize="128" type="aarch64v" regnum="51"/> 355 <reg name="v18" bitsize="128" type="aarch64v" regnum="52"/> 356 <reg name="v19" bitsize="128" type="aarch64v" regnum="53"/> 357 <reg name="v20" bitsize="128" type="aarch64v" regnum="54"/> 358 <reg name="v21" bitsize="128" type="aarch64v" regnum="55"/> 359 <reg name="v22" bitsize="128" type="aarch64v" regnum="56"/> 360 <reg name="v23" bitsize="128" type="aarch64v" regnum="57"/> 361 <reg name="v24" bitsize="128" type="aarch64v" regnum="58"/> 362 <reg name="v25" bitsize="128" type="aarch64v" regnum="59"/> 363 <reg name="v26" bitsize="128" type="aarch64v" regnum="60"/> 364 <reg name="v27" bitsize="128" type="aarch64v" regnum="61"/> 365 <reg name="v28" bitsize="128" type="aarch64v" regnum="62"/> 366 <reg name="v29" bitsize="128" type="aarch64v" regnum="63"/> 367 <reg name="v30" bitsize="128" type="aarch64v" regnum="64"/> 368 <reg name="v31" bitsize="128" type="aarch64v" regnum="65"/> 369 <reg name="fpsr" bitsize="32" type="int" regnum="66"/> 370 <reg name="fpcr" bitsize="32" type="int" regnum="67"/> 371 </feature> 372 </target>""", False 373 else: 374 return None, False 375 376 def readRegister(self, regnum): 377 return "" 378 379 def readRegisters(self): 380 return self.reg_data 381 382 def writeRegisters(self, reg_hex): 383 self.reg_data = reg_hex 384 return "OK" 385 386 def haltReason(self): 387 return "T02thread:1ff0d;threads:1ff0d;thread-pcs:000000010001bc00;07:0102030405060708;10:1112131415161718;" 388 389 self.server.responder = MyResponder() 390 391 target = self.createTarget("basic_eh_frame-aarch64.yaml") 392 process = self.connect(target) 393 lldbutil.expect_state_changes(self, self.dbg.GetListener(), process, 394 [lldb.eStateStopped]) 395 396 # test GPRs 397 self.match("register read x0", 398 ["x0 = 0x0807060504030201"]) 399 self.match("register read x1", 400 ["x1 = 0x1817161514131211"]) 401 self.match("register read x29", 402 ["x29 = 0x3837363534333231"]) 403 self.match("register read x30", 404 ["x30 = 0x4847464544434241"]) 405 self.match("register read x31", 406 ["sp = 0x5857565554535251"]) 407 self.match("register read sp", 408 ["sp = 0x5857565554535251"]) 409 self.match("register read pc", 410 ["pc = 0x6867666564636261"]) 411 self.match("register read cpsr", 412 ["cpsr = 0x74737271"]) 413 414 # test generic aliases 415 self.match("register read arg1", 416 ["x0 = 0x0807060504030201"]) 417 self.match("register read arg2", 418 ["x1 = 0x1817161514131211"]) 419 self.match("register read fp", 420 ["x29 = 0x3837363534333231"]) 421 self.match("register read lr", 422 ["x30 = 0x4847464544434241"]) 423 self.match("register read ra", 424 ["x30 = 0x4847464544434241"]) 425 self.match("register read flags", 426 ["cpsr = 0x74737271"]) 427 428 # test vector registers 429 self.match("register read v0", 430 ["v0 = {0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90}"]) 431 self.match("register read v31", 432 ["v31 = {0xa1 0xa2 0xa3 0xa4 0xa5 0xa6 0xa7 0xa8 0xa9 0xaa 0xab 0xac 0xad 0xae 0xaf 0xb0}"]) 433 434 # test partial registers 435 self.match("register read w0", 436 ["w0 = 0x04030201"]) 437 self.runCmd("register write w0 0xfffefdfc") 438 self.match("register read x0", 439 ["x0 = 0x08070605fffefdfc"]) 440 441 self.match("register read w1", 442 ["w1 = 0x14131211"]) 443 self.runCmd("register write w1 0xefeeedec") 444 self.match("register read x1", 445 ["x1 = 0x18171615efeeedec"]) 446 447 self.match("register read w30", 448 ["w30 = 0x44434241"]) 449 self.runCmd("register write w30 0xdfdedddc") 450 self.match("register read x30", 451 ["x30 = 0x48474645dfdedddc"]) 452 453 self.match("register read w31", 454 ["w31 = 0x54535251"]) 455 self.runCmd("register write w31 0xcfcecdcc") 456 self.match("register read x31", 457 ["sp = 0x58575655cfcecdcc"]) 458 459 # test FPU registers (overlapping with vector registers) 460 self.runCmd("register write d0 16") 461 self.match("register read v0", 462 ["v0 = {0x00 0x00 0x00 0x00 0x00 0x00 0x30 0x40 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90}"]) 463 self.runCmd("register write v31 '{0x00 0x00 0x00 0x00 0x00 0x00 0x50 0x40 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff}'") 464 self.match("register read d31", 465 ["d31 = 64"]) 466 467 self.runCmd("register write s0 32") 468 self.match("register read v0", 469 ["v0 = {0x00 0x00 0x00 0x42 0x00 0x00 0x30 0x40 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90}"]) 470 self.runCmd("register write v31 '{0x00 0x00 0x00 0x43 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff}'") 471 self.match("register read s31", 472 ["s31 = 128"]) 473