1from __future__ import print_function 2import lldb 3from lldbsuite.test.lldbtest import * 4from lldbsuite.test.decorators import * 5from lldbsuite.test.gdbclientutils import * 6from lldbsuite.test.lldbgdbclient import GDBRemoteTestBase 7 8 9class TestGDBServerTargetXML(GDBRemoteTestBase): 10 11 mydir = TestBase.compute_mydir(__file__) 12 13 @skipIfXmlSupportMissing 14 @skipIfRemote 15 @skipIfLLVMTargetMissing("X86") 16 def test_x86_64_regs(self): 17 """Test grabbing various x86_64 registers from gdbserver.""" 18 class MyResponder(MockGDBServerResponder): 19 reg_data = ( 20 "0102030405060708" # rcx 21 "1112131415161718" # rdx 22 "2122232425262728" # rsi 23 "3132333435363738" # rdi 24 "4142434445464748" # rbp 25 "5152535455565758" # rsp 26 "6162636465666768" # r8 27 "7172737475767778" # r9 28 "8182838485868788" # rip 29 "91929394" # eflags 30 "0102030405060708090a" # st0 31 "1112131415161718191a" # st1 32 ) + 6 * ( 33 "2122232425262728292a" # st2..st7 34 ) + ( 35 "8182838485868788898a8b8c8d8e8f90" # xmm0 36 "9192939495969798999a9b9c9d9e9fa0" # xmm1 37 ) + 14 * ( 38 "a1a2a3a4a5a6a7a8a9aaabacadaeafb0" # xmm2..xmm15 39 ) + ( 40 "00000000" # mxcsr 41 ) + ( 42 "b1b2b3b4b5b6b7b8b9babbbcbdbebfc0" # ymm0h 43 "c1c2c3c4c5c6c7c8c9cacbcccdcecfd0" # ymm1h 44 ) + 14 * ( 45 "d1d2d3d4d5d6d7d8d9dadbdcdddedfe0" # ymm2h..ymm15h 46 ) 47 48 def qXferRead(self, obj, annex, offset, length): 49 if annex == "target.xml": 50 return """<?xml version="1.0"?> 51 <!DOCTYPE feature SYSTEM "gdb-target.dtd"> 52 <target> 53 <architecture>i386:x86-64</architecture> 54 <osabi>GNU/Linux</osabi> 55 <feature name="org.gnu.gdb.i386.core"> 56 <reg name="rcx" bitsize="64" type="int64" regnum="2"/> 57 <reg name="rdx" bitsize="64" type="int64" regnum="3"/> 58 <reg name="rsi" bitsize="64" type="int64" regnum="4"/> 59 <reg name="rdi" bitsize="64" type="int64" regnum="5"/> 60 <reg name="rbp" bitsize="64" type="data_ptr" regnum="6"/> 61 <reg name="rsp" bitsize="64" type="data_ptr" regnum="7"/> 62 <reg name="r8" bitsize="64" type="int64" regnum="8"/> 63 <reg name="r9" bitsize="64" type="int64" regnum="9"/> 64 <reg name="rip" bitsize="64" type="code_ptr" regnum="16"/> 65 <reg name="eflags" bitsize="32" type="i386_eflags" regnum="17"/> 66 <reg name="st0" bitsize="80" type="i387_ext" regnum="24"/> 67 <reg name="st1" bitsize="80" type="i387_ext" regnum="25"/> 68 <reg name="st2" bitsize="80" type="i387_ext" regnum="26"/> 69 <reg name="st3" bitsize="80" type="i387_ext" regnum="27"/> 70 <reg name="st4" bitsize="80" type="i387_ext" regnum="28"/> 71 <reg name="st5" bitsize="80" type="i387_ext" regnum="29"/> 72 <reg name="st6" bitsize="80" type="i387_ext" regnum="30"/> 73 <reg name="st7" bitsize="80" type="i387_ext" regnum="31"/> 74 </feature> 75 <feature name="org.gnu.gdb.i386.sse"> 76 <reg name="xmm0" bitsize="128" type="vec128" regnum="40"/> 77 <reg name="xmm1" bitsize="128" type="vec128" regnum="41"/> 78 <reg name="xmm2" bitsize="128" type="vec128" regnum="42"/> 79 <reg name="xmm3" bitsize="128" type="vec128" regnum="43"/> 80 <reg name="xmm4" bitsize="128" type="vec128" regnum="44"/> 81 <reg name="xmm5" bitsize="128" type="vec128" regnum="45"/> 82 <reg name="xmm6" bitsize="128" type="vec128" regnum="46"/> 83 <reg name="xmm7" bitsize="128" type="vec128" regnum="47"/> 84 <reg name="xmm8" bitsize="128" type="vec128" regnum="48"/> 85 <reg name="xmm9" bitsize="128" type="vec128" regnum="49"/> 86 <reg name="xmm10" bitsize="128" type="vec128" regnum="50"/> 87 <reg name="xmm11" bitsize="128" type="vec128" regnum="51"/> 88 <reg name="xmm12" bitsize="128" type="vec128" regnum="52"/> 89 <reg name="xmm13" bitsize="128" type="vec128" regnum="53"/> 90 <reg name="xmm14" bitsize="128" type="vec128" regnum="54"/> 91 <reg name="xmm15" bitsize="128" type="vec128" regnum="55"/> 92 <reg name="mxcsr" bitsize="32" type="i386_mxcsr" regnum="56" group="vector"/> 93 </feature> 94 <feature name="org.gnu.gdb.i386.avx"> 95 <reg name="ymm0h" bitsize="128" type="uint128" regnum="60"/> 96 <reg name="ymm1h" bitsize="128" type="uint128" regnum="61"/> 97 <reg name="ymm2h" bitsize="128" type="uint128" regnum="62"/> 98 <reg name="ymm3h" bitsize="128" type="uint128" regnum="63"/> 99 <reg name="ymm4h" bitsize="128" type="uint128" regnum="64"/> 100 <reg name="ymm5h" bitsize="128" type="uint128" regnum="65"/> 101 <reg name="ymm6h" bitsize="128" type="uint128" regnum="66"/> 102 <reg name="ymm7h" bitsize="128" type="uint128" regnum="67"/> 103 <reg name="ymm8h" bitsize="128" type="uint128" regnum="68"/> 104 <reg name="ymm9h" bitsize="128" type="uint128" regnum="69"/> 105 <reg name="ymm10h" bitsize="128" type="uint128" regnum="70"/> 106 <reg name="ymm11h" bitsize="128" type="uint128" regnum="71"/> 107 <reg name="ymm12h" bitsize="128" type="uint128" regnum="72"/> 108 <reg name="ymm13h" bitsize="128" type="uint128" regnum="73"/> 109 <reg name="ymm14h" bitsize="128" type="uint128" regnum="74"/> 110 <reg name="ymm15h" bitsize="128" type="uint128" regnum="75"/> 111 </feature> 112 </target>""", False 113 else: 114 return None, False 115 116 def readRegister(self, regnum): 117 return "" 118 119 def readRegisters(self): 120 return self.reg_data 121 122 def writeRegisters(self, reg_hex): 123 self.reg_data = reg_hex 124 return "OK" 125 126 def haltReason(self): 127 return "T02thread:1ff0d;threads:1ff0d;thread-pcs:000000010001bc00;07:0102030405060708;10:1112131415161718;" 128 129 self.server.responder = MyResponder() 130 131 target = self.createTarget("basic_eh_frame.yaml") 132 process = self.connect(target) 133 lldbutil.expect_state_changes(self, self.dbg.GetListener(), process, 134 [lldb.eStateStopped]) 135 136 # test generic aliases 137 self.match("register read arg4", 138 ["rcx = 0x0807060504030201"]) 139 self.match("register read arg3", 140 ["rdx = 0x1817161514131211"]) 141 self.match("register read arg2", 142 ["rsi = 0x2827262524232221"]) 143 self.match("register read arg1", 144 ["rdi = 0x3837363534333231"]) 145 self.match("register read fp", 146 ["rbp = 0x4847464544434241"]) 147 self.match("register read sp", 148 ["rsp = 0x5857565554535251"]) 149 self.match("register read arg5", 150 ["r8 = 0x6867666564636261"]) 151 self.match("register read arg6", 152 ["r9 = 0x7877767574737271"]) 153 self.match("register read pc", 154 ["rip = 0x8887868584838281"]) 155 self.match("register read flags", 156 ["eflags = 0x94939291"]) 157 158 # both stX and xmmX should be displayed as vectors 159 self.match("register read st0", 160 ["st0 = {0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a}"]) 161 self.match("register read st1", 162 ["st1 = {0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a}"]) 163 self.match("register read xmm0", 164 ["xmm0 = {0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 " 165 "0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90}"]) 166 self.match("register read xmm1", 167 ["xmm1 = {0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 " 168 "0x99 0x9a 0x9b 0x9c 0x9d 0x9e 0x9f 0xa0}"]) 169 170 # test pseudo-registers 171 self.filecheck("register read --all", 172 os.path.join(os.path.dirname(__file__), 173 "amd64-partial-regs.FileCheck")) 174 175 # test writing into pseudo-registers 176 self.runCmd("register write ecx 0xfffefdfc") 177 self.match("register read rcx", 178 ["rcx = 0x08070605fffefdfc"]) 179 180 self.runCmd("register write cx 0xfbfa") 181 self.match("register read ecx", 182 ["ecx = 0xfffefbfa"]) 183 self.match("register read rcx", 184 ["rcx = 0x08070605fffefbfa"]) 185 186 self.runCmd("register write ch 0xf9") 187 self.match("register read cx", 188 ["cx = 0xf9fa"]) 189 self.match("register read ecx", 190 ["ecx = 0xfffef9fa"]) 191 self.match("register read rcx", 192 ["rcx = 0x08070605fffef9fa"]) 193 194 self.runCmd("register write cl 0xf8") 195 self.match("register read cx", 196 ["cx = 0xf9f8"]) 197 self.match("register read ecx", 198 ["ecx = 0xfffef9f8"]) 199 self.match("register read rcx", 200 ["rcx = 0x08070605fffef9f8"]) 201 202 self.runCmd("register write mm0 0xfffefdfcfbfaf9f8") 203 self.match("register read st0", 204 ["st0 = {0xf8 0xf9 0xfa 0xfb 0xfc 0xfd 0xfe 0xff 0x09 0x0a}"]) 205 206 self.runCmd("register write xmm0 \"{0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 " 207 "0xf8 0xf7 0xf6 0xf5 0xf4 0xf3 0xf2 0xf1 0xf0}\"") 208 self.match("register read ymm0", 209 ["ymm0 = {0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 0xf8 0xf7 0xf6 " 210 "0xf5 0xf4 0xf3 0xf2 0xf1 0xf0 0xb1 0xb2 0xb3 0xb4 0xb5 " 211 "0xb6 0xb7 0xb8 0xb9 0xba 0xbb 0xbc 0xbd 0xbe 0xbf 0xc0}"]) 212 213 self.runCmd("register write ymm0h \"{0xef 0xee 0xed 0xec 0xeb 0xea 0xe9 " 214 "0xe8 0xe7 0xe6 0xe5 0xe4 0xe3 0xe2 0xe1 0xe0}\"") 215 self.match("register read ymm0", 216 ["ymm0 = {0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 0xf8 0xf7 0xf6 " 217 "0xf5 0xf4 0xf3 0xf2 0xf1 0xf0 0xef 0xee 0xed 0xec 0xeb " 218 "0xea 0xe9 0xe8 0xe7 0xe6 0xe5 0xe4 0xe3 0xe2 0xe1 0xe0}"]) 219 220 self.runCmd("register write ymm0 \"{0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 " 221 "0xd7 0xd8 0xd9 0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 " 222 "0xe2 0xe3 0xe4 0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec " 223 "0xed 0xee 0xef}\"") 224 self.match("register read ymm0", 225 ["ymm0 = {0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 0xd7 0xd8 0xd9 " 226 "0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 0xe2 0xe3 0xe4 " 227 "0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec 0xed 0xee 0xef}"]) 228 229 @skipIfXmlSupportMissing 230 @skipIfRemote 231 @skipIfLLVMTargetMissing("X86") 232 def test_i386_regs(self): 233 """Test grabbing various i386 registers from gdbserver.""" 234 class MyResponder(MockGDBServerResponder): 235 reg_data = ( 236 "01020304" # eax 237 "11121314" # ecx 238 "21222324" # edx 239 "31323334" # ebx 240 "41424344" # esp 241 "51525354" # ebp 242 "61626364" # esi 243 "71727374" # edi 244 "81828384" # eip 245 "91929394" # eflags 246 "0102030405060708090a" # st0 247 "1112131415161718191a" # st1 248 ) + 6 * ( 249 "2122232425262728292a" # st2..st7 250 ) + ( 251 "8182838485868788898a8b8c8d8e8f90" # xmm0 252 "9192939495969798999a9b9c9d9e9fa0" # xmm1 253 ) + 6 * ( 254 "a1a2a3a4a5a6a7a8a9aaabacadaeafb0" # xmm2..xmm7 255 ) + ( 256 "00000000" # mxcsr 257 ) + ( 258 "b1b2b3b4b5b6b7b8b9babbbcbdbebfc0" # ymm0h 259 "c1c2c3c4c5c6c7c8c9cacbcccdcecfd0" # ymm1h 260 ) + 6 * ( 261 "d1d2d3d4d5d6d7d8d9dadbdcdddedfe0" # ymm2h..ymm7h 262 ) 263 264 def qXferRead(self, obj, annex, offset, length): 265 if annex == "target.xml": 266 return """<?xml version="1.0"?> 267 <!DOCTYPE feature SYSTEM "gdb-target.dtd"> 268 <target> 269 <architecture>i386</architecture> 270 <osabi>GNU/Linux</osabi> 271 <feature name="org.gnu.gdb.i386.core"> 272 <reg name="eax" bitsize="32" type="int32" regnum="0"/> 273 <reg name="ecx" bitsize="32" type="int32" regnum="1"/> 274 <reg name="edx" bitsize="32" type="int32" regnum="2"/> 275 <reg name="ebx" bitsize="32" type="int32" regnum="3"/> 276 <reg name="esp" bitsize="32" type="data_ptr" regnum="4"/> 277 <reg name="ebp" bitsize="32" type="data_ptr" regnum="5"/> 278 <reg name="esi" bitsize="32" type="int32" regnum="6"/> 279 <reg name="edi" bitsize="32" type="int32" regnum="7"/> 280 <reg name="eip" bitsize="32" type="code_ptr" regnum="8"/> 281 <reg name="eflags" bitsize="32" type="i386_eflags" regnum="9"/> 282 <reg name="st0" bitsize="80" type="i387_ext" regnum="16"/> 283 <reg name="st1" bitsize="80" type="i387_ext" regnum="17"/> 284 <reg name="st2" bitsize="80" type="i387_ext" regnum="18"/> 285 <reg name="st3" bitsize="80" type="i387_ext" regnum="19"/> 286 <reg name="st4" bitsize="80" type="i387_ext" regnum="20"/> 287 <reg name="st5" bitsize="80" type="i387_ext" regnum="21"/> 288 <reg name="st6" bitsize="80" type="i387_ext" regnum="22"/> 289 <reg name="st7" bitsize="80" type="i387_ext" regnum="23"/> 290 </feature> 291 <feature name="org.gnu.gdb.i386.sse"> 292 <reg name="xmm0" bitsize="128" type="vec128" regnum="32"/> 293 <reg name="xmm1" bitsize="128" type="vec128" regnum="33"/> 294 <reg name="xmm2" bitsize="128" type="vec128" regnum="34"/> 295 <reg name="xmm3" bitsize="128" type="vec128" regnum="35"/> 296 <reg name="xmm4" bitsize="128" type="vec128" regnum="36"/> 297 <reg name="xmm5" bitsize="128" type="vec128" regnum="37"/> 298 <reg name="xmm6" bitsize="128" type="vec128" regnum="38"/> 299 <reg name="xmm7" bitsize="128" type="vec128" regnum="39"/> 300 <reg name="mxcsr" bitsize="32" type="i386_mxcsr" regnum="40" group="vector"/> 301 </feature> 302 <feature name="org.gnu.gdb.i386.avx"> 303 <reg name="ymm0h" bitsize="128" type="uint128" regnum="42"/> 304 <reg name="ymm1h" bitsize="128" type="uint128" regnum="43"/> 305 <reg name="ymm2h" bitsize="128" type="uint128" regnum="44"/> 306 <reg name="ymm3h" bitsize="128" type="uint128" regnum="45"/> 307 <reg name="ymm4h" bitsize="128" type="uint128" regnum="46"/> 308 <reg name="ymm5h" bitsize="128" type="uint128" regnum="47"/> 309 <reg name="ymm6h" bitsize="128" type="uint128" regnum="48"/> 310 <reg name="ymm7h" bitsize="128" type="uint128" regnum="49"/> 311 </feature> 312 </target>""", False 313 else: 314 return None, False 315 316 def readRegister(self, regnum): 317 return "" 318 319 def readRegisters(self): 320 return self.reg_data 321 322 def writeRegisters(self, reg_hex): 323 self.reg_data = reg_hex 324 return "OK" 325 326 def haltReason(self): 327 return "T02thread:1ff0d;threads:1ff0d;thread-pcs:000000010001bc00;07:0102030405060708;10:1112131415161718;" 328 329 self.server.responder = MyResponder() 330 331 target = self.createTarget("basic_eh_frame-i386.yaml") 332 process = self.connect(target) 333 lldbutil.expect_state_changes(self, self.dbg.GetListener(), process, 334 [lldb.eStateStopped]) 335 336 # test generic aliases 337 self.match("register read fp", 338 ["ebp = 0x54535251"]) 339 self.match("register read sp", 340 ["esp = 0x44434241"]) 341 self.match("register read pc", 342 ["eip = 0x84838281"]) 343 self.match("register read flags", 344 ["eflags = 0x94939291"]) 345 346 # test pseudo-registers 347 self.match("register read cx", 348 ["cx = 0x1211"]) 349 self.match("register read ch", 350 ["ch = 0x12"]) 351 self.match("register read cl", 352 ["cl = 0x11"]) 353 self.match("register read mm0", 354 ["mm0 = 0x0807060504030201"]) 355 self.match("register read mm1", 356 ["mm1 = 0x1817161514131211"]) 357 358 # both stX and xmmX should be displayed as vectors 359 self.match("register read st0", 360 ["st0 = {0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a}"]) 361 self.match("register read st1", 362 ["st1 = {0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a}"]) 363 self.match("register read xmm0", 364 ["xmm0 = {0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 " 365 "0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90}"]) 366 self.match("register read xmm1", 367 ["xmm1 = {0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 " 368 "0x99 0x9a 0x9b 0x9c 0x9d 0x9e 0x9f 0xa0}"]) 369 370 # test writing into pseudo-registers 371 self.runCmd("register write cx 0xfbfa") 372 self.match("register read ecx", 373 ["ecx = 0x1413fbfa"]) 374 375 self.runCmd("register write ch 0xf9") 376 self.match("register read cx", 377 ["cx = 0xf9fa"]) 378 self.match("register read ecx", 379 ["ecx = 0x1413f9fa"]) 380 381 self.runCmd("register write cl 0xf8") 382 self.match("register read cx", 383 ["cx = 0xf9f8"]) 384 self.match("register read ecx", 385 ["ecx = 0x1413f9f8"]) 386 387 self.runCmd("register write mm0 0xfffefdfcfbfaf9f8") 388 self.match("register read st0", 389 ["st0 = {0xf8 0xf9 0xfa 0xfb 0xfc 0xfd 0xfe 0xff 0x09 0x0a}"]) 390 391 self.runCmd("register write xmm0 \"{0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 " 392 "0xf8 0xf7 0xf6 0xf5 0xf4 0xf3 0xf2 0xf1 0xf0}\"") 393 self.match("register read ymm0", 394 ["ymm0 = {0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 0xf8 0xf7 0xf6 " 395 "0xf5 0xf4 0xf3 0xf2 0xf1 0xf0 0xb1 0xb2 0xb3 0xb4 0xb5 " 396 "0xb6 0xb7 0xb8 0xb9 0xba 0xbb 0xbc 0xbd 0xbe 0xbf 0xc0}"]) 397 398 self.runCmd("register write ymm0h \"{0xef 0xee 0xed 0xec 0xeb 0xea 0xe9 " 399 "0xe8 0xe7 0xe6 0xe5 0xe4 0xe3 0xe2 0xe1 0xe0}\"") 400 self.match("register read ymm0", 401 ["ymm0 = {0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 0xf8 0xf7 0xf6 " 402 "0xf5 0xf4 0xf3 0xf2 0xf1 0xf0 0xef 0xee 0xed 0xec 0xeb " 403 "0xea 0xe9 0xe8 0xe7 0xe6 0xe5 0xe4 0xe3 0xe2 0xe1 0xe0}"]) 404 405 self.runCmd("register write ymm0 \"{0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 " 406 "0xd7 0xd8 0xd9 0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 " 407 "0xe2 0xe3 0xe4 0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec " 408 "0xed 0xee 0xef}\"") 409 self.match("register read ymm0", 410 ["ymm0 = {0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 0xd7 0xd8 0xd9 " 411 "0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 0xe2 0xe3 0xe4 " 412 "0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec 0xed 0xee 0xef}"]) 413 414 @skipIfXmlSupportMissing 415 @skipIfRemote 416 @skipIfLLVMTargetMissing("AArch64") 417 def test_aarch64_regs(self): 418 """Test grabbing various aarch64 registers from gdbserver.""" 419 class MyResponder(MockGDBServerResponder): 420 reg_data = ( 421 "0102030405060708" # x0 422 "1112131415161718" # x1 423 ) + 27 * ( 424 "2122232425262728" # x2..x28 425 ) + ( 426 "3132333435363738" # x29 (fp) 427 "4142434445464748" # x30 (lr) 428 "5152535455565758" # x31 (sp) 429 "6162636465666768" # pc 430 "71727374" # cpsr 431 "8182838485868788898a8b8c8d8e8f90" # v0 432 "9192939495969798999a9b9c9d9e9fa0" # v1 433 ) + 30 * ( 434 "a1a2a3a4a5a6a7a8a9aaabacadaeafb0" # v2..v31 435 ) + ( 436 "00000000" # fpsr 437 "00000000" # fpcr 438 ) 439 440 def qXferRead(self, obj, annex, offset, length): 441 if annex == "target.xml": 442 return """<?xml version="1.0"?> 443 <!DOCTYPE feature SYSTEM "gdb-target.dtd"> 444 <target> 445 <architecture>aarch64</architecture> 446 <feature name="org.gnu.gdb.aarch64.core"> 447 <reg name="x0" bitsize="64" type="int" regnum="0"/> 448 <reg name="x1" bitsize="64" type="int" regnum="1"/> 449 <reg name="x2" bitsize="64" type="int" regnum="2"/> 450 <reg name="x3" bitsize="64" type="int" regnum="3"/> 451 <reg name="x4" bitsize="64" type="int" regnum="4"/> 452 <reg name="x5" bitsize="64" type="int" regnum="5"/> 453 <reg name="x6" bitsize="64" type="int" regnum="6"/> 454 <reg name="x7" bitsize="64" type="int" regnum="7"/> 455 <reg name="x8" bitsize="64" type="int" regnum="8"/> 456 <reg name="x9" bitsize="64" type="int" regnum="9"/> 457 <reg name="x10" bitsize="64" type="int" regnum="10"/> 458 <reg name="x11" bitsize="64" type="int" regnum="11"/> 459 <reg name="x12" bitsize="64" type="int" regnum="12"/> 460 <reg name="x13" bitsize="64" type="int" regnum="13"/> 461 <reg name="x14" bitsize="64" type="int" regnum="14"/> 462 <reg name="x15" bitsize="64" type="int" regnum="15"/> 463 <reg name="x16" bitsize="64" type="int" regnum="16"/> 464 <reg name="x17" bitsize="64" type="int" regnum="17"/> 465 <reg name="x18" bitsize="64" type="int" regnum="18"/> 466 <reg name="x19" bitsize="64" type="int" regnum="19"/> 467 <reg name="x20" bitsize="64" type="int" regnum="20"/> 468 <reg name="x21" bitsize="64" type="int" regnum="21"/> 469 <reg name="x22" bitsize="64" type="int" regnum="22"/> 470 <reg name="x23" bitsize="64" type="int" regnum="23"/> 471 <reg name="x24" bitsize="64" type="int" regnum="24"/> 472 <reg name="x25" bitsize="64" type="int" regnum="25"/> 473 <reg name="x26" bitsize="64" type="int" regnum="26"/> 474 <reg name="x27" bitsize="64" type="int" regnum="27"/> 475 <reg name="x28" bitsize="64" type="int" regnum="28"/> 476 <reg name="x29" bitsize="64" type="int" regnum="29"/> 477 <reg name="x30" bitsize="64" type="int" regnum="30"/> 478 <reg name="sp" bitsize="64" type="data_ptr" regnum="31"/> 479 <reg name="pc" bitsize="64" type="code_ptr" regnum="32"/> 480 <reg name="cpsr" bitsize="32" type="cpsr_flags" regnum="33"/> 481 </feature> 482 <feature name="org.gnu.gdb.aarch64.fpu"> 483 <reg name="v0" bitsize="128" type="aarch64v" regnum="34"/> 484 <reg name="v1" bitsize="128" type="aarch64v" regnum="35"/> 485 <reg name="v2" bitsize="128" type="aarch64v" regnum="36"/> 486 <reg name="v3" bitsize="128" type="aarch64v" regnum="37"/> 487 <reg name="v4" bitsize="128" type="aarch64v" regnum="38"/> 488 <reg name="v5" bitsize="128" type="aarch64v" regnum="39"/> 489 <reg name="v6" bitsize="128" type="aarch64v" regnum="40"/> 490 <reg name="v7" bitsize="128" type="aarch64v" regnum="41"/> 491 <reg name="v8" bitsize="128" type="aarch64v" regnum="42"/> 492 <reg name="v9" bitsize="128" type="aarch64v" regnum="43"/> 493 <reg name="v10" bitsize="128" type="aarch64v" regnum="44"/> 494 <reg name="v11" bitsize="128" type="aarch64v" regnum="45"/> 495 <reg name="v12" bitsize="128" type="aarch64v" regnum="46"/> 496 <reg name="v13" bitsize="128" type="aarch64v" regnum="47"/> 497 <reg name="v14" bitsize="128" type="aarch64v" regnum="48"/> 498 <reg name="v15" bitsize="128" type="aarch64v" regnum="49"/> 499 <reg name="v16" bitsize="128" type="aarch64v" regnum="50"/> 500 <reg name="v17" bitsize="128" type="aarch64v" regnum="51"/> 501 <reg name="v18" bitsize="128" type="aarch64v" regnum="52"/> 502 <reg name="v19" bitsize="128" type="aarch64v" regnum="53"/> 503 <reg name="v20" bitsize="128" type="aarch64v" regnum="54"/> 504 <reg name="v21" bitsize="128" type="aarch64v" regnum="55"/> 505 <reg name="v22" bitsize="128" type="aarch64v" regnum="56"/> 506 <reg name="v23" bitsize="128" type="aarch64v" regnum="57"/> 507 <reg name="v24" bitsize="128" type="aarch64v" regnum="58"/> 508 <reg name="v25" bitsize="128" type="aarch64v" regnum="59"/> 509 <reg name="v26" bitsize="128" type="aarch64v" regnum="60"/> 510 <reg name="v27" bitsize="128" type="aarch64v" regnum="61"/> 511 <reg name="v28" bitsize="128" type="aarch64v" regnum="62"/> 512 <reg name="v29" bitsize="128" type="aarch64v" regnum="63"/> 513 <reg name="v30" bitsize="128" type="aarch64v" regnum="64"/> 514 <reg name="v31" bitsize="128" type="aarch64v" regnum="65"/> 515 <reg name="fpsr" bitsize="32" type="int" regnum="66"/> 516 <reg name="fpcr" bitsize="32" type="int" regnum="67"/> 517 </feature> 518 </target>""", False 519 else: 520 return None, False 521 522 def readRegister(self, regnum): 523 return "" 524 525 def readRegisters(self): 526 return self.reg_data 527 528 def writeRegisters(self, reg_hex): 529 self.reg_data = reg_hex 530 return "OK" 531 532 def haltReason(self): 533 return "T02thread:1ff0d;threads:1ff0d;thread-pcs:000000010001bc00;07:0102030405060708;10:1112131415161718;" 534 535 self.server.responder = MyResponder() 536 537 target = self.createTarget("basic_eh_frame-aarch64.yaml") 538 process = self.connect(target) 539 lldbutil.expect_state_changes(self, self.dbg.GetListener(), process, 540 [lldb.eStateStopped]) 541 542 # test GPRs 543 self.match("register read x0", 544 ["x0 = 0x0807060504030201"]) 545 self.match("register read x1", 546 ["x1 = 0x1817161514131211"]) 547 self.match("register read x29", 548 ["x29 = 0x3837363534333231"]) 549 self.match("register read x30", 550 ["x30 = 0x4847464544434241"]) 551 self.match("register read x31", 552 ["sp = 0x5857565554535251"]) 553 self.match("register read sp", 554 ["sp = 0x5857565554535251"]) 555 self.match("register read pc", 556 ["pc = 0x6867666564636261"]) 557 self.match("register read cpsr", 558 ["cpsr = 0x74737271"]) 559 560 # test generic aliases 561 self.match("register read arg1", 562 ["x0 = 0x0807060504030201"]) 563 self.match("register read arg2", 564 ["x1 = 0x1817161514131211"]) 565 self.match("register read fp", 566 ["x29 = 0x3837363534333231"]) 567 self.match("register read lr", 568 ["x30 = 0x4847464544434241"]) 569 self.match("register read ra", 570 ["x30 = 0x4847464544434241"]) 571 self.match("register read flags", 572 ["cpsr = 0x74737271"]) 573 574 # test vector registers 575 self.match("register read v0", 576 ["v0 = {0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90}"]) 577 self.match("register read v31", 578 ["v31 = {0xa1 0xa2 0xa3 0xa4 0xa5 0xa6 0xa7 0xa8 0xa9 0xaa 0xab 0xac 0xad 0xae 0xaf 0xb0}"]) 579 580 # test partial registers 581 self.match("register read w0", 582 ["w0 = 0x04030201"]) 583 self.runCmd("register write w0 0xfffefdfc") 584 self.match("register read x0", 585 ["x0 = 0x08070605fffefdfc"]) 586 587 self.match("register read w1", 588 ["w1 = 0x14131211"]) 589 self.runCmd("register write w1 0xefeeedec") 590 self.match("register read x1", 591 ["x1 = 0x18171615efeeedec"]) 592 593 self.match("register read w30", 594 ["w30 = 0x44434241"]) 595 self.runCmd("register write w30 0xdfdedddc") 596 self.match("register read x30", 597 ["x30 = 0x48474645dfdedddc"]) 598 599 self.match("register read w31", 600 ["w31 = 0x54535251"]) 601 self.runCmd("register write w31 0xcfcecdcc") 602 self.match("register read x31", 603 ["sp = 0x58575655cfcecdcc"]) 604 605 # test FPU registers (overlapping with vector registers) 606 self.runCmd("register write d0 16") 607 self.match("register read v0", 608 ["v0 = {0x00 0x00 0x00 0x00 0x00 0x00 0x30 0x40 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90}"]) 609 self.runCmd("register write v31 '{0x00 0x00 0x00 0x00 0x00 0x00 0x50 0x40 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff}'") 610 self.match("register read d31", 611 ["d31 = 64"]) 612 613 self.runCmd("register write s0 32") 614 self.match("register read v0", 615 ["v0 = {0x00 0x00 0x00 0x42 0x00 0x00 0x30 0x40 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90}"]) 616 self.runCmd("register write v31 '{0x00 0x00 0x00 0x43 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff}'") 617 self.match("register read s31", 618 ["s31 = 128"]) 619 620 @skipIfXmlSupportMissing 621 @skipIfRemote 622 @skipIfLLVMTargetMissing("X86") 623 def test_x86_64_no_duplicate_subregs(self): 624 """Test that duplicate subregisters are not added (on x86_64).""" 625 class MyResponder(MockGDBServerResponder): 626 reg_data = ( 627 "0102030405060708" # rcx 628 "1112131415161718" # rdx 629 "2122232425262728" # rsi 630 "3132333435363738" # rdi 631 "4142434445464748" # rbp 632 "5152535455565758" # rsp 633 "6162636465666768" # r8 634 "7172737475767778" # r9 635 "8182838485868788" # rip 636 "91929394" # eflags 637 ) 638 639 def qXferRead(self, obj, annex, offset, length): 640 if annex == "target.xml": 641 return """<?xml version="1.0"?> 642 <!DOCTYPE feature SYSTEM "gdb-target.dtd"> 643 <target> 644 <architecture>i386:x86-64</architecture> 645 <osabi>GNU/Linux</osabi> 646 <feature name="org.gnu.gdb.i386.core"> 647 <reg name="rcx" bitsize="64" type="int64" regnum="2"/> 648 <reg name="rdx" bitsize="64" type="int64" regnum="3"/> 649 <reg name="rsi" bitsize="64" type="int64" regnum="4"/> 650 <reg name="rdi" bitsize="64" type="int64" regnum="5"/> 651 <reg name="rbp" bitsize="64" type="data_ptr" regnum="6"/> 652 <reg name="rsp" bitsize="64" type="data_ptr" regnum="7"/> 653 <reg name="r8" bitsize="64" type="int64" regnum="8"/> 654 <reg name="r9" bitsize="64" type="int64" regnum="9"/> 655 <reg name="rip" bitsize="64" type="code_ptr" regnum="16"/> 656 <reg name="eflags" bitsize="32" type="i386_eflags" regnum="17"/> 657 <reg name="ecx" bitsize="32" type="int" regnum="18" value_regnums="2"/> 658 </feature> 659 </target>""", False 660 else: 661 return None, False 662 663 def readRegister(self, regnum): 664 return "" 665 666 def readRegisters(self): 667 return self.reg_data 668 669 def haltReason(self): 670 return "T02thread:1ff0d;threads:1ff0d;thread-pcs:000000010001bc00;07:0102030405060708;10:1112131415161718;" 671 672 self.server.responder = MyResponder() 673 674 target = self.createTarget("basic_eh_frame.yaml") 675 process = self.connect(target) 676 lldbutil.expect_state_changes(self, self.dbg.GetListener(), process, 677 [lldb.eStateStopped]) 678 679 self.match("register read rcx", 680 ["rcx = 0x0807060504030201"]) 681 # ecx is supplied via target.xml 682 self.match("register read ecx", 683 ["ecx = 0x04030201"]) 684 self.match("register read rdx", 685 ["rdx = 0x1817161514131211"]) 686 # edx should not be added 687 self.match("register read edx", 688 ["error: Invalid register name 'edx'."], 689 error=True) 690 691 @skipIfXmlSupportMissing 692 @skipIfRemote 693 @skipIfLLVMTargetMissing("X86") 694 def test_i386_no_duplicate_subregs(self): 695 """Test that duplicate subregisters are not added (on i386).""" 696 class MyResponder(MockGDBServerResponder): 697 reg_data = ( 698 "01020304" # eax 699 "11121314" # ecx 700 "21222324" # edx 701 "31323334" # ebx 702 "41424344" # esp 703 "51525354" # ebp 704 "61626364" # esi 705 "71727374" # edi 706 "81828384" # eip 707 "91929394" # eflags 708 ) 709 710 def qXferRead(self, obj, annex, offset, length): 711 if annex == "target.xml": 712 return """<?xml version="1.0"?> 713 <!DOCTYPE feature SYSTEM "gdb-target.dtd"> 714 <target> 715 <architecture>i386</architecture> 716 <osabi>GNU/Linux</osabi> 717 <feature name="org.gnu.gdb.i386.core"> 718 <reg name="eax" bitsize="32" type="int32" regnum="0"/> 719 <reg name="ecx" bitsize="32" type="int32" regnum="1"/> 720 <reg name="edx" bitsize="32" type="int32" regnum="2"/> 721 <reg name="ebx" bitsize="32" type="int32" regnum="3"/> 722 <reg name="esp" bitsize="32" type="data_ptr" regnum="4"/> 723 <reg name="ebp" bitsize="32" type="data_ptr" regnum="5"/> 724 <reg name="esi" bitsize="32" type="int32" regnum="6"/> 725 <reg name="edi" bitsize="32" type="int32" regnum="7"/> 726 <reg name="eip" bitsize="32" type="code_ptr" regnum="8"/> 727 <reg name="eflags" bitsize="32" type="i386_eflags" regnum="9"/> 728 <reg name="ax" bitsize="16" type="int" regnum="10" value_regnums="0"/> 729 </feature> 730 </target>""", False 731 else: 732 return None, False 733 734 def readRegister(self, regnum): 735 return "" 736 737 def readRegisters(self): 738 return self.reg_data 739 740 def haltReason(self): 741 return "T02thread:1ff0d;threads:1ff0d;thread-pcs:000000010001bc00;07:0102030405060708;10:1112131415161718;" 742 743 self.server.responder = MyResponder() 744 745 target = self.createTarget("basic_eh_frame-i386.yaml") 746 process = self.connect(target) 747 lldbutil.expect_state_changes(self, self.dbg.GetListener(), process, 748 [lldb.eStateStopped]) 749 750 self.match("register read eax", 751 ["eax = 0x04030201"]) 752 # cx is supplied via target.xml 753 self.match("register read ax", 754 ["ax = 0x0201"]) 755 self.match("register read ecx", 756 ["ecx = 0x14131211"]) 757 # dx should not be added 758 self.match("register read cx", 759 ["error: Invalid register name 'cx'."], 760 error=True) 761 762 @skipIfXmlSupportMissing 763 @skipIfRemote 764 @skipIfLLVMTargetMissing("AArch64") 765 def test_aarch64_no_duplicate_subregs(self): 766 """Test that duplicate subregisters are not added.""" 767 class MyResponder(MockGDBServerResponder): 768 reg_data = ( 769 "0102030405060708" # x0 770 "1112131415161718" # x1 771 ) + 27 * ( 772 "2122232425262728" # x2..x28 773 ) + ( 774 "3132333435363738" # x29 (fp) 775 "4142434445464748" # x30 (lr) 776 "5152535455565758" # x31 (sp) 777 "6162636465666768" # pc 778 "71727374" # cpsr 779 ) 780 781 def qXferRead(self, obj, annex, offset, length): 782 if annex == "target.xml": 783 return """<?xml version="1.0"?> 784 <!DOCTYPE feature SYSTEM "gdb-target.dtd"> 785 <target> 786 <architecture>aarch64</architecture> 787 <feature name="org.gnu.gdb.aarch64.core"> 788 <reg name="x0" bitsize="64" type="int" regnum="0"/> 789 <reg name="x1" bitsize="64" type="int" regnum="1"/> 790 <reg name="x2" bitsize="64" type="int" regnum="2"/> 791 <reg name="x3" bitsize="64" type="int" regnum="3"/> 792 <reg name="x4" bitsize="64" type="int" regnum="4"/> 793 <reg name="x5" bitsize="64" type="int" regnum="5"/> 794 <reg name="x6" bitsize="64" type="int" regnum="6"/> 795 <reg name="x7" bitsize="64" type="int" regnum="7"/> 796 <reg name="x8" bitsize="64" type="int" regnum="8"/> 797 <reg name="x9" bitsize="64" type="int" regnum="9"/> 798 <reg name="x10" bitsize="64" type="int" regnum="10"/> 799 <reg name="x11" bitsize="64" type="int" regnum="11"/> 800 <reg name="x12" bitsize="64" type="int" regnum="12"/> 801 <reg name="x13" bitsize="64" type="int" regnum="13"/> 802 <reg name="x14" bitsize="64" type="int" regnum="14"/> 803 <reg name="x15" bitsize="64" type="int" regnum="15"/> 804 <reg name="x16" bitsize="64" type="int" regnum="16"/> 805 <reg name="x17" bitsize="64" type="int" regnum="17"/> 806 <reg name="x18" bitsize="64" type="int" regnum="18"/> 807 <reg name="x19" bitsize="64" type="int" regnum="19"/> 808 <reg name="x20" bitsize="64" type="int" regnum="20"/> 809 <reg name="x21" bitsize="64" type="int" regnum="21"/> 810 <reg name="x22" bitsize="64" type="int" regnum="22"/> 811 <reg name="x23" bitsize="64" type="int" regnum="23"/> 812 <reg name="x24" bitsize="64" type="int" regnum="24"/> 813 <reg name="x25" bitsize="64" type="int" regnum="25"/> 814 <reg name="x26" bitsize="64" type="int" regnum="26"/> 815 <reg name="x27" bitsize="64" type="int" regnum="27"/> 816 <reg name="x28" bitsize="64" type="int" regnum="28"/> 817 <reg name="x29" bitsize="64" type="int" regnum="29"/> 818 <reg name="x30" bitsize="64" type="int" regnum="30"/> 819 <reg name="sp" bitsize="64" type="data_ptr" regnum="31"/> 820 <reg name="pc" bitsize="64" type="code_ptr" regnum="32"/> 821 <reg name="cpsr" bitsize="32" type="cpsr_flags" regnum="33"/> 822 <reg name="w0" bitsize="32" type="int" regnum="34" value_regnums="0"/> 823 </feature> 824 </target>""", False 825 else: 826 return None, False 827 828 def readRegister(self, regnum): 829 return "" 830 831 def readRegisters(self): 832 return self.reg_data 833 834 def haltReason(self): 835 return "T02thread:1ff0d;threads:1ff0d;thread-pcs:000000010001bc00;07:0102030405060708;10:1112131415161718;" 836 837 self.server.responder = MyResponder() 838 839 target = self.createTarget("basic_eh_frame-aarch64.yaml") 840 process = self.connect(target) 841 lldbutil.expect_state_changes(self, self.dbg.GetListener(), process, 842 [lldb.eStateStopped]) 843 844 self.match("register read x0", 845 ["x0 = 0x0807060504030201"]) 846 # w0 comes from target.xml 847 self.match("register read w0", 848 ["w0 = 0x04030201"]) 849 self.match("register read x1", 850 ["x1 = 0x1817161514131211"]) 851 # w1 should not be added 852 self.match("register read w1", 853 ["error: Invalid register name 'w1'."], 854 error=True) 855