1import lldb 2from lldbsuite.test.lldbtest import * 3from lldbsuite.test.decorators import * 4from lldbsuite.test.gdbclientutils import * 5from lldbsuite.test.lldbgdbclient import GDBRemoteTestBase 6 7 8class TestGDBServerTargetXML(GDBRemoteTestBase): 9 10 @skipIfXmlSupportMissing 11 @skipIfRemote 12 @skipIfLLVMTargetMissing("X86") 13 def test_x86_64_regs(self): 14 """Test grabbing various x86_64 registers from gdbserver.""" 15 class MyResponder(MockGDBServerResponder): 16 reg_data = ( 17 "0102030405060708" # rcx 18 "1112131415161718" # rdx 19 "2122232425262728" # rsi 20 "3132333435363738" # rdi 21 "4142434445464748" # rbp 22 "5152535455565758" # rsp 23 "6162636465666768" # r8 24 "7172737475767778" # r9 25 "8182838485868788" # rip 26 "91929394" # eflags 27 "0102030405060708090a" # st0 28 "1112131415161718191a" # st1 29 ) + 6 * ( 30 "2122232425262728292a" # st2..st7 31 ) + ( 32 "8182838485868788898a8b8c8d8e8f90" # xmm0 33 "9192939495969798999a9b9c9d9e9fa0" # xmm1 34 ) + 14 * ( 35 "a1a2a3a4a5a6a7a8a9aaabacadaeafb0" # xmm2..xmm15 36 ) + ( 37 "00000000" # mxcsr 38 ) + ( 39 "b1b2b3b4b5b6b7b8b9babbbcbdbebfc0" # ymm0h 40 "c1c2c3c4c5c6c7c8c9cacbcccdcecfd0" # ymm1h 41 ) + 14 * ( 42 "d1d2d3d4d5d6d7d8d9dadbdcdddedfe0" # ymm2h..ymm15h 43 ) 44 45 def qXferRead(self, obj, annex, offset, length): 46 if annex == "target.xml": 47 return """<?xml version="1.0"?> 48 <!DOCTYPE feature SYSTEM "gdb-target.dtd"> 49 <target> 50 <architecture>i386:x86-64</architecture> 51 <osabi>GNU/Linux</osabi> 52 <feature name="org.gnu.gdb.i386.core"> 53 <reg name="rcx" bitsize="64" type="int64" regnum="2"/> 54 <reg name="rdx" bitsize="64" type="int64" regnum="3"/> 55 <reg name="rsi" bitsize="64" type="int64" regnum="4"/> 56 <reg name="rdi" bitsize="64" type="int64" regnum="5"/> 57 <reg name="rbp" bitsize="64" type="data_ptr" regnum="6"/> 58 <reg name="rsp" bitsize="64" type="data_ptr" regnum="7"/> 59 <reg name="r8" bitsize="64" type="int64" regnum="8"/> 60 <reg name="r9" bitsize="64" type="int64" regnum="9"/> 61 <reg name="rip" bitsize="64" type="code_ptr" regnum="16"/> 62 <reg name="eflags" bitsize="32" type="i386_eflags" regnum="17"/> 63 <reg name="st0" bitsize="80" type="i387_ext" regnum="24"/> 64 <reg name="st1" bitsize="80" type="i387_ext" regnum="25"/> 65 <reg name="st2" bitsize="80" type="i387_ext" regnum="26"/> 66 <reg name="st3" bitsize="80" type="i387_ext" regnum="27"/> 67 <reg name="st4" bitsize="80" type="i387_ext" regnum="28"/> 68 <reg name="st5" bitsize="80" type="i387_ext" regnum="29"/> 69 <reg name="st6" bitsize="80" type="i387_ext" regnum="30"/> 70 <reg name="st7" bitsize="80" type="i387_ext" regnum="31"/> 71 </feature> 72 <feature name="org.gnu.gdb.i386.sse"> 73 <reg name="xmm0" bitsize="128" type="vec128" regnum="40"/> 74 <reg name="xmm1" bitsize="128" type="vec128" regnum="41"/> 75 <reg name="xmm2" bitsize="128" type="vec128" regnum="42"/> 76 <reg name="xmm3" bitsize="128" type="vec128" regnum="43"/> 77 <reg name="xmm4" bitsize="128" type="vec128" regnum="44"/> 78 <reg name="xmm5" bitsize="128" type="vec128" regnum="45"/> 79 <reg name="xmm6" bitsize="128" type="vec128" regnum="46"/> 80 <reg name="xmm7" bitsize="128" type="vec128" regnum="47"/> 81 <reg name="xmm8" bitsize="128" type="vec128" regnum="48"/> 82 <reg name="xmm9" bitsize="128" type="vec128" regnum="49"/> 83 <reg name="xmm10" bitsize="128" type="vec128" regnum="50"/> 84 <reg name="xmm11" bitsize="128" type="vec128" regnum="51"/> 85 <reg name="xmm12" bitsize="128" type="vec128" regnum="52"/> 86 <reg name="xmm13" bitsize="128" type="vec128" regnum="53"/> 87 <reg name="xmm14" bitsize="128" type="vec128" regnum="54"/> 88 <reg name="xmm15" bitsize="128" type="vec128" regnum="55"/> 89 <reg name="mxcsr" bitsize="32" type="i386_mxcsr" regnum="56" group="vector"/> 90 </feature> 91 <feature name="org.gnu.gdb.i386.avx"> 92 <reg name="ymm0h" bitsize="128" type="uint128" regnum="60"/> 93 <reg name="ymm1h" bitsize="128" type="uint128" regnum="61"/> 94 <reg name="ymm2h" bitsize="128" type="uint128" regnum="62"/> 95 <reg name="ymm3h" bitsize="128" type="uint128" regnum="63"/> 96 <reg name="ymm4h" bitsize="128" type="uint128" regnum="64"/> 97 <reg name="ymm5h" bitsize="128" type="uint128" regnum="65"/> 98 <reg name="ymm6h" bitsize="128" type="uint128" regnum="66"/> 99 <reg name="ymm7h" bitsize="128" type="uint128" regnum="67"/> 100 <reg name="ymm8h" bitsize="128" type="uint128" regnum="68"/> 101 <reg name="ymm9h" bitsize="128" type="uint128" regnum="69"/> 102 <reg name="ymm10h" bitsize="128" type="uint128" regnum="70"/> 103 <reg name="ymm11h" bitsize="128" type="uint128" regnum="71"/> 104 <reg name="ymm12h" bitsize="128" type="uint128" regnum="72"/> 105 <reg name="ymm13h" bitsize="128" type="uint128" regnum="73"/> 106 <reg name="ymm14h" bitsize="128" type="uint128" regnum="74"/> 107 <reg name="ymm15h" bitsize="128" type="uint128" regnum="75"/> 108 </feature> 109 </target>""", False 110 else: 111 return None, False 112 113 def readRegister(self, regnum): 114 return "" 115 116 def readRegisters(self): 117 return self.reg_data 118 119 def writeRegisters(self, reg_hex): 120 self.reg_data = reg_hex 121 return "OK" 122 123 def haltReason(self): 124 return "T02thread:1ff0d;threads:1ff0d;thread-pcs:000000010001bc00;07:0102030405060708;10:1112131415161718;" 125 126 self.server.responder = MyResponder() 127 128 target = self.createTarget("basic_eh_frame.yaml") 129 process = self.connect(target) 130 lldbutil.expect_state_changes(self, self.dbg.GetListener(), process, 131 [lldb.eStateStopped]) 132 133 # test generic aliases 134 self.match("register read arg4", 135 ["rcx = 0x0807060504030201"]) 136 self.match("register read arg3", 137 ["rdx = 0x1817161514131211"]) 138 self.match("register read arg2", 139 ["rsi = 0x2827262524232221"]) 140 self.match("register read arg1", 141 ["rdi = 0x3837363534333231"]) 142 self.match("register read fp", 143 ["rbp = 0x4847464544434241"]) 144 self.match("register read sp", 145 ["rsp = 0x5857565554535251"]) 146 self.match("register read arg5", 147 ["r8 = 0x6867666564636261"]) 148 self.match("register read arg6", 149 ["r9 = 0x7877767574737271"]) 150 self.match("register read pc", 151 ["rip = 0x8887868584838281"]) 152 self.match("register read flags", 153 ["eflags = 0x94939291"]) 154 155 # both stX and xmmX should be displayed as vectors 156 self.match("register read st0", 157 ["st0 = {0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a}"]) 158 self.match("register read st1", 159 ["st1 = {0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a}"]) 160 self.match("register read xmm0", 161 ["xmm0 = {0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 " 162 "0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90}"]) 163 self.match("register read xmm1", 164 ["xmm1 = {0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 " 165 "0x99 0x9a 0x9b 0x9c 0x9d 0x9e 0x9f 0xa0}"]) 166 167 # test pseudo-registers 168 self.filecheck("register read --all", 169 os.path.join(os.path.dirname(__file__), 170 "amd64-partial-regs.FileCheck")) 171 172 # test writing into pseudo-registers 173 self.runCmd("register write ecx 0xfffefdfc") 174 self.match("register read rcx", 175 ["rcx = 0x08070605fffefdfc"]) 176 177 self.runCmd("register write cx 0xfbfa") 178 self.match("register read ecx", 179 ["ecx = 0xfffefbfa"]) 180 self.match("register read rcx", 181 ["rcx = 0x08070605fffefbfa"]) 182 183 self.runCmd("register write ch 0xf9") 184 self.match("register read cx", 185 ["cx = 0xf9fa"]) 186 self.match("register read ecx", 187 ["ecx = 0xfffef9fa"]) 188 self.match("register read rcx", 189 ["rcx = 0x08070605fffef9fa"]) 190 191 self.runCmd("register write cl 0xf8") 192 self.match("register read cx", 193 ["cx = 0xf9f8"]) 194 self.match("register read ecx", 195 ["ecx = 0xfffef9f8"]) 196 self.match("register read rcx", 197 ["rcx = 0x08070605fffef9f8"]) 198 199 self.runCmd("register write mm0 0xfffefdfcfbfaf9f8") 200 self.match("register read st0", 201 ["st0 = {0xf8 0xf9 0xfa 0xfb 0xfc 0xfd 0xfe 0xff 0x09 0x0a}"]) 202 203 self.runCmd("register write xmm0 \"{0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 " 204 "0xf8 0xf7 0xf6 0xf5 0xf4 0xf3 0xf2 0xf1 0xf0}\"") 205 self.match("register read ymm0", 206 ["ymm0 = {0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 0xf8 0xf7 0xf6 " 207 "0xf5 0xf4 0xf3 0xf2 0xf1 0xf0 0xb1 0xb2 0xb3 0xb4 0xb5 " 208 "0xb6 0xb7 0xb8 0xb9 0xba 0xbb 0xbc 0xbd 0xbe 0xbf 0xc0}"]) 209 210 self.runCmd("register write ymm0h \"{0xef 0xee 0xed 0xec 0xeb 0xea 0xe9 " 211 "0xe8 0xe7 0xe6 0xe5 0xe4 0xe3 0xe2 0xe1 0xe0}\"") 212 self.match("register read ymm0", 213 ["ymm0 = {0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 0xf8 0xf7 0xf6 " 214 "0xf5 0xf4 0xf3 0xf2 0xf1 0xf0 0xef 0xee 0xed 0xec 0xeb " 215 "0xea 0xe9 0xe8 0xe7 0xe6 0xe5 0xe4 0xe3 0xe2 0xe1 0xe0}"]) 216 217 self.runCmd("register write ymm0 \"{0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 " 218 "0xd7 0xd8 0xd9 0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 " 219 "0xe2 0xe3 0xe4 0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec " 220 "0xed 0xee 0xef}\"") 221 self.match("register read ymm0", 222 ["ymm0 = {0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 0xd7 0xd8 0xd9 " 223 "0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 0xe2 0xe3 0xe4 " 224 "0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec 0xed 0xee 0xef}"]) 225 226 @skipIfXmlSupportMissing 227 @skipIfRemote 228 @skipIfLLVMTargetMissing("X86") 229 def test_i386_regs(self): 230 """Test grabbing various i386 registers from gdbserver.""" 231 class MyResponder(MockGDBServerResponder): 232 reg_data = ( 233 "01020304" # eax 234 "11121314" # ecx 235 "21222324" # edx 236 "31323334" # ebx 237 "41424344" # esp 238 "51525354" # ebp 239 "61626364" # esi 240 "71727374" # edi 241 "81828384" # eip 242 "91929394" # eflags 243 "0102030405060708090a" # st0 244 "1112131415161718191a" # st1 245 ) + 6 * ( 246 "2122232425262728292a" # st2..st7 247 ) + ( 248 "8182838485868788898a8b8c8d8e8f90" # xmm0 249 "9192939495969798999a9b9c9d9e9fa0" # xmm1 250 ) + 6 * ( 251 "a1a2a3a4a5a6a7a8a9aaabacadaeafb0" # xmm2..xmm7 252 ) + ( 253 "00000000" # mxcsr 254 ) + ( 255 "b1b2b3b4b5b6b7b8b9babbbcbdbebfc0" # ymm0h 256 "c1c2c3c4c5c6c7c8c9cacbcccdcecfd0" # ymm1h 257 ) + 6 * ( 258 "d1d2d3d4d5d6d7d8d9dadbdcdddedfe0" # ymm2h..ymm7h 259 ) 260 261 def qXferRead(self, obj, annex, offset, length): 262 if annex == "target.xml": 263 return """<?xml version="1.0"?> 264 <!DOCTYPE feature SYSTEM "gdb-target.dtd"> 265 <target> 266 <architecture>i386</architecture> 267 <osabi>GNU/Linux</osabi> 268 <feature name="org.gnu.gdb.i386.core"> 269 <reg name="eax" bitsize="32" type="int32" regnum="0"/> 270 <reg name="ecx" bitsize="32" type="int32" regnum="1"/> 271 <reg name="edx" bitsize="32" type="int32" regnum="2"/> 272 <reg name="ebx" bitsize="32" type="int32" regnum="3"/> 273 <reg name="esp" bitsize="32" type="data_ptr" regnum="4"/> 274 <reg name="ebp" bitsize="32" type="data_ptr" regnum="5"/> 275 <reg name="esi" bitsize="32" type="int32" regnum="6"/> 276 <reg name="edi" bitsize="32" type="int32" regnum="7"/> 277 <reg name="eip" bitsize="32" type="code_ptr" regnum="8"/> 278 <reg name="eflags" bitsize="32" type="i386_eflags" regnum="9"/> 279 <reg name="st0" bitsize="80" type="i387_ext" regnum="16"/> 280 <reg name="st1" bitsize="80" type="i387_ext" regnum="17"/> 281 <reg name="st2" bitsize="80" type="i387_ext" regnum="18"/> 282 <reg name="st3" bitsize="80" type="i387_ext" regnum="19"/> 283 <reg name="st4" bitsize="80" type="i387_ext" regnum="20"/> 284 <reg name="st5" bitsize="80" type="i387_ext" regnum="21"/> 285 <reg name="st6" bitsize="80" type="i387_ext" regnum="22"/> 286 <reg name="st7" bitsize="80" type="i387_ext" regnum="23"/> 287 </feature> 288 <feature name="org.gnu.gdb.i386.sse"> 289 <reg name="xmm0" bitsize="128" type="vec128" regnum="32"/> 290 <reg name="xmm1" bitsize="128" type="vec128" regnum="33"/> 291 <reg name="xmm2" bitsize="128" type="vec128" regnum="34"/> 292 <reg name="xmm3" bitsize="128" type="vec128" regnum="35"/> 293 <reg name="xmm4" bitsize="128" type="vec128" regnum="36"/> 294 <reg name="xmm5" bitsize="128" type="vec128" regnum="37"/> 295 <reg name="xmm6" bitsize="128" type="vec128" regnum="38"/> 296 <reg name="xmm7" bitsize="128" type="vec128" regnum="39"/> 297 <reg name="mxcsr" bitsize="32" type="i386_mxcsr" regnum="40" group="vector"/> 298 </feature> 299 <feature name="org.gnu.gdb.i386.avx"> 300 <reg name="ymm0h" bitsize="128" type="uint128" regnum="42"/> 301 <reg name="ymm1h" bitsize="128" type="uint128" regnum="43"/> 302 <reg name="ymm2h" bitsize="128" type="uint128" regnum="44"/> 303 <reg name="ymm3h" bitsize="128" type="uint128" regnum="45"/> 304 <reg name="ymm4h" bitsize="128" type="uint128" regnum="46"/> 305 <reg name="ymm5h" bitsize="128" type="uint128" regnum="47"/> 306 <reg name="ymm6h" bitsize="128" type="uint128" regnum="48"/> 307 <reg name="ymm7h" bitsize="128" type="uint128" regnum="49"/> 308 </feature> 309 </target>""", False 310 else: 311 return None, False 312 313 def readRegister(self, regnum): 314 return "" 315 316 def readRegisters(self): 317 return self.reg_data 318 319 def writeRegisters(self, reg_hex): 320 self.reg_data = reg_hex 321 return "OK" 322 323 def haltReason(self): 324 return "T02thread:1ff0d;threads:1ff0d;thread-pcs:000000010001bc00;07:0102030405060708;10:1112131415161718;" 325 326 self.server.responder = MyResponder() 327 328 target = self.createTarget("basic_eh_frame-i386.yaml") 329 process = self.connect(target) 330 lldbutil.expect_state_changes(self, self.dbg.GetListener(), process, 331 [lldb.eStateStopped]) 332 333 # test generic aliases 334 self.match("register read fp", 335 ["ebp = 0x54535251"]) 336 self.match("register read sp", 337 ["esp = 0x44434241"]) 338 self.match("register read pc", 339 ["eip = 0x84838281"]) 340 self.match("register read flags", 341 ["eflags = 0x94939291"]) 342 343 # test pseudo-registers 344 self.match("register read cx", 345 ["cx = 0x1211"]) 346 self.match("register read ch", 347 ["ch = 0x12"]) 348 self.match("register read cl", 349 ["cl = 0x11"]) 350 self.match("register read mm0", 351 ["mm0 = 0x0807060504030201"]) 352 self.match("register read mm1", 353 ["mm1 = 0x1817161514131211"]) 354 355 # both stX and xmmX should be displayed as vectors 356 self.match("register read st0", 357 ["st0 = {0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a}"]) 358 self.match("register read st1", 359 ["st1 = {0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a}"]) 360 self.match("register read xmm0", 361 ["xmm0 = {0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 " 362 "0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90}"]) 363 self.match("register read xmm1", 364 ["xmm1 = {0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 " 365 "0x99 0x9a 0x9b 0x9c 0x9d 0x9e 0x9f 0xa0}"]) 366 367 # test writing into pseudo-registers 368 self.runCmd("register write cx 0xfbfa") 369 self.match("register read ecx", 370 ["ecx = 0x1413fbfa"]) 371 372 self.runCmd("register write ch 0xf9") 373 self.match("register read cx", 374 ["cx = 0xf9fa"]) 375 self.match("register read ecx", 376 ["ecx = 0x1413f9fa"]) 377 378 self.runCmd("register write cl 0xf8") 379 self.match("register read cx", 380 ["cx = 0xf9f8"]) 381 self.match("register read ecx", 382 ["ecx = 0x1413f9f8"]) 383 384 self.runCmd("register write mm0 0xfffefdfcfbfaf9f8") 385 self.match("register read st0", 386 ["st0 = {0xf8 0xf9 0xfa 0xfb 0xfc 0xfd 0xfe 0xff 0x09 0x0a}"]) 387 388 self.runCmd("register write xmm0 \"{0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 " 389 "0xf8 0xf7 0xf6 0xf5 0xf4 0xf3 0xf2 0xf1 0xf0}\"") 390 self.match("register read ymm0", 391 ["ymm0 = {0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 0xf8 0xf7 0xf6 " 392 "0xf5 0xf4 0xf3 0xf2 0xf1 0xf0 0xb1 0xb2 0xb3 0xb4 0xb5 " 393 "0xb6 0xb7 0xb8 0xb9 0xba 0xbb 0xbc 0xbd 0xbe 0xbf 0xc0}"]) 394 395 self.runCmd("register write ymm0h \"{0xef 0xee 0xed 0xec 0xeb 0xea 0xe9 " 396 "0xe8 0xe7 0xe6 0xe5 0xe4 0xe3 0xe2 0xe1 0xe0}\"") 397 self.match("register read ymm0", 398 ["ymm0 = {0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 0xf8 0xf7 0xf6 " 399 "0xf5 0xf4 0xf3 0xf2 0xf1 0xf0 0xef 0xee 0xed 0xec 0xeb " 400 "0xea 0xe9 0xe8 0xe7 0xe6 0xe5 0xe4 0xe3 0xe2 0xe1 0xe0}"]) 401 402 self.runCmd("register write ymm0 \"{0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 " 403 "0xd7 0xd8 0xd9 0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 " 404 "0xe2 0xe3 0xe4 0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec " 405 "0xed 0xee 0xef}\"") 406 self.match("register read ymm0", 407 ["ymm0 = {0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 0xd7 0xd8 0xd9 " 408 "0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 0xe2 0xe3 0xe4 " 409 "0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec 0xed 0xee 0xef}"]) 410 411 @skipIfXmlSupportMissing 412 @skipIfRemote 413 @skipIfLLVMTargetMissing("AArch64") 414 def test_aarch64_regs(self): 415 """Test grabbing various aarch64 registers from gdbserver.""" 416 class MyResponder(MockGDBServerResponder): 417 reg_data = ( 418 "0102030405060708" # x0 419 "1112131415161718" # x1 420 ) + 27 * ( 421 "2122232425262728" # x2..x28 422 ) + ( 423 "3132333435363738" # x29 (fp) 424 "4142434445464748" # x30 (lr) 425 "5152535455565758" # x31 (sp) 426 "6162636465666768" # pc 427 "71727374" # cpsr 428 "8182838485868788898a8b8c8d8e8f90" # v0 429 "9192939495969798999a9b9c9d9e9fa0" # v1 430 ) + 30 * ( 431 "a1a2a3a4a5a6a7a8a9aaabacadaeafb0" # v2..v31 432 ) + ( 433 "00000000" # fpsr 434 "00000000" # fpcr 435 ) 436 437 def qXferRead(self, obj, annex, offset, length): 438 if annex == "target.xml": 439 return """<?xml version="1.0"?> 440 <!DOCTYPE feature SYSTEM "gdb-target.dtd"> 441 <target> 442 <architecture>aarch64</architecture> 443 <feature name="org.gnu.gdb.aarch64.core"> 444 <reg name="x0" bitsize="64" type="int" regnum="0"/> 445 <reg name="x1" bitsize="64" type="int" regnum="1"/> 446 <reg name="x2" bitsize="64" type="int" regnum="2"/> 447 <reg name="x3" bitsize="64" type="int" regnum="3"/> 448 <reg name="x4" bitsize="64" type="int" regnum="4"/> 449 <reg name="x5" bitsize="64" type="int" regnum="5"/> 450 <reg name="x6" bitsize="64" type="int" regnum="6"/> 451 <reg name="x7" bitsize="64" type="int" regnum="7"/> 452 <reg name="x8" bitsize="64" type="int" regnum="8"/> 453 <reg name="x9" bitsize="64" type="int" regnum="9"/> 454 <reg name="x10" bitsize="64" type="int" regnum="10"/> 455 <reg name="x11" bitsize="64" type="int" regnum="11"/> 456 <reg name="x12" bitsize="64" type="int" regnum="12"/> 457 <reg name="x13" bitsize="64" type="int" regnum="13"/> 458 <reg name="x14" bitsize="64" type="int" regnum="14"/> 459 <reg name="x15" bitsize="64" type="int" regnum="15"/> 460 <reg name="x16" bitsize="64" type="int" regnum="16"/> 461 <reg name="x17" bitsize="64" type="int" regnum="17"/> 462 <reg name="x18" bitsize="64" type="int" regnum="18"/> 463 <reg name="x19" bitsize="64" type="int" regnum="19"/> 464 <reg name="x20" bitsize="64" type="int" regnum="20"/> 465 <reg name="x21" bitsize="64" type="int" regnum="21"/> 466 <reg name="x22" bitsize="64" type="int" regnum="22"/> 467 <reg name="x23" bitsize="64" type="int" regnum="23"/> 468 <reg name="x24" bitsize="64" type="int" regnum="24"/> 469 <reg name="x25" bitsize="64" type="int" regnum="25"/> 470 <reg name="x26" bitsize="64" type="int" regnum="26"/> 471 <reg name="x27" bitsize="64" type="int" regnum="27"/> 472 <reg name="x28" bitsize="64" type="int" regnum="28"/> 473 <reg name="x29" bitsize="64" type="int" regnum="29"/> 474 <reg name="x30" bitsize="64" type="int" regnum="30"/> 475 <reg name="sp" bitsize="64" type="data_ptr" regnum="31"/> 476 <reg name="pc" bitsize="64" type="code_ptr" regnum="32"/> 477 <reg name="cpsr" bitsize="32" type="cpsr_flags" regnum="33"/> 478 </feature> 479 <feature name="org.gnu.gdb.aarch64.fpu"> 480 <reg name="v0" bitsize="128" type="aarch64v" regnum="34"/> 481 <reg name="v1" bitsize="128" type="aarch64v" regnum="35"/> 482 <reg name="v2" bitsize="128" type="aarch64v" regnum="36"/> 483 <reg name="v3" bitsize="128" type="aarch64v" regnum="37"/> 484 <reg name="v4" bitsize="128" type="aarch64v" regnum="38"/> 485 <reg name="v5" bitsize="128" type="aarch64v" regnum="39"/> 486 <reg name="v6" bitsize="128" type="aarch64v" regnum="40"/> 487 <reg name="v7" bitsize="128" type="aarch64v" regnum="41"/> 488 <reg name="v8" bitsize="128" type="aarch64v" regnum="42"/> 489 <reg name="v9" bitsize="128" type="aarch64v" regnum="43"/> 490 <reg name="v10" bitsize="128" type="aarch64v" regnum="44"/> 491 <reg name="v11" bitsize="128" type="aarch64v" regnum="45"/> 492 <reg name="v12" bitsize="128" type="aarch64v" regnum="46"/> 493 <reg name="v13" bitsize="128" type="aarch64v" regnum="47"/> 494 <reg name="v14" bitsize="128" type="aarch64v" regnum="48"/> 495 <reg name="v15" bitsize="128" type="aarch64v" regnum="49"/> 496 <reg name="v16" bitsize="128" type="aarch64v" regnum="50"/> 497 <reg name="v17" bitsize="128" type="aarch64v" regnum="51"/> 498 <reg name="v18" bitsize="128" type="aarch64v" regnum="52"/> 499 <reg name="v19" bitsize="128" type="aarch64v" regnum="53"/> 500 <reg name="v20" bitsize="128" type="aarch64v" regnum="54"/> 501 <reg name="v21" bitsize="128" type="aarch64v" regnum="55"/> 502 <reg name="v22" bitsize="128" type="aarch64v" regnum="56"/> 503 <reg name="v23" bitsize="128" type="aarch64v" regnum="57"/> 504 <reg name="v24" bitsize="128" type="aarch64v" regnum="58"/> 505 <reg name="v25" bitsize="128" type="aarch64v" regnum="59"/> 506 <reg name="v26" bitsize="128" type="aarch64v" regnum="60"/> 507 <reg name="v27" bitsize="128" type="aarch64v" regnum="61"/> 508 <reg name="v28" bitsize="128" type="aarch64v" regnum="62"/> 509 <reg name="v29" bitsize="128" type="aarch64v" regnum="63"/> 510 <reg name="v30" bitsize="128" type="aarch64v" regnum="64"/> 511 <reg name="v31" bitsize="128" type="aarch64v" regnum="65"/> 512 <reg name="fpsr" bitsize="32" type="int" regnum="66"/> 513 <reg name="fpcr" bitsize="32" type="int" regnum="67"/> 514 </feature> 515 </target>""", False 516 else: 517 return None, False 518 519 def readRegister(self, regnum): 520 return "" 521 522 def readRegisters(self): 523 return self.reg_data 524 525 def writeRegisters(self, reg_hex): 526 self.reg_data = reg_hex 527 return "OK" 528 529 def haltReason(self): 530 return "T02thread:1ff0d;threads:1ff0d;thread-pcs:000000010001bc00;07:0102030405060708;10:1112131415161718;" 531 532 self.server.responder = MyResponder() 533 534 target = self.createTarget("basic_eh_frame-aarch64.yaml") 535 process = self.connect(target) 536 lldbutil.expect_state_changes(self, self.dbg.GetListener(), process, 537 [lldb.eStateStopped]) 538 539 # test GPRs 540 self.match("register read x0", 541 ["x0 = 0x0807060504030201"]) 542 self.match("register read x1", 543 ["x1 = 0x1817161514131211"]) 544 self.match("register read x29", 545 ["x29 = 0x3837363534333231"]) 546 self.match("register read x30", 547 ["x30 = 0x4847464544434241"]) 548 self.match("register read x31", 549 ["sp = 0x5857565554535251"]) 550 self.match("register read sp", 551 ["sp = 0x5857565554535251"]) 552 self.match("register read pc", 553 ["pc = 0x6867666564636261"]) 554 self.match("register read cpsr", 555 ["cpsr = 0x74737271"]) 556 557 # test generic aliases 558 self.match("register read arg1", 559 ["x0 = 0x0807060504030201"]) 560 self.match("register read arg2", 561 ["x1 = 0x1817161514131211"]) 562 self.match("register read fp", 563 ["x29 = 0x3837363534333231"]) 564 self.match("register read lr", 565 ["x30 = 0x4847464544434241"]) 566 self.match("register read ra", 567 ["x30 = 0x4847464544434241"]) 568 self.match("register read flags", 569 ["cpsr = 0x74737271"]) 570 571 # test vector registers 572 self.match("register read v0", 573 ["v0 = {0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90}"]) 574 self.match("register read v31", 575 ["v31 = {0xa1 0xa2 0xa3 0xa4 0xa5 0xa6 0xa7 0xa8 0xa9 0xaa 0xab 0xac 0xad 0xae 0xaf 0xb0}"]) 576 577 # test partial registers 578 self.match("register read w0", 579 ["w0 = 0x04030201"]) 580 self.runCmd("register write w0 0xfffefdfc") 581 self.match("register read x0", 582 ["x0 = 0x08070605fffefdfc"]) 583 584 self.match("register read w1", 585 ["w1 = 0x14131211"]) 586 self.runCmd("register write w1 0xefeeedec") 587 self.match("register read x1", 588 ["x1 = 0x18171615efeeedec"]) 589 590 self.match("register read w30", 591 ["w30 = 0x44434241"]) 592 self.runCmd("register write w30 0xdfdedddc") 593 self.match("register read x30", 594 ["x30 = 0x48474645dfdedddc"]) 595 596 self.match("register read w31", 597 ["w31 = 0x54535251"]) 598 self.runCmd("register write w31 0xcfcecdcc") 599 self.match("register read x31", 600 ["sp = 0x58575655cfcecdcc"]) 601 602 # test FPU registers (overlapping with vector registers) 603 self.runCmd("register write d0 16") 604 self.match("register read v0", 605 ["v0 = {0x00 0x00 0x00 0x00 0x00 0x00 0x30 0x40 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90}"]) 606 self.runCmd("register write v31 '{0x00 0x00 0x00 0x00 0x00 0x00 0x50 0x40 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff}'") 607 self.match("register read d31", 608 ["d31 = 64"]) 609 610 self.runCmd("register write s0 32") 611 self.match("register read v0", 612 ["v0 = {0x00 0x00 0x00 0x42 0x00 0x00 0x30 0x40 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90}"]) 613 self.runCmd("register write v31 '{0x00 0x00 0x00 0x43 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff}'") 614 self.match("register read s31", 615 ["s31 = 128"]) 616 617 @skipIfXmlSupportMissing 618 @skipIfRemote 619 @skipIfLLVMTargetMissing("X86") 620 def test_x86_64_no_duplicate_subregs(self): 621 """Test that duplicate subregisters are not added (on x86_64).""" 622 class MyResponder(MockGDBServerResponder): 623 reg_data = ( 624 "0102030405060708" # rcx 625 "1112131415161718" # rdx 626 "2122232425262728" # rsi 627 "3132333435363738" # rdi 628 "4142434445464748" # rbp 629 "5152535455565758" # rsp 630 "6162636465666768" # r8 631 "7172737475767778" # r9 632 "8182838485868788" # rip 633 "91929394" # eflags 634 ) 635 636 def qXferRead(self, obj, annex, offset, length): 637 if annex == "target.xml": 638 return """<?xml version="1.0"?> 639 <!DOCTYPE feature SYSTEM "gdb-target.dtd"> 640 <target> 641 <architecture>i386:x86-64</architecture> 642 <osabi>GNU/Linux</osabi> 643 <feature name="org.gnu.gdb.i386.core"> 644 <reg name="rcx" bitsize="64" type="int64" regnum="2"/> 645 <reg name="rdx" bitsize="64" type="int64" regnum="3"/> 646 <reg name="rsi" bitsize="64" type="int64" regnum="4"/> 647 <reg name="rdi" bitsize="64" type="int64" regnum="5"/> 648 <reg name="rbp" bitsize="64" type="data_ptr" regnum="6"/> 649 <reg name="rsp" bitsize="64" type="data_ptr" regnum="7"/> 650 <reg name="r8" bitsize="64" type="int64" regnum="8"/> 651 <reg name="r9" bitsize="64" type="int64" regnum="9"/> 652 <reg name="rip" bitsize="64" type="code_ptr" regnum="16"/> 653 <reg name="eflags" bitsize="32" type="i386_eflags" regnum="17"/> 654 <reg name="ecx" bitsize="32" type="int" regnum="18" value_regnums="2"/> 655 </feature> 656 </target>""", False 657 else: 658 return None, False 659 660 def readRegister(self, regnum): 661 return "" 662 663 def readRegisters(self): 664 return self.reg_data 665 666 def haltReason(self): 667 return "T02thread:1ff0d;threads:1ff0d;thread-pcs:000000010001bc00;07:0102030405060708;10:1112131415161718;" 668 669 self.server.responder = MyResponder() 670 671 target = self.createTarget("basic_eh_frame.yaml") 672 process = self.connect(target) 673 lldbutil.expect_state_changes(self, self.dbg.GetListener(), process, 674 [lldb.eStateStopped]) 675 676 self.match("register read rcx", 677 ["rcx = 0x0807060504030201"]) 678 # ecx is supplied via target.xml 679 self.match("register read ecx", 680 ["ecx = 0x04030201"]) 681 self.match("register read rdx", 682 ["rdx = 0x1817161514131211"]) 683 # edx should not be added 684 self.match("register read edx", 685 ["error: Invalid register name 'edx'."], 686 error=True) 687 688 @skipIfXmlSupportMissing 689 @skipIfRemote 690 @skipIfLLVMTargetMissing("X86") 691 def test_i386_no_duplicate_subregs(self): 692 """Test that duplicate subregisters are not added (on i386).""" 693 class MyResponder(MockGDBServerResponder): 694 reg_data = ( 695 "01020304" # eax 696 "11121314" # ecx 697 "21222324" # edx 698 "31323334" # ebx 699 "41424344" # esp 700 "51525354" # ebp 701 "61626364" # esi 702 "71727374" # edi 703 "81828384" # eip 704 "91929394" # eflags 705 ) 706 707 def qXferRead(self, obj, annex, offset, length): 708 if annex == "target.xml": 709 return """<?xml version="1.0"?> 710 <!DOCTYPE feature SYSTEM "gdb-target.dtd"> 711 <target> 712 <architecture>i386</architecture> 713 <osabi>GNU/Linux</osabi> 714 <feature name="org.gnu.gdb.i386.core"> 715 <reg name="eax" bitsize="32" type="int32" regnum="0"/> 716 <reg name="ecx" bitsize="32" type="int32" regnum="1"/> 717 <reg name="edx" bitsize="32" type="int32" regnum="2"/> 718 <reg name="ebx" bitsize="32" type="int32" regnum="3"/> 719 <reg name="esp" bitsize="32" type="data_ptr" regnum="4"/> 720 <reg name="ebp" bitsize="32" type="data_ptr" regnum="5"/> 721 <reg name="esi" bitsize="32" type="int32" regnum="6"/> 722 <reg name="edi" bitsize="32" type="int32" regnum="7"/> 723 <reg name="eip" bitsize="32" type="code_ptr" regnum="8"/> 724 <reg name="eflags" bitsize="32" type="i386_eflags" regnum="9"/> 725 <reg name="ax" bitsize="16" type="int" regnum="10" value_regnums="0"/> 726 </feature> 727 </target>""", False 728 else: 729 return None, False 730 731 def readRegister(self, regnum): 732 return "" 733 734 def readRegisters(self): 735 return self.reg_data 736 737 def haltReason(self): 738 return "T02thread:1ff0d;threads:1ff0d;thread-pcs:000000010001bc00;07:0102030405060708;10:1112131415161718;" 739 740 self.server.responder = MyResponder() 741 742 target = self.createTarget("basic_eh_frame-i386.yaml") 743 process = self.connect(target) 744 lldbutil.expect_state_changes(self, self.dbg.GetListener(), process, 745 [lldb.eStateStopped]) 746 747 self.match("register read eax", 748 ["eax = 0x04030201"]) 749 # cx is supplied via target.xml 750 self.match("register read ax", 751 ["ax = 0x0201"]) 752 self.match("register read ecx", 753 ["ecx = 0x14131211"]) 754 # dx should not be added 755 self.match("register read cx", 756 ["error: Invalid register name 'cx'."], 757 error=True) 758 759 @skipIfXmlSupportMissing 760 @skipIfRemote 761 @skipIfLLVMTargetMissing("AArch64") 762 def test_aarch64_no_duplicate_subregs(self): 763 """Test that duplicate subregisters are not added.""" 764 class MyResponder(MockGDBServerResponder): 765 reg_data = ( 766 "0102030405060708" # x0 767 "1112131415161718" # x1 768 ) + 27 * ( 769 "2122232425262728" # x2..x28 770 ) + ( 771 "3132333435363738" # x29 (fp) 772 "4142434445464748" # x30 (lr) 773 "5152535455565758" # x31 (sp) 774 "6162636465666768" # pc 775 "71727374" # cpsr 776 ) 777 778 def qXferRead(self, obj, annex, offset, length): 779 if annex == "target.xml": 780 return """<?xml version="1.0"?> 781 <!DOCTYPE feature SYSTEM "gdb-target.dtd"> 782 <target> 783 <architecture>aarch64</architecture> 784 <feature name="org.gnu.gdb.aarch64.core"> 785 <reg name="x0" bitsize="64" type="int" regnum="0"/> 786 <reg name="x1" bitsize="64" type="int" regnum="1"/> 787 <reg name="x2" bitsize="64" type="int" regnum="2"/> 788 <reg name="x3" bitsize="64" type="int" regnum="3"/> 789 <reg name="x4" bitsize="64" type="int" regnum="4"/> 790 <reg name="x5" bitsize="64" type="int" regnum="5"/> 791 <reg name="x6" bitsize="64" type="int" regnum="6"/> 792 <reg name="x7" bitsize="64" type="int" regnum="7"/> 793 <reg name="x8" bitsize="64" type="int" regnum="8"/> 794 <reg name="x9" bitsize="64" type="int" regnum="9"/> 795 <reg name="x10" bitsize="64" type="int" regnum="10"/> 796 <reg name="x11" bitsize="64" type="int" regnum="11"/> 797 <reg name="x12" bitsize="64" type="int" regnum="12"/> 798 <reg name="x13" bitsize="64" type="int" regnum="13"/> 799 <reg name="x14" bitsize="64" type="int" regnum="14"/> 800 <reg name="x15" bitsize="64" type="int" regnum="15"/> 801 <reg name="x16" bitsize="64" type="int" regnum="16"/> 802 <reg name="x17" bitsize="64" type="int" regnum="17"/> 803 <reg name="x18" bitsize="64" type="int" regnum="18"/> 804 <reg name="x19" bitsize="64" type="int" regnum="19"/> 805 <reg name="x20" bitsize="64" type="int" regnum="20"/> 806 <reg name="x21" bitsize="64" type="int" regnum="21"/> 807 <reg name="x22" bitsize="64" type="int" regnum="22"/> 808 <reg name="x23" bitsize="64" type="int" regnum="23"/> 809 <reg name="x24" bitsize="64" type="int" regnum="24"/> 810 <reg name="x25" bitsize="64" type="int" regnum="25"/> 811 <reg name="x26" bitsize="64" type="int" regnum="26"/> 812 <reg name="x27" bitsize="64" type="int" regnum="27"/> 813 <reg name="x28" bitsize="64" type="int" regnum="28"/> 814 <reg name="x29" bitsize="64" type="int" regnum="29"/> 815 <reg name="x30" bitsize="64" type="int" regnum="30"/> 816 <reg name="sp" bitsize="64" type="data_ptr" regnum="31"/> 817 <reg name="pc" bitsize="64" type="code_ptr" regnum="32"/> 818 <reg name="cpsr" bitsize="32" type="cpsr_flags" regnum="33"/> 819 <reg name="w0" bitsize="32" type="int" regnum="34" value_regnums="0"/> 820 </feature> 821 </target>""", False 822 else: 823 return None, False 824 825 def readRegister(self, regnum): 826 return "" 827 828 def readRegisters(self): 829 return self.reg_data 830 831 def haltReason(self): 832 return "T02thread:1ff0d;threads:1ff0d;thread-pcs:000000010001bc00;07:0102030405060708;10:1112131415161718;" 833 834 self.server.responder = MyResponder() 835 836 target = self.createTarget("basic_eh_frame-aarch64.yaml") 837 process = self.connect(target) 838 lldbutil.expect_state_changes(self, self.dbg.GetListener(), process, 839 [lldb.eStateStopped]) 840 841 self.match("register read x0", 842 ["x0 = 0x0807060504030201"]) 843 # w0 comes from target.xml 844 self.match("register read w0", 845 ["w0 = 0x04030201"]) 846 self.match("register read x1", 847 ["x1 = 0x1817161514131211"]) 848 # w1 should not be added 849 self.match("register read w1", 850 ["error: Invalid register name 'w1'."], 851 error=True) 852