1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 3 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s 4 // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 5 // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 6 // RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK4 7 8 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 9 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s 10 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 11 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 12 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 13 // expected-no-diagnostics 14 #ifndef HEADER 15 #define HEADER 16 17 template <class T> 18 struct S { 19 T f; 20 S(T a) : f(a) {} 21 S() : f() {} 22 S<T> &operator=(const S<T> &); 23 operator T() { return T(); } 24 ~S() {} 25 }; 26 27 volatile int g = 1212; 28 float f; 29 char cnt; 30 31 template <typename T> 32 T tmain() { 33 S<T> test; 34 T *pvar = &test.f; 35 T lvar = T(); 36 #pragma omp parallel for linear(pvar, lvar) 37 for (int i = 0; i < 2; ++i) { 38 ++pvar, ++lvar; 39 } 40 return T(); 41 } 42 43 int main() { 44 #ifdef LAMBDA 45 [&]() { 46 #pragma omp parallel for linear(g:5) 47 for (int i = 0; i < 2; ++i) { 48 g += 5; 49 [&]() { 50 g = 2; 51 }(); 52 } 53 }(); 54 return 0; 55 #elif defined(BLOCKS) 56 ^{ 57 #pragma omp parallel for linear(g:5) 58 for (int i = 0; i < 2; ++i) { 59 g += 5; 60 g = 1; 61 ^{ 62 g = 2; 63 }(); 64 } 65 }(); 66 return 0; 67 #else 68 S<float> test; 69 float *pvar = &test.f; 70 long long lvar = 0; 71 #pragma omp parallel for linear(pvar, lvar : 3) 72 for (int i = 0; i < 2; ++i) { 73 pvar += 3, lvar += 3; 74 } 75 return tmain<int>(); 76 #endif 77 } 78 79 80 81 82 // Check for default initialization. 83 84 85 86 // Check for default initialization. 87 #endif 88 89 // CHECK1-LABEL: define {{[^@]+}}@main 90 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 91 // CHECK1-NEXT: entry: 92 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 93 // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 94 // CHECK1-NEXT: [[PVAR:%.*]] = alloca float*, align 8 95 // CHECK1-NEXT: [[LVAR:%.*]] = alloca i64, align 8 96 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 97 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) 98 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TEST]], i32 0, i32 0 99 // CHECK1-NEXT: store float* [[F]], float** [[PVAR]], align 8 100 // CHECK1-NEXT: store i64 0, i64* [[LVAR]], align 8 101 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, i64*)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[PVAR]], i64* [[LVAR]]) 102 // CHECK1-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() 103 // CHECK1-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 104 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4:[0-9]+]] 105 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[RETVAL]], align 4 106 // CHECK1-NEXT: ret i32 [[TMP0]] 107 // 108 // 109 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 110 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { 111 // CHECK1-NEXT: entry: 112 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 113 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 114 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 115 // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 116 // CHECK1-NEXT: ret void 117 // 118 // 119 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 120 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[PVAR:%.*]], i64* nonnull align 8 dereferenceable(8) [[LVAR:%.*]]) #[[ATTR2:[0-9]+]] { 121 // CHECK1-NEXT: entry: 122 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 123 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 124 // CHECK1-NEXT: [[PVAR_ADDR:%.*]] = alloca float**, align 8 125 // CHECK1-NEXT: [[LVAR_ADDR:%.*]] = alloca i64*, align 8 126 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 127 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 128 // CHECK1-NEXT: [[DOTLINEAR_START:%.*]] = alloca float*, align 8 129 // CHECK1-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i64, align 8 130 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 131 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 132 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 133 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 134 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 135 // CHECK1-NEXT: [[PVAR2:%.*]] = alloca float*, align 8 136 // CHECK1-NEXT: [[LVAR3:%.*]] = alloca i64, align 8 137 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 138 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 139 // CHECK1-NEXT: store float** [[PVAR]], float*** [[PVAR_ADDR]], align 8 140 // CHECK1-NEXT: store i64* [[LVAR]], i64** [[LVAR_ADDR]], align 8 141 // CHECK1-NEXT: [[TMP0:%.*]] = load float**, float*** [[PVAR_ADDR]], align 8 142 // CHECK1-NEXT: [[TMP1:%.*]] = load i64*, i64** [[LVAR_ADDR]], align 8 143 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[TMP0]], align 8 144 // CHECK1-NEXT: store float* [[TMP2]], float** [[DOTLINEAR_START]], align 8 145 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[TMP1]], align 8 146 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[DOTLINEAR_START1]], align 8 147 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 148 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 149 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 150 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 151 // CHECK1-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 152 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 153 // CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP5]]) 154 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 155 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 156 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1 157 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 158 // CHECK1: cond.true: 159 // CHECK1-NEXT: br label [[COND_END:%.*]] 160 // CHECK1: cond.false: 161 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 162 // CHECK1-NEXT: br label [[COND_END]] 163 // CHECK1: cond.end: 164 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 165 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 166 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 167 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 168 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 169 // CHECK1: omp.inner.for.cond: 170 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 171 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 172 // CHECK1-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 173 // CHECK1-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 174 // CHECK1: omp.inner.for.body: 175 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 176 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 177 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 178 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 179 // CHECK1-NEXT: [[TMP12:%.*]] = load float*, float** [[DOTLINEAR_START]], align 8 180 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 181 // CHECK1-NEXT: [[MUL5:%.*]] = mul nsw i32 [[TMP13]], 3 182 // CHECK1-NEXT: [[IDX_EXT:%.*]] = sext i32 [[MUL5]] to i64 183 // CHECK1-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDX_EXT]] 184 // CHECK1-NEXT: store float* [[ADD_PTR]], float** [[PVAR2]], align 8 185 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTLINEAR_START1]], align 8 186 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 187 // CHECK1-NEXT: [[MUL6:%.*]] = mul nsw i32 [[TMP15]], 3 188 // CHECK1-NEXT: [[CONV:%.*]] = sext i32 [[MUL6]] to i64 189 // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i64 [[TMP14]], [[CONV]] 190 // CHECK1-NEXT: store i64 [[ADD7]], i64* [[LVAR3]], align 8 191 // CHECK1-NEXT: [[TMP16:%.*]] = load float*, float** [[PVAR2]], align 8 192 // CHECK1-NEXT: [[ADD_PTR8:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 3 193 // CHECK1-NEXT: store float* [[ADD_PTR8]], float** [[PVAR2]], align 8 194 // CHECK1-NEXT: [[TMP17:%.*]] = load i64, i64* [[LVAR3]], align 8 195 // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i64 [[TMP17]], 3 196 // CHECK1-NEXT: store i64 [[ADD9]], i64* [[LVAR3]], align 8 197 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 198 // CHECK1: omp.body.continue: 199 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 200 // CHECK1: omp.inner.for.inc: 201 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 202 // CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP18]], 1 203 // CHECK1-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 204 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 205 // CHECK1: omp.inner.for.end: 206 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 207 // CHECK1: omp.loop.exit: 208 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]]) 209 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 210 // CHECK1-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0 211 // CHECK1-NEXT: br i1 [[TMP20]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 212 // CHECK1: .omp.linear.pu: 213 // CHECK1-NEXT: [[TMP21:%.*]] = load float*, float** [[PVAR2]], align 8 214 // CHECK1-NEXT: store float* [[TMP21]], float** [[TMP0]], align 8 215 // CHECK1-NEXT: [[TMP22:%.*]] = load i64, i64* [[LVAR3]], align 8 216 // CHECK1-NEXT: store i64 [[TMP22]], i64* [[TMP1]], align 8 217 // CHECK1-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 218 // CHECK1: .omp.linear.pu.done: 219 // CHECK1-NEXT: ret void 220 // 221 // 222 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 223 // CHECK1-SAME: () #[[ATTR5:[0-9]+]] { 224 // CHECK1-NEXT: entry: 225 // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 226 // CHECK1-NEXT: [[PVAR:%.*]] = alloca i32*, align 8 227 // CHECK1-NEXT: [[LVAR:%.*]] = alloca i32, align 4 228 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 229 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TEST]], i32 0, i32 0 230 // CHECK1-NEXT: store i32* [[F]], i32** [[PVAR]], align 8 231 // CHECK1-NEXT: store i32 0, i32* [[LVAR]], align 4 232 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32**, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32** [[PVAR]], i32* [[LVAR]]) 233 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 234 // CHECK1-NEXT: ret i32 0 235 // 236 // 237 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 238 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 239 // CHECK1-NEXT: entry: 240 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 241 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 242 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 243 // CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 244 // CHECK1-NEXT: ret void 245 // 246 // 247 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 248 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 249 // CHECK1-NEXT: entry: 250 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 251 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 252 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 253 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 254 // CHECK1-NEXT: store float 0.000000e+00, float* [[F]], align 4 255 // CHECK1-NEXT: ret void 256 // 257 // 258 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 259 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 260 // CHECK1-NEXT: entry: 261 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 262 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 263 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 264 // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 265 // CHECK1-NEXT: ret void 266 // 267 // 268 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 269 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32** nonnull align 8 dereferenceable(8) [[PVAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[LVAR:%.*]]) #[[ATTR2]] { 270 // CHECK1-NEXT: entry: 271 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 272 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 273 // CHECK1-NEXT: [[PVAR_ADDR:%.*]] = alloca i32**, align 8 274 // CHECK1-NEXT: [[LVAR_ADDR:%.*]] = alloca i32*, align 8 275 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 276 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 277 // CHECK1-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32*, align 8 278 // CHECK1-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 279 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 280 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 281 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 282 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 283 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 284 // CHECK1-NEXT: [[PVAR2:%.*]] = alloca i32*, align 8 285 // CHECK1-NEXT: [[LVAR3:%.*]] = alloca i32, align 4 286 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 287 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 288 // CHECK1-NEXT: store i32** [[PVAR]], i32*** [[PVAR_ADDR]], align 8 289 // CHECK1-NEXT: store i32* [[LVAR]], i32** [[LVAR_ADDR]], align 8 290 // CHECK1-NEXT: [[TMP0:%.*]] = load i32**, i32*** [[PVAR_ADDR]], align 8 291 // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[LVAR_ADDR]], align 8 292 // CHECK1-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP0]], align 8 293 // CHECK1-NEXT: store i32* [[TMP2]], i32** [[DOTLINEAR_START]], align 8 294 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP1]], align 4 295 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[DOTLINEAR_START1]], align 4 296 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 297 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 298 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 299 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 300 // CHECK1-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 301 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 302 // CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 303 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 304 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 305 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1 306 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 307 // CHECK1: cond.true: 308 // CHECK1-NEXT: br label [[COND_END:%.*]] 309 // CHECK1: cond.false: 310 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 311 // CHECK1-NEXT: br label [[COND_END]] 312 // CHECK1: cond.end: 313 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 314 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 315 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 316 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 317 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 318 // CHECK1: omp.inner.for.cond: 319 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 320 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 321 // CHECK1-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 322 // CHECK1-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 323 // CHECK1: omp.inner.for.body: 324 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 325 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 326 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 327 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 328 // CHECK1-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTLINEAR_START]], align 8 329 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 330 // CHECK1-NEXT: [[MUL5:%.*]] = mul nsw i32 [[TMP13]], 1 331 // CHECK1-NEXT: [[IDX_EXT:%.*]] = sext i32 [[MUL5]] to i64 332 // CHECK1-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i32, i32* [[TMP12]], i64 [[IDX_EXT]] 333 // CHECK1-NEXT: store i32* [[ADD_PTR]], i32** [[PVAR2]], align 8 334 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4 335 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 336 // CHECK1-NEXT: [[MUL6:%.*]] = mul nsw i32 [[TMP15]], 1 337 // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP14]], [[MUL6]] 338 // CHECK1-NEXT: store i32 [[ADD7]], i32* [[LVAR3]], align 4 339 // CHECK1-NEXT: [[TMP16:%.*]] = load i32*, i32** [[PVAR2]], align 8 340 // CHECK1-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds i32, i32* [[TMP16]], i32 1 341 // CHECK1-NEXT: store i32* [[INCDEC_PTR]], i32** [[PVAR2]], align 8 342 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[LVAR3]], align 4 343 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP17]], 1 344 // CHECK1-NEXT: store i32 [[INC]], i32* [[LVAR3]], align 4 345 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 346 // CHECK1: omp.body.continue: 347 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 348 // CHECK1: omp.inner.for.inc: 349 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 350 // CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP18]], 1 351 // CHECK1-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 352 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 353 // CHECK1: omp.inner.for.end: 354 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 355 // CHECK1: omp.loop.exit: 356 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]]) 357 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 358 // CHECK1-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0 359 // CHECK1-NEXT: br i1 [[TMP20]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 360 // CHECK1: .omp.linear.pu: 361 // CHECK1-NEXT: [[TMP21:%.*]] = load i32*, i32** [[PVAR2]], align 8 362 // CHECK1-NEXT: store i32* [[TMP21]], i32** [[TMP0]], align 8 363 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[LVAR3]], align 4 364 // CHECK1-NEXT: store i32 [[TMP22]], i32* [[TMP1]], align 4 365 // CHECK1-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 366 // CHECK1: .omp.linear.pu.done: 367 // CHECK1-NEXT: ret void 368 // 369 // 370 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 371 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 372 // CHECK1-NEXT: entry: 373 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 374 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 375 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 376 // CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 377 // CHECK1-NEXT: ret void 378 // 379 // 380 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 381 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 382 // CHECK1-NEXT: entry: 383 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 384 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 385 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 386 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 387 // CHECK1-NEXT: store i32 0, i32* [[F]], align 4 388 // CHECK1-NEXT: ret void 389 // 390 // 391 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 392 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 393 // CHECK1-NEXT: entry: 394 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 395 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 396 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 397 // CHECK1-NEXT: ret void 398 // 399 // 400 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 401 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 402 // CHECK1-NEXT: entry: 403 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 404 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 405 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 406 // CHECK1-NEXT: ret void 407 // 408 // 409 // CHECK2-LABEL: define {{[^@]+}}@main 410 // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { 411 // CHECK2-NEXT: entry: 412 // CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 413 // CHECK2-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 414 // CHECK2-NEXT: [[PVAR:%.*]] = alloca float*, align 8 415 // CHECK2-NEXT: [[LVAR:%.*]] = alloca i64, align 8 416 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 417 // CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) 418 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TEST]], i32 0, i32 0 419 // CHECK2-NEXT: store float* [[F]], float** [[PVAR]], align 8 420 // CHECK2-NEXT: store i64 0, i64* [[LVAR]], align 8 421 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, i64*)* @.omp_outlined. to void (i32*, i32*, ...)*), float** [[PVAR]], i64* [[LVAR]]) 422 // CHECK2-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() 423 // CHECK2-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 424 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4:[0-9]+]] 425 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[RETVAL]], align 4 426 // CHECK2-NEXT: ret i32 [[TMP0]] 427 // 428 // 429 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 430 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { 431 // CHECK2-NEXT: entry: 432 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 433 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 434 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 435 // CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 436 // CHECK2-NEXT: ret void 437 // 438 // 439 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. 440 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[PVAR:%.*]], i64* nonnull align 8 dereferenceable(8) [[LVAR:%.*]]) #[[ATTR2:[0-9]+]] { 441 // CHECK2-NEXT: entry: 442 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 443 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 444 // CHECK2-NEXT: [[PVAR_ADDR:%.*]] = alloca float**, align 8 445 // CHECK2-NEXT: [[LVAR_ADDR:%.*]] = alloca i64*, align 8 446 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 447 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 448 // CHECK2-NEXT: [[DOTLINEAR_START:%.*]] = alloca float*, align 8 449 // CHECK2-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i64, align 8 450 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 451 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 452 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 453 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 454 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 455 // CHECK2-NEXT: [[PVAR2:%.*]] = alloca float*, align 8 456 // CHECK2-NEXT: [[LVAR3:%.*]] = alloca i64, align 8 457 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 458 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 459 // CHECK2-NEXT: store float** [[PVAR]], float*** [[PVAR_ADDR]], align 8 460 // CHECK2-NEXT: store i64* [[LVAR]], i64** [[LVAR_ADDR]], align 8 461 // CHECK2-NEXT: [[TMP0:%.*]] = load float**, float*** [[PVAR_ADDR]], align 8 462 // CHECK2-NEXT: [[TMP1:%.*]] = load i64*, i64** [[LVAR_ADDR]], align 8 463 // CHECK2-NEXT: [[TMP2:%.*]] = load float*, float** [[TMP0]], align 8 464 // CHECK2-NEXT: store float* [[TMP2]], float** [[DOTLINEAR_START]], align 8 465 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[TMP1]], align 8 466 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[DOTLINEAR_START1]], align 8 467 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 468 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 469 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 470 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 471 // CHECK2-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 472 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 473 // CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP5]]) 474 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 475 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 476 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1 477 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 478 // CHECK2: cond.true: 479 // CHECK2-NEXT: br label [[COND_END:%.*]] 480 // CHECK2: cond.false: 481 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 482 // CHECK2-NEXT: br label [[COND_END]] 483 // CHECK2: cond.end: 484 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 485 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 486 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 487 // CHECK2-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 488 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 489 // CHECK2: omp.inner.for.cond: 490 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 491 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 492 // CHECK2-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 493 // CHECK2-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 494 // CHECK2: omp.inner.for.body: 495 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 496 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 497 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 498 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 499 // CHECK2-NEXT: [[TMP12:%.*]] = load float*, float** [[DOTLINEAR_START]], align 8 500 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 501 // CHECK2-NEXT: [[MUL5:%.*]] = mul nsw i32 [[TMP13]], 3 502 // CHECK2-NEXT: [[IDX_EXT:%.*]] = sext i32 [[MUL5]] to i64 503 // CHECK2-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDX_EXT]] 504 // CHECK2-NEXT: store float* [[ADD_PTR]], float** [[PVAR2]], align 8 505 // CHECK2-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTLINEAR_START1]], align 8 506 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 507 // CHECK2-NEXT: [[MUL6:%.*]] = mul nsw i32 [[TMP15]], 3 508 // CHECK2-NEXT: [[CONV:%.*]] = sext i32 [[MUL6]] to i64 509 // CHECK2-NEXT: [[ADD7:%.*]] = add nsw i64 [[TMP14]], [[CONV]] 510 // CHECK2-NEXT: store i64 [[ADD7]], i64* [[LVAR3]], align 8 511 // CHECK2-NEXT: [[TMP16:%.*]] = load float*, float** [[PVAR2]], align 8 512 // CHECK2-NEXT: [[ADD_PTR8:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 3 513 // CHECK2-NEXT: store float* [[ADD_PTR8]], float** [[PVAR2]], align 8 514 // CHECK2-NEXT: [[TMP17:%.*]] = load i64, i64* [[LVAR3]], align 8 515 // CHECK2-NEXT: [[ADD9:%.*]] = add nsw i64 [[TMP17]], 3 516 // CHECK2-NEXT: store i64 [[ADD9]], i64* [[LVAR3]], align 8 517 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 518 // CHECK2: omp.body.continue: 519 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 520 // CHECK2: omp.inner.for.inc: 521 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 522 // CHECK2-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP18]], 1 523 // CHECK2-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 524 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 525 // CHECK2: omp.inner.for.end: 526 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 527 // CHECK2: omp.loop.exit: 528 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]]) 529 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 530 // CHECK2-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0 531 // CHECK2-NEXT: br i1 [[TMP20]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 532 // CHECK2: .omp.linear.pu: 533 // CHECK2-NEXT: [[TMP21:%.*]] = load float*, float** [[PVAR2]], align 8 534 // CHECK2-NEXT: store float* [[TMP21]], float** [[TMP0]], align 8 535 // CHECK2-NEXT: [[TMP22:%.*]] = load i64, i64* [[LVAR3]], align 8 536 // CHECK2-NEXT: store i64 [[TMP22]], i64* [[TMP1]], align 8 537 // CHECK2-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 538 // CHECK2: .omp.linear.pu.done: 539 // CHECK2-NEXT: ret void 540 // 541 // 542 // CHECK2-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 543 // CHECK2-SAME: () #[[ATTR5:[0-9]+]] { 544 // CHECK2-NEXT: entry: 545 // CHECK2-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 546 // CHECK2-NEXT: [[PVAR:%.*]] = alloca i32*, align 8 547 // CHECK2-NEXT: [[LVAR:%.*]] = alloca i32, align 4 548 // CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 549 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TEST]], i32 0, i32 0 550 // CHECK2-NEXT: store i32* [[F]], i32** [[PVAR]], align 8 551 // CHECK2-NEXT: store i32 0, i32* [[LVAR]], align 4 552 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32**, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32** [[PVAR]], i32* [[LVAR]]) 553 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 554 // CHECK2-NEXT: ret i32 0 555 // 556 // 557 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 558 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 559 // CHECK2-NEXT: entry: 560 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 561 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 562 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 563 // CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 564 // CHECK2-NEXT: ret void 565 // 566 // 567 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 568 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 569 // CHECK2-NEXT: entry: 570 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 571 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 572 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 573 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 574 // CHECK2-NEXT: store float 0.000000e+00, float* [[F]], align 4 575 // CHECK2-NEXT: ret void 576 // 577 // 578 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 579 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 580 // CHECK2-NEXT: entry: 581 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 582 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 583 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 584 // CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 585 // CHECK2-NEXT: ret void 586 // 587 // 588 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 589 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32** nonnull align 8 dereferenceable(8) [[PVAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[LVAR:%.*]]) #[[ATTR2]] { 590 // CHECK2-NEXT: entry: 591 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 592 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 593 // CHECK2-NEXT: [[PVAR_ADDR:%.*]] = alloca i32**, align 8 594 // CHECK2-NEXT: [[LVAR_ADDR:%.*]] = alloca i32*, align 8 595 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 596 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 597 // CHECK2-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32*, align 8 598 // CHECK2-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 599 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 600 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 601 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 602 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 603 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 604 // CHECK2-NEXT: [[PVAR2:%.*]] = alloca i32*, align 8 605 // CHECK2-NEXT: [[LVAR3:%.*]] = alloca i32, align 4 606 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 607 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 608 // CHECK2-NEXT: store i32** [[PVAR]], i32*** [[PVAR_ADDR]], align 8 609 // CHECK2-NEXT: store i32* [[LVAR]], i32** [[LVAR_ADDR]], align 8 610 // CHECK2-NEXT: [[TMP0:%.*]] = load i32**, i32*** [[PVAR_ADDR]], align 8 611 // CHECK2-NEXT: [[TMP1:%.*]] = load i32*, i32** [[LVAR_ADDR]], align 8 612 // CHECK2-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP0]], align 8 613 // CHECK2-NEXT: store i32* [[TMP2]], i32** [[DOTLINEAR_START]], align 8 614 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP1]], align 4 615 // CHECK2-NEXT: store i32 [[TMP3]], i32* [[DOTLINEAR_START1]], align 4 616 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 617 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 618 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 619 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 620 // CHECK2-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 621 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 622 // CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 623 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 624 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 625 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1 626 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 627 // CHECK2: cond.true: 628 // CHECK2-NEXT: br label [[COND_END:%.*]] 629 // CHECK2: cond.false: 630 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 631 // CHECK2-NEXT: br label [[COND_END]] 632 // CHECK2: cond.end: 633 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 634 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 635 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 636 // CHECK2-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 637 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 638 // CHECK2: omp.inner.for.cond: 639 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 640 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 641 // CHECK2-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 642 // CHECK2-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 643 // CHECK2: omp.inner.for.body: 644 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 645 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 646 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 647 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 648 // CHECK2-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTLINEAR_START]], align 8 649 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 650 // CHECK2-NEXT: [[MUL5:%.*]] = mul nsw i32 [[TMP13]], 1 651 // CHECK2-NEXT: [[IDX_EXT:%.*]] = sext i32 [[MUL5]] to i64 652 // CHECK2-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i32, i32* [[TMP12]], i64 [[IDX_EXT]] 653 // CHECK2-NEXT: store i32* [[ADD_PTR]], i32** [[PVAR2]], align 8 654 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4 655 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 656 // CHECK2-NEXT: [[MUL6:%.*]] = mul nsw i32 [[TMP15]], 1 657 // CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP14]], [[MUL6]] 658 // CHECK2-NEXT: store i32 [[ADD7]], i32* [[LVAR3]], align 4 659 // CHECK2-NEXT: [[TMP16:%.*]] = load i32*, i32** [[PVAR2]], align 8 660 // CHECK2-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds i32, i32* [[TMP16]], i32 1 661 // CHECK2-NEXT: store i32* [[INCDEC_PTR]], i32** [[PVAR2]], align 8 662 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[LVAR3]], align 4 663 // CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP17]], 1 664 // CHECK2-NEXT: store i32 [[INC]], i32* [[LVAR3]], align 4 665 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 666 // CHECK2: omp.body.continue: 667 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 668 // CHECK2: omp.inner.for.inc: 669 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 670 // CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP18]], 1 671 // CHECK2-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 672 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 673 // CHECK2: omp.inner.for.end: 674 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 675 // CHECK2: omp.loop.exit: 676 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]]) 677 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 678 // CHECK2-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0 679 // CHECK2-NEXT: br i1 [[TMP20]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 680 // CHECK2: .omp.linear.pu: 681 // CHECK2-NEXT: [[TMP21:%.*]] = load i32*, i32** [[PVAR2]], align 8 682 // CHECK2-NEXT: store i32* [[TMP21]], i32** [[TMP0]], align 8 683 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[LVAR3]], align 4 684 // CHECK2-NEXT: store i32 [[TMP22]], i32* [[TMP1]], align 4 685 // CHECK2-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 686 // CHECK2: .omp.linear.pu.done: 687 // CHECK2-NEXT: ret void 688 // 689 // 690 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 691 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 692 // CHECK2-NEXT: entry: 693 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 694 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 695 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 696 // CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 697 // CHECK2-NEXT: ret void 698 // 699 // 700 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 701 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 702 // CHECK2-NEXT: entry: 703 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 704 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 705 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 706 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 707 // CHECK2-NEXT: store i32 0, i32* [[F]], align 4 708 // CHECK2-NEXT: ret void 709 // 710 // 711 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 712 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 713 // CHECK2-NEXT: entry: 714 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 715 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 716 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 717 // CHECK2-NEXT: ret void 718 // 719 // 720 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 721 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 722 // CHECK2-NEXT: entry: 723 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 724 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 725 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 726 // CHECK2-NEXT: ret void 727 // 728 // 729 // CHECK3-LABEL: define {{[^@]+}}@main 730 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 731 // CHECK3-NEXT: entry: 732 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 733 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 734 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 735 // CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) 736 // CHECK3-NEXT: ret i32 0 737 // 738 // 739 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. 740 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[G:%.*]]) #[[ATTR2:[0-9]+]] { 741 // CHECK3-NEXT: entry: 742 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 743 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 744 // CHECK3-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 745 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 746 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 747 // CHECK3-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 748 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 749 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 750 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 751 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 752 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 753 // CHECK3-NEXT: [[G1:%.*]] = alloca i32, align 4 754 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 755 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 756 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 757 // CHECK3-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 758 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[G_ADDR]], align 8 759 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 760 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START]], align 4 761 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 762 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 763 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 764 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 765 // CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 766 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 767 // CHECK3-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP3]]) 768 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 769 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 770 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 771 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 772 // CHECK3: cond.true: 773 // CHECK3-NEXT: br label [[COND_END:%.*]] 774 // CHECK3: cond.false: 775 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 776 // CHECK3-NEXT: br label [[COND_END]] 777 // CHECK3: cond.end: 778 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 779 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 780 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 781 // CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 782 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 783 // CHECK3: omp.inner.for.cond: 784 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 785 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 786 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 787 // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 788 // CHECK3: omp.inner.for.body: 789 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 790 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 791 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 792 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 793 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 794 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 795 // CHECK3-NEXT: [[MUL3:%.*]] = mul nsw i32 [[TMP11]], 5 796 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], [[MUL3]] 797 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[G1]], align 4 798 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[G1]], align 4 799 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP12]], 5 800 // CHECK3-NEXT: store i32 [[ADD5]], i32* [[G1]], align 4 801 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 802 // CHECK3-NEXT: store i32* [[G1]], i32** [[TMP13]], align 8 803 // CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(8) [[REF_TMP]]) 804 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 805 // CHECK3: omp.body.continue: 806 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 807 // CHECK3: omp.inner.for.inc: 808 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 809 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP14]], 1 810 // CHECK3-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 811 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 812 // CHECK3: omp.inner.for.end: 813 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 814 // CHECK3: omp.loop.exit: 815 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]]) 816 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 817 // CHECK3-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0 818 // CHECK3-NEXT: br i1 [[TMP16]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 819 // CHECK3: .omp.linear.pu: 820 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[G1]], align 4 821 // CHECK3-NEXT: store i32 [[TMP17]], i32* [[TMP0]], align 4 822 // CHECK3-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 823 // CHECK3: .omp.linear.pu.done: 824 // CHECK3-NEXT: ret void 825 // 826 // 827 // CHECK4-LABEL: define {{[^@]+}}@main 828 // CHECK4-SAME: () #[[ATTR1:[0-9]+]] { 829 // CHECK4-NEXT: entry: 830 // CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 831 // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 832 // CHECK4-NEXT: [[TMP0:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to %struct.__block_literal_generic*), i32 0, i32 3), align 8 833 // CHECK4-NEXT: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to void (i8*)* 834 // CHECK4-NEXT: call void [[TMP1]](i8* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*)) 835 // CHECK4-NEXT: ret i32 0 836 // 837 // 838 // CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke 839 // CHECK4-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] { 840 // CHECK4-NEXT: entry: 841 // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 842 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8 843 // CHECK4-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 844 // CHECK4-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* 845 // CHECK4-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>** [[BLOCK_ADDR]], align 8 846 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* @g) 847 // CHECK4-NEXT: ret void 848 // 849 // 850 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. 851 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[G:%.*]]) #[[ATTR3:[0-9]+]] { 852 // CHECK4-NEXT: entry: 853 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 854 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 855 // CHECK4-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 856 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 857 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 858 // CHECK4-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 859 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 860 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 861 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 862 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 863 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 864 // CHECK4-NEXT: [[G1:%.*]] = alloca i32, align 4 865 // CHECK4-NEXT: [[BLOCK:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, align 8 866 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 867 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 868 // CHECK4-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 869 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[G_ADDR]], align 8 870 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 871 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START]], align 4 872 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 873 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 874 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 875 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 876 // CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 877 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 878 // CHECK4-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP3]]) 879 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 880 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 881 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 882 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 883 // CHECK4: cond.true: 884 // CHECK4-NEXT: br label [[COND_END:%.*]] 885 // CHECK4: cond.false: 886 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 887 // CHECK4-NEXT: br label [[COND_END]] 888 // CHECK4: cond.end: 889 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 890 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 891 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 892 // CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 893 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 894 // CHECK4: omp.inner.for.cond: 895 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 896 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 897 // CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 898 // CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 899 // CHECK4: omp.inner.for.body: 900 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 901 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 902 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 903 // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 904 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4 905 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 906 // CHECK4-NEXT: [[MUL3:%.*]] = mul nsw i32 [[TMP11]], 5 907 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], [[MUL3]] 908 // CHECK4-NEXT: store i32 [[ADD4]], i32* [[G1]], align 4 909 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[G1]], align 4 910 // CHECK4-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP12]], 5 911 // CHECK4-NEXT: store i32 [[ADD5]], i32* [[G1]], align 4 912 // CHECK4-NEXT: store i32 1, i32* [[G1]], align 4 913 // CHECK4-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 0 914 // CHECK4-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 915 // CHECK4-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 1 916 // CHECK4-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 917 // CHECK4-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 2 918 // CHECK4-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 919 // CHECK4-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 3 920 // CHECK4-NEXT: store i8* bitcast (void (i8*)* @g_block_invoke to i8*), i8** [[BLOCK_INVOKE]], align 8 921 // CHECK4-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 4 922 // CHECK4-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.1 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 923 // CHECK4-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 5 924 // CHECK4-NEXT: [[TMP13:%.*]] = load volatile i32, i32* [[G1]], align 4 925 // CHECK4-NEXT: store volatile i32 [[TMP13]], i32* [[BLOCK_CAPTURED]], align 8 926 // CHECK4-NEXT: [[TMP14:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]] to void ()* 927 // CHECK4-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP14]] to %struct.__block_literal_generic* 928 // CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 929 // CHECK4-NEXT: [[TMP16:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* 930 // CHECK4-NEXT: [[TMP17:%.*]] = load i8*, i8** [[TMP15]], align 8 931 // CHECK4-NEXT: [[TMP18:%.*]] = bitcast i8* [[TMP17]] to void (i8*)* 932 // CHECK4-NEXT: call void [[TMP18]](i8* [[TMP16]]) 933 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 934 // CHECK4: omp.body.continue: 935 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 936 // CHECK4: omp.inner.for.inc: 937 // CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 938 // CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP19]], 1 939 // CHECK4-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 940 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] 941 // CHECK4: omp.inner.for.end: 942 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 943 // CHECK4: omp.loop.exit: 944 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]]) 945 // CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 946 // CHECK4-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 947 // CHECK4-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 948 // CHECK4: .omp.linear.pu: 949 // CHECK4-NEXT: [[TMP22:%.*]] = load i32, i32* [[G1]], align 4 950 // CHECK4-NEXT: store i32 [[TMP22]], i32* [[TMP0]], align 4 951 // CHECK4-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 952 // CHECK4: .omp.linear.pu.done: 953 // CHECK4-NEXT: ret void 954 // 955 // 956 // CHECK4-LABEL: define {{[^@]+}}@g_block_invoke 957 // CHECK4-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { 958 // CHECK4-NEXT: entry: 959 // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 960 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>*, align 8 961 // CHECK4-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 962 // CHECK4-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* 963 // CHECK4-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>** [[BLOCK_ADDR]], align 8 964 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 5 965 // CHECK4-NEXT: store i32 2, i32* [[BLOCK_CAPTURE_ADDR]], align 8 966 // CHECK4-NEXT: ret void 967 // 968