1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefixes=CHECK1,CHECK1-NORMAL 3 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s 4 // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK2,CHECK2-NORMAL 5 6 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-enable-irbuilder -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefixes=CHECK1,CHECK1-IRBUILDER 7 // RUN: %clang_cc1 -fopenmp -fopenmp-enable-irbuilder -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s 8 // RUN: %clang_cc1 -fopenmp -fopenmp-enable-irbuilder -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK2,CHECK2-IRBUILDER 9 10 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -fopenmp-version=45 -o - | FileCheck %s --check-prefixes=CHECK3,CHECK3-NORMAL 11 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -fopenmp-version=45 -o %t %s 12 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK4,CHECK4-NORMAL 13 14 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-enable-irbuilder -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -fopenmp-version=45 -o - | FileCheck %s --check-prefixes=CHECK3,CHECK3-IRBUILDER 15 // RUN: %clang_cc1 -fopenmp -fopenmp-enable-irbuilder -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -fopenmp-version=45 -o %t %s 16 // RUN: %clang_cc1 -fopenmp -fopenmp-enable-irbuilder -fopenmp-version=45 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK4,CHECK4-IRBUILDER 17 18 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK5 19 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s 20 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 21 // expected-no-diagnostics 22 #ifndef HEADER 23 #define HEADER 24 25 void static_not_chunked(float *a, float *b, float *c, float *d) { 26 #pragma omp for schedule(static) ordered 27 28 // Loop header 29 30 for (int i = 32000000; i > 33; i += -7) { 31 // Start of body: calculate i from IV: 32 33 // ... start of ordered region ... 34 // ... loop body ... 35 // End of body: store into a[i]: 36 // ... end of ordered region ... 37 #pragma omp ordered 38 a[i] = b[i] * c[i] * d[i]; 39 } 40 } 41 42 void dynamic1(float *a, float *b, float *c, float *d) { 43 #pragma omp for schedule(dynamic) ordered 44 45 // Loop header 46 47 for (unsigned long long i = 131071; i < 2147483647; i += 127) { 48 // Start of body: calculate i from IV: 49 50 // ... start of ordered region ... 51 // ... loop body ... 52 // End of body: store into a[i]: 53 // ... end of ordered region ... 54 #pragma omp ordered threads 55 a[i] = b[i] * c[i] * d[i]; 56 57 // ... end iteration for ordered loop ... 58 } 59 } 60 61 void test_auto(float *a, float *b, float *c, float *d) { 62 unsigned int x = 0; 63 unsigned int y = 0; 64 #pragma omp for schedule(auto) collapse(2) ordered 65 66 // Loop header 67 68 // FIXME: When the iteration count of some nested loop is not a known constant, 69 // we should pre-calculate it, like we do for the total number of iterations! 70 for (char i = static_cast<char>(y); i <= '9'; ++i) 71 for (x = 11; x > 0; --x) { 72 // Start of body: indices are calculated from IV: 73 74 // ... start of ordered region ... 75 // ... loop body ... 76 // End of body: store into a[i]: 77 // ... end of ordered region ... 78 #pragma omp ordered 79 a[i] = b[i] * c[i] * d[i]; 80 81 // ... end iteration for ordered loop ... 82 } 83 } 84 85 void runtime(float *a, float *b, float *c, float *d) { 86 int x = 0; 87 #pragma omp for collapse(2) schedule(runtime) ordered 88 89 // Loop header 90 91 for (unsigned char i = '0' ; i <= '9'; ++i) 92 for (x = -10; x < 10; ++x) { 93 // Start of body: indices are calculated from IV: 94 95 // ... start of ordered region ... 96 // ... loop body ... 97 // End of body: store into a[i]: 98 // ... end of ordered region ... 99 #pragma omp ordered threads 100 a[i] = b[i] * c[i] * d[i]; 101 102 // ... end iteration for ordered loop ... 103 } 104 } 105 106 float f[10]; 107 void foo_simd(int low, int up) { 108 #pragma omp simd 109 for (int i = low; i < up; ++i) { 110 f[i] = 0.0; 111 #pragma omp ordered simd 112 f[i] = 1.0; 113 } 114 #pragma omp for simd ordered 115 for (int i = low; i < up; ++i) { 116 f[i] = 0.0; 117 #pragma omp ordered simd 118 f[i] = 1.0; 119 } 120 } 121 122 123 #endif // HEADER 124 125 // CHECK1-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 126 // CHECK1-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { 127 // CHECK1-NEXT: entry: 128 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 129 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 130 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 131 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 132 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 133 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 134 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 135 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 136 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 137 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 138 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 139 // CHECK1-NORMAL-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 140 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 141 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 142 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 143 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 144 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 145 // CHECK1-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 146 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 147 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 148 // CHECK1-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3:[0-9]+]]) 149 // CHECK1-IRBUILDER-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP0]], i32 66, i32 0, i32 4571423, i32 1, i32 1) 150 // CHECK1-NORMAL-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 66, i32 0, i32 4571423, i32 1, i32 1) 151 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 152 // CHECK1: omp.dispatch.cond: 153 // CHECK1-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3]]) 154 // CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 155 // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 156 // CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 157 // CHECK1: omp.dispatch.body: 158 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 159 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_IV]], align 4 160 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 161 // CHECK1: omp.inner.for.cond: 162 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 163 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 164 // CHECK1-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP3]], [[TMP4]] 165 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 166 // CHECK1: omp.inner.for.body: 167 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 168 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP5]], 7 169 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 170 // CHECK1-NEXT: store i32 [[SUB]], i32* [[I]], align 4 171 // CHECK1-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 172 // CHECK1-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 173 // CHECK1-NEXT: [[TMP6:%.*]] = load float*, float** [[B_ADDR]], align 8 174 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 175 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 176 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP6]], i64 [[IDXPROM]] 177 // CHECK1-NEXT: [[TMP8:%.*]] = load float, float* [[ARRAYIDX]], align 4 178 // CHECK1-NEXT: [[TMP9:%.*]] = load float*, float** [[C_ADDR]], align 8 179 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 180 // CHECK1-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP10]] to i64 181 // CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP9]], i64 [[IDXPROM1]] 182 // CHECK1-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX2]], align 4 183 // CHECK1-NEXT: [[MUL3:%.*]] = fmul float [[TMP8]], [[TMP11]] 184 // CHECK1-NEXT: [[TMP12:%.*]] = load float*, float** [[D_ADDR]], align 8 185 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 186 // CHECK1-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP13]] to i64 187 // CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM4]] 188 // CHECK1-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX5]], align 4 189 // CHECK1-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP14]] 190 // CHECK1-NEXT: [[TMP15:%.*]] = load float*, float** [[A_ADDR]], align 8 191 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 192 // CHECK1-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP16]] to i64 193 // CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM7]] 194 // CHECK1-NEXT: store float [[MUL6]], float* [[ARRAYIDX8]], align 4 195 // CHECK1-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 196 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 197 // CHECK1: omp.body.continue: 198 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 199 // CHECK1: omp.inner.for.inc: 200 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 201 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP17]], 1 202 // CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 203 // CHECK1-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3]]) 204 // CHECK1-NEXT: call void @__kmpc_dispatch_fini_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 205 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 206 // CHECK1: omp.inner.for.end: 207 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 208 // CHECK1: omp.dispatch.inc: 209 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 210 // CHECK1: omp.dispatch.end: 211 // CHECK1-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 212 // CHECK1-IRBUILDER-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4:[0-9]+]], i32 [[TMP0]]) 213 // CHECK1-NORMAL-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP0]]) 214 // CHECK1-NEXT: ret void 215 // 216 // 217 // CHECK1-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_ 218 // CHECK1-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 219 // CHECK1-NEXT: entry: 220 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 221 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 222 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 223 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 224 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 225 // CHECK1-NEXT: [[TMP:%.*]] = alloca i64, align 8 226 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 227 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 228 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 229 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 230 // CHECK1-NEXT: [[I:%.*]] = alloca i64, align 8 231 // CHECK1-NORMAL-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 232 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 233 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 234 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 235 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 236 // CHECK1-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 237 // CHECK1-NEXT: store i64 16908287, i64* [[DOTOMP_UB]], align 8 238 // CHECK1-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 239 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 240 // CHECK1-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB6:[0-9]+]]) 241 // CHECK1-NEXT: call void @__kmpc_dispatch_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1073741891, i64 0, i64 16908287, i64 1, i64 1) 242 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 243 // CHECK1: omp.dispatch.cond: 244 // CHECK1-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB6]]) 245 // CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 246 // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 247 // CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 248 // CHECK1: omp.dispatch.body: 249 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 250 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[DOTOMP_IV]], align 8 251 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 252 // CHECK1: omp.inner.for.cond: 253 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 254 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 255 // CHECK1-NEXT: [[ADD:%.*]] = add i64 [[TMP4]], 1 256 // CHECK1-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP3]], [[ADD]] 257 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 258 // CHECK1: omp.inner.for.body: 259 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 260 // CHECK1-NEXT: [[MUL:%.*]] = mul i64 [[TMP5]], 127 261 // CHECK1-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]] 262 // CHECK1-NEXT: store i64 [[ADD1]], i64* [[I]], align 8 263 // CHECK1-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 264 // CHECK1-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 265 // CHECK1-NEXT: [[TMP6:%.*]] = load float*, float** [[B_ADDR]], align 8 266 // CHECK1-NEXT: [[TMP7:%.*]] = load i64, i64* [[I]], align 8 267 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP6]], i64 [[TMP7]] 268 // CHECK1-NEXT: [[TMP8:%.*]] = load float, float* [[ARRAYIDX]], align 4 269 // CHECK1-NEXT: [[TMP9:%.*]] = load float*, float** [[C_ADDR]], align 8 270 // CHECK1-NEXT: [[TMP10:%.*]] = load i64, i64* [[I]], align 8 271 // CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP9]], i64 [[TMP10]] 272 // CHECK1-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX2]], align 4 273 // CHECK1-NEXT: [[MUL3:%.*]] = fmul float [[TMP8]], [[TMP11]] 274 // CHECK1-NEXT: [[TMP12:%.*]] = load float*, float** [[D_ADDR]], align 8 275 // CHECK1-NEXT: [[TMP13:%.*]] = load i64, i64* [[I]], align 8 276 // CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[TMP13]] 277 // CHECK1-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX4]], align 4 278 // CHECK1-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP14]] 279 // CHECK1-NEXT: [[TMP15:%.*]] = load float*, float** [[A_ADDR]], align 8 280 // CHECK1-NEXT: [[TMP16:%.*]] = load i64, i64* [[I]], align 8 281 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[TMP16]] 282 // CHECK1-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4 283 // CHECK1-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 284 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 285 // CHECK1: omp.body.continue: 286 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 287 // CHECK1: omp.inner.for.inc: 288 // CHECK1-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 289 // CHECK1-NEXT: [[ADD7:%.*]] = add i64 [[TMP17]], 1 290 // CHECK1-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 291 // CHECK1-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB6]]) 292 // CHECK1-NEXT: call void @__kmpc_dispatch_fini_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 293 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 294 // CHECK1: omp.inner.for.end: 295 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 296 // CHECK1: omp.dispatch.inc: 297 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 298 // CHECK1: omp.dispatch.end: 299 // CHECK1-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 300 // CHECK1-IRBUILDER-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[TMP0]]) 301 // CHECK1-NORMAL-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 302 // CHECK1-NEXT: ret void 303 // 304 // 305 // CHECK1-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_ 306 // CHECK1-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 307 // CHECK1-NEXT: entry: 308 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 309 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 310 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 311 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 312 // CHECK1-NEXT: [[X:%.*]] = alloca i32, align 4 313 // CHECK1-NEXT: [[Y:%.*]] = alloca i32, align 4 314 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 315 // CHECK1-NEXT: [[TMP:%.*]] = alloca i8, align 1 316 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 317 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 318 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8 319 // CHECK1-NEXT: [[I:%.*]] = alloca i8, align 1 320 // CHECK1-NEXT: [[X6:%.*]] = alloca i32, align 4 321 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 322 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 323 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 324 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 325 // CHECK1-NEXT: [[I8:%.*]] = alloca i8, align 1 326 // CHECK1-NEXT: [[X9:%.*]] = alloca i32, align 4 327 // CHECK1-NORMAL-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 328 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 329 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 330 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 331 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 332 // CHECK1-NEXT: store i32 0, i32* [[X]], align 4 333 // CHECK1-NEXT: store i32 0, i32* [[Y]], align 4 334 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[Y]], align 4 335 // CHECK1-NEXT: [[CONV:%.*]] = trunc i32 [[TMP1]] to i8 336 // CHECK1-NEXT: store i8 [[CONV]], i8* [[DOTCAPTURE_EXPR_]], align 1 337 // CHECK1-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 338 // CHECK1-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 339 // CHECK1-NEXT: [[SUB:%.*]] = sub i32 57, [[CONV3]] 340 // CHECK1-NEXT: [[ADD:%.*]] = add i32 [[SUB]], 1 341 // CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 342 // CHECK1-NEXT: [[CONV4:%.*]] = zext i32 [[DIV]] to i64 343 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV4]], 11 344 // CHECK1-NEXT: [[SUB5:%.*]] = sub nsw i64 [[MUL]], 1 345 // CHECK1-NEXT: store i64 [[SUB5]], i64* [[DOTCAPTURE_EXPR_2]], align 8 346 // CHECK1-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 347 // CHECK1-NEXT: store i8 [[TMP3]], i8* [[I]], align 1 348 // CHECK1-NEXT: store i32 11, i32* [[X6]], align 4 349 // CHECK1-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 350 // CHECK1-NEXT: [[CONV7:%.*]] = sext i8 [[TMP4]] to i32 351 // CHECK1-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV7]], 57 352 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 353 // CHECK1: omp.precond.then: 354 // CHECK1-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 355 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 356 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_UB]], align 8 357 // CHECK1-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 358 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 359 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 360 // CHECK1-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB8:[0-9]+]]) 361 // CHECK1-NEXT: call void @__kmpc_dispatch_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1073741894, i64 0, i64 [[TMP6]], i64 1, i64 1) 362 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 363 // CHECK1: omp.dispatch.cond: 364 // CHECK1-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB8]]) 365 // CHECK1-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_dispatch_next_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 366 // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0 367 // CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 368 // CHECK1: omp.dispatch.body: 369 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 370 // CHECK1-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 371 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 372 // CHECK1: omp.inner.for.cond: 373 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 374 // CHECK1-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 375 // CHECK1-NEXT: [[CMP10:%.*]] = icmp sle i64 [[TMP9]], [[TMP10]] 376 // CHECK1-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 377 // CHECK1: omp.inner.for.body: 378 // CHECK1-NEXT: [[TMP11:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 379 // CHECK1-NEXT: [[CONV11:%.*]] = sext i8 [[TMP11]] to i64 380 // CHECK1-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 381 // CHECK1-NEXT: [[DIV12:%.*]] = sdiv i64 [[TMP12]], 11 382 // CHECK1-NEXT: [[MUL13:%.*]] = mul nsw i64 [[DIV12]], 1 383 // CHECK1-NEXT: [[ADD14:%.*]] = add nsw i64 [[CONV11]], [[MUL13]] 384 // CHECK1-NEXT: [[CONV15:%.*]] = trunc i64 [[ADD14]] to i8 385 // CHECK1-NEXT: store i8 [[CONV15]], i8* [[I8]], align 1 386 // CHECK1-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 387 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 388 // CHECK1-NEXT: [[DIV16:%.*]] = sdiv i64 [[TMP14]], 11 389 // CHECK1-NEXT: [[MUL17:%.*]] = mul nsw i64 [[DIV16]], 11 390 // CHECK1-NEXT: [[SUB18:%.*]] = sub nsw i64 [[TMP13]], [[MUL17]] 391 // CHECK1-NEXT: [[MUL19:%.*]] = mul nsw i64 [[SUB18]], 1 392 // CHECK1-NEXT: [[SUB20:%.*]] = sub nsw i64 11, [[MUL19]] 393 // CHECK1-NEXT: [[CONV21:%.*]] = trunc i64 [[SUB20]] to i32 394 // CHECK1-NEXT: store i32 [[CONV21]], i32* [[X9]], align 4 395 // CHECK1-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 396 // CHECK1-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 397 // CHECK1-NEXT: [[TMP15:%.*]] = load float*, float** [[B_ADDR]], align 8 398 // CHECK1-NEXT: [[TMP16:%.*]] = load i8, i8* [[I8]], align 1 399 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP16]] to i64 400 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM]] 401 // CHECK1-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4 402 // CHECK1-NEXT: [[TMP18:%.*]] = load float*, float** [[C_ADDR]], align 8 403 // CHECK1-NEXT: [[TMP19:%.*]] = load i8, i8* [[I8]], align 1 404 // CHECK1-NEXT: [[IDXPROM22:%.*]] = sext i8 [[TMP19]] to i64 405 // CHECK1-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM22]] 406 // CHECK1-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX23]], align 4 407 // CHECK1-NEXT: [[MUL24:%.*]] = fmul float [[TMP17]], [[TMP20]] 408 // CHECK1-NEXT: [[TMP21:%.*]] = load float*, float** [[D_ADDR]], align 8 409 // CHECK1-NEXT: [[TMP22:%.*]] = load i8, i8* [[I8]], align 1 410 // CHECK1-NEXT: [[IDXPROM25:%.*]] = sext i8 [[TMP22]] to i64 411 // CHECK1-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM25]] 412 // CHECK1-NEXT: [[TMP23:%.*]] = load float, float* [[ARRAYIDX26]], align 4 413 // CHECK1-NEXT: [[MUL27:%.*]] = fmul float [[MUL24]], [[TMP23]] 414 // CHECK1-NEXT: [[TMP24:%.*]] = load float*, float** [[A_ADDR]], align 8 415 // CHECK1-NEXT: [[TMP25:%.*]] = load i8, i8* [[I8]], align 1 416 // CHECK1-NEXT: [[IDXPROM28:%.*]] = sext i8 [[TMP25]] to i64 417 // CHECK1-NEXT: [[ARRAYIDX29:%.*]] = getelementptr inbounds float, float* [[TMP24]], i64 [[IDXPROM28]] 418 // CHECK1-NEXT: store float [[MUL27]], float* [[ARRAYIDX29]], align 4 419 // CHECK1-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 420 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 421 // CHECK1: omp.body.continue: 422 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 423 // CHECK1: omp.inner.for.inc: 424 // CHECK1-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 425 // CHECK1-NEXT: [[ADD30:%.*]] = add nsw i64 [[TMP26]], 1 426 // CHECK1-NEXT: store i64 [[ADD30]], i64* [[DOTOMP_IV]], align 8 427 // CHECK1-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB8]]) 428 // CHECK1-NEXT: call void @__kmpc_dispatch_fini_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 429 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 430 // CHECK1: omp.inner.for.end: 431 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 432 // CHECK1: omp.dispatch.inc: 433 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 434 // CHECK1: omp.dispatch.end: 435 // CHECK1-NEXT: br label [[OMP_PRECOND_END]] 436 // CHECK1: omp.precond.end: 437 // CHECK1-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 438 // CHECK1-IRBUILDER-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[TMP0]]) 439 // CHECK1-NORMAL-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 440 // CHECK1-NEXT: ret void 441 // 442 // 443 // CHECK1-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_ 444 // CHECK1-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 445 // CHECK1-NEXT: entry: 446 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 447 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 448 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 449 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 450 // CHECK1-NEXT: [[X:%.*]] = alloca i32, align 4 451 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 452 // CHECK1-NEXT: [[TMP:%.*]] = alloca i8, align 1 453 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 454 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 455 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 456 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 457 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 458 // CHECK1-NEXT: [[I:%.*]] = alloca i8, align 1 459 // CHECK1-NEXT: [[X2:%.*]] = alloca i32, align 4 460 // CHECK1-NORMAL-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 461 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 462 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 463 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 464 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 465 // CHECK1-NEXT: store i32 0, i32* [[X]], align 4 466 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 467 // CHECK1-NEXT: store i32 199, i32* [[DOTOMP_UB]], align 4 468 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 469 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 470 // CHECK1-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB10:[0-9]+]]) 471 // CHECK1-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1073741893, i32 0, i32 199, i32 1, i32 1) 472 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 473 // CHECK1: omp.dispatch.cond: 474 // CHECK1-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB10]]) 475 // CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 476 // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 477 // CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 478 // CHECK1: omp.dispatch.body: 479 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 480 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_IV]], align 4 481 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 482 // CHECK1: omp.inner.for.cond: 483 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 484 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 485 // CHECK1-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP3]], [[TMP4]] 486 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 487 // CHECK1: omp.inner.for.body: 488 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 489 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 20 490 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 491 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 48, [[MUL]] 492 // CHECK1-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i8 493 // CHECK1-NEXT: store i8 [[CONV]], i8* [[I]], align 1 494 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 495 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 496 // CHECK1-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP7]], 20 497 // CHECK1-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 20 498 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP6]], [[MUL4]] 499 // CHECK1-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 500 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 -10, [[MUL5]] 501 // CHECK1-NEXT: store i32 [[ADD6]], i32* [[X2]], align 4 502 // CHECK1-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 503 // CHECK1-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 504 // CHECK1-NEXT: [[TMP8:%.*]] = load float*, float** [[B_ADDR]], align 8 505 // CHECK1-NEXT: [[TMP9:%.*]] = load i8, i8* [[I]], align 1 506 // CHECK1-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP9]] to i64 507 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[IDXPROM]] 508 // CHECK1-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX]], align 4 509 // CHECK1-NEXT: [[TMP11:%.*]] = load float*, float** [[C_ADDR]], align 8 510 // CHECK1-NEXT: [[TMP12:%.*]] = load i8, i8* [[I]], align 1 511 // CHECK1-NEXT: [[IDXPROM7:%.*]] = zext i8 [[TMP12]] to i64 512 // CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[IDXPROM7]] 513 // CHECK1-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX8]], align 4 514 // CHECK1-NEXT: [[MUL9:%.*]] = fmul float [[TMP10]], [[TMP13]] 515 // CHECK1-NEXT: [[TMP14:%.*]] = load float*, float** [[D_ADDR]], align 8 516 // CHECK1-NEXT: [[TMP15:%.*]] = load i8, i8* [[I]], align 1 517 // CHECK1-NEXT: [[IDXPROM10:%.*]] = zext i8 [[TMP15]] to i64 518 // CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM10]] 519 // CHECK1-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX11]], align 4 520 // CHECK1-NEXT: [[MUL12:%.*]] = fmul float [[MUL9]], [[TMP16]] 521 // CHECK1-NEXT: [[TMP17:%.*]] = load float*, float** [[A_ADDR]], align 8 522 // CHECK1-NEXT: [[TMP18:%.*]] = load i8, i8* [[I]], align 1 523 // CHECK1-NEXT: [[IDXPROM13:%.*]] = zext i8 [[TMP18]] to i64 524 // CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM13]] 525 // CHECK1-NEXT: store float [[MUL12]], float* [[ARRAYIDX14]], align 4 526 // CHECK1-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 527 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 528 // CHECK1: omp.body.continue: 529 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 530 // CHECK1: omp.inner.for.inc: 531 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 532 // CHECK1-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP19]], 1 533 // CHECK1-NEXT: store i32 [[ADD15]], i32* [[DOTOMP_IV]], align 4 534 // CHECK1-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB10]]) 535 // CHECK1-NEXT: call void @__kmpc_dispatch_fini_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 536 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 537 // CHECK1: omp.inner.for.end: 538 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 539 // CHECK1: omp.dispatch.inc: 540 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 541 // CHECK1: omp.dispatch.end: 542 // CHECK1-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 543 // CHECK1-IRBUILDER-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[TMP0]]) 544 // CHECK1-NORMAL-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 545 // CHECK1-NEXT: ret void 546 // 547 // 548 // CHECK1-LABEL: define {{[^@]+}}@_Z8foo_simdii 549 // CHECK1-SAME: (i32 [[LOW:%.*]], i32 [[UP:%.*]]) #[[ATTR0]] { 550 // CHECK1-NEXT: entry: 551 // CHECK1-NEXT: [[LOW_ADDR:%.*]] = alloca i32, align 4 552 // CHECK1-NEXT: [[UP_ADDR:%.*]] = alloca i32, align 4 553 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 554 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 555 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 556 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 557 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 558 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 559 // CHECK1-NEXT: [[I5:%.*]] = alloca i32, align 4 560 // CHECK1-NEXT: [[DOTOMP_IV16:%.*]] = alloca i32, align 4 561 // CHECK1-NEXT: [[_TMP17:%.*]] = alloca i32, align 4 562 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_18:%.*]] = alloca i32, align 4 563 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_19:%.*]] = alloca i32, align 4 564 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_20:%.*]] = alloca i32, align 4 565 // CHECK1-NEXT: [[I26:%.*]] = alloca i32, align 4 566 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 567 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 568 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 569 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 570 // CHECK1-NEXT: [[I28:%.*]] = alloca i32, align 4 571 // CHECK1-NORMAL-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 572 // CHECK1-NEXT: store i32 [[LOW]], i32* [[LOW_ADDR]], align 4 573 // CHECK1-NEXT: store i32 [[UP]], i32* [[UP_ADDR]], align 4 574 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[LOW_ADDR]], align 4 575 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 576 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[UP_ADDR]], align 4 577 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 578 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 579 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 580 // CHECK1-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] 581 // CHECK1-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1 582 // CHECK1-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1 583 // CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 584 // CHECK1-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1 585 // CHECK1-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4 586 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 587 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 588 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 589 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 590 // CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] 591 // CHECK1-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]] 592 // CHECK1: simd.if.then: 593 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IV]], align 4 594 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 595 // CHECK1: omp.inner.for.cond: 596 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 597 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !3 598 // CHECK1-NEXT: [[ADD6:%.*]] = add i32 [[TMP9]], 1 599 // CHECK1-NEXT: [[CMP7:%.*]] = icmp ult i32 [[TMP8]], [[ADD6]] 600 // CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 601 // CHECK1: omp.inner.for.body: 602 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !3 603 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 604 // CHECK1-NEXT: [[MUL:%.*]] = mul i32 [[TMP11]], 1 605 // CHECK1-NEXT: [[ADD8:%.*]] = add i32 [[TMP10]], [[MUL]] 606 // CHECK1-NEXT: store i32 [[ADD8]], i32* [[I5]], align 4, !llvm.access.group !3 607 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[I5]], align 4, !llvm.access.group !3 608 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64 609 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM]] 610 // CHECK1-NEXT: store float 0.000000e+00, float* [[ARRAYIDX]], align 4, !llvm.access.group !3 611 // CHECK1-NEXT: call void @__captured_stmt(i32* [[I5]]), !llvm.access.group !3 612 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 613 // CHECK1: omp.body.continue: 614 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 615 // CHECK1: omp.inner.for.inc: 616 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 617 // CHECK1-NEXT: [[ADD9:%.*]] = add i32 [[TMP13]], 1 618 // CHECK1-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 619 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 620 // CHECK1: omp.inner.for.end: 621 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 622 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 623 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 624 // CHECK1-NEXT: [[SUB10:%.*]] = sub i32 [[TMP15]], [[TMP16]] 625 // CHECK1-NEXT: [[SUB11:%.*]] = sub i32 [[SUB10]], 1 626 // CHECK1-NEXT: [[ADD12:%.*]] = add i32 [[SUB11]], 1 627 // CHECK1-NEXT: [[DIV13:%.*]] = udiv i32 [[ADD12]], 1 628 // CHECK1-NEXT: [[MUL14:%.*]] = mul i32 [[DIV13]], 1 629 // CHECK1-NEXT: [[ADD15:%.*]] = add i32 [[TMP14]], [[MUL14]] 630 // CHECK1-NEXT: store i32 [[ADD15]], i32* [[I5]], align 4 631 // CHECK1-NEXT: br label [[SIMD_IF_END]] 632 // CHECK1: simd.if.end: 633 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[LOW_ADDR]], align 4 634 // CHECK1-NEXT: store i32 [[TMP17]], i32* [[DOTCAPTURE_EXPR_18]], align 4 635 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[UP_ADDR]], align 4 636 // CHECK1-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_19]], align 4 637 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 638 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 639 // CHECK1-NEXT: [[SUB21:%.*]] = sub i32 [[TMP19]], [[TMP20]] 640 // CHECK1-NEXT: [[SUB22:%.*]] = sub i32 [[SUB21]], 1 641 // CHECK1-NEXT: [[ADD23:%.*]] = add i32 [[SUB22]], 1 642 // CHECK1-NEXT: [[DIV24:%.*]] = udiv i32 [[ADD23]], 1 643 // CHECK1-NEXT: [[SUB25:%.*]] = sub i32 [[DIV24]], 1 644 // CHECK1-NEXT: store i32 [[SUB25]], i32* [[DOTCAPTURE_EXPR_20]], align 4 645 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 646 // CHECK1-NEXT: store i32 [[TMP21]], i32* [[I26]], align 4 647 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 648 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 649 // CHECK1-NEXT: [[CMP27:%.*]] = icmp slt i32 [[TMP22]], [[TMP23]] 650 // CHECK1-NEXT: br i1 [[CMP27]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 651 // CHECK1: omp.precond.then: 652 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 653 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_20]], align 4 654 // CHECK1-NEXT: store i32 [[TMP24]], i32* [[DOTOMP_UB]], align 4 655 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 656 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 657 // CHECK1-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_20]], align 4 658 // CHECK1-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB12:[0-9]+]]) 659 // CHECK1-NEXT: call void @__kmpc_dispatch_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 66, i32 0, i32 [[TMP25]], i32 1, i32 1) 660 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 661 // CHECK1: omp.dispatch.cond: 662 // CHECK1-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB12]]) 663 // CHECK1-NEXT: [[TMP26:%.*]] = call i32 @__kmpc_dispatch_next_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 664 // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP26]], 0 665 // CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 666 // CHECK1: omp.dispatch.body: 667 // CHECK1-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 668 // CHECK1-NEXT: store i32 [[TMP27]], i32* [[DOTOMP_IV16]], align 4 669 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND29:%.*]] 670 // CHECK1-IRBUILDER: omp.inner.for.cond30: 671 // CHECK1-NORMAL: omp.inner.for.cond29: 672 // CHECK1-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV16]], align 4, !llvm.access.group !7 673 // CHECK1-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !7 674 // CHECK1-NEXT: [[ADD30:%.*]] = add i32 [[TMP29]], 1 675 // CHECK1-NEXT: [[CMP31:%.*]] = icmp ult i32 [[TMP28]], [[ADD30]] 676 // CHECK1-NEXT: br i1 [[CMP31]], label [[OMP_INNER_FOR_BODY32:%.*]], label [[OMP_INNER_FOR_END40:%.*]] 677 // CHECK1-IRBUILDER: omp.inner.for.body33: 678 // CHECK1-NORMAL: omp.inner.for.body32: 679 // CHECK1-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4, !llvm.access.group !7 680 // CHECK1-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV16]], align 4, !llvm.access.group !7 681 // CHECK1-NEXT: [[MUL33:%.*]] = mul i32 [[TMP31]], 1 682 // CHECK1-NEXT: [[ADD34:%.*]] = add i32 [[TMP30]], [[MUL33]] 683 // CHECK1-NEXT: store i32 [[ADD34]], i32* [[I28]], align 4, !llvm.access.group !7 684 // CHECK1-NEXT: [[TMP32:%.*]] = load i32, i32* [[I28]], align 4, !llvm.access.group !7 685 // CHECK1-NEXT: [[IDXPROM35:%.*]] = sext i32 [[TMP32]] to i64 686 // CHECK1-NEXT: [[ARRAYIDX36:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM35]] 687 // CHECK1-NEXT: store float 0.000000e+00, float* [[ARRAYIDX36]], align 4, !llvm.access.group !7 688 // CHECK1-NEXT: call void @__captured_stmt.1(i32* [[I28]]), !llvm.access.group !7 689 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE37:%.*]] 690 // CHECK1-IRBUILDER: omp.body.continue38: 691 // CHECK1-NORMAL: omp.body.continue37: 692 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC38:%.*]] 693 // CHECK1-IRBUILDER: omp.inner.for.inc39: 694 // CHECK1-NORMAL: omp.inner.for.inc38: 695 // CHECK1-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_IV16]], align 4, !llvm.access.group !7 696 // CHECK1-NEXT: [[ADD39:%.*]] = add i32 [[TMP33]], 1 697 // CHECK1-NEXT: store i32 [[ADD39]], i32* [[DOTOMP_IV16]], align 4, !llvm.access.group !7 698 // CHECK1-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB12]]) 699 // CHECK1-NEXT: call void @__kmpc_dispatch_fini_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]), !llvm.access.group !7 700 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND29]], !llvm.loop [[LOOP8:![0-9]+]] 701 // CHECK1-IRBUILDER: omp.inner.for.end42: 702 // CHECK1-NORMAL: omp.inner.for.end40: 703 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 704 // CHECK1: omp.dispatch.inc: 705 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 706 // CHECK1: omp.dispatch.end: 707 // CHECK1-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 708 // CHECK1-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 709 // CHECK1-NEXT: br i1 [[TMP35]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 710 // CHECK1: .omp.final.then: 711 // CHECK1-NEXT: [[TMP36:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 712 // CHECK1-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 713 // CHECK1-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 714 // CHECK1-NEXT: [[SUB41:%.*]] = sub i32 [[TMP37]], [[TMP38]] 715 // CHECK1-NEXT: [[SUB42:%.*]] = sub i32 [[SUB41]], 1 716 // CHECK1-NEXT: [[ADD43:%.*]] = add i32 [[SUB42]], 1 717 // CHECK1-NEXT: [[DIV44:%.*]] = udiv i32 [[ADD43]], 1 718 // CHECK1-NEXT: [[MUL45:%.*]] = mul i32 [[DIV44]], 1 719 // CHECK1-NEXT: [[ADD46:%.*]] = add i32 [[TMP36]], [[MUL45]] 720 // CHECK1-NEXT: store i32 [[ADD46]], i32* [[I28]], align 4 721 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 722 // CHECK1: .omp.final.done: 723 // CHECK1-NEXT: br label [[OMP_PRECOND_END]] 724 // CHECK1: omp.precond.end: 725 // CHECK1-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 726 // CHECK1-IRBUILDER-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[TMP0]]) 727 // CHECK1-NORMAL-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 728 // CHECK1-NEXT: ret void 729 // 730 // 731 // CHECK1-LABEL: define {{[^@]+}}@__captured_stmt 732 // CHECK1-SAME: (i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR3:[0-9]+]] { 733 // CHECK1-NEXT: entry: 734 // CHECK1-NEXT: [[I_ADDR:%.*]] = alloca i32*, align 8 735 // CHECK1-NEXT: store i32* [[I]], i32** [[I_ADDR]], align 8 736 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[I_ADDR]], align 8 737 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 738 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 739 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM]] 740 // CHECK1-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 741 // CHECK1-NEXT: ret void 742 // 743 // 744 // CHECK1-LABEL: define {{[^@]+}}@__captured_stmt.1 745 // CHECK1-SAME: (i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR3]] { 746 // CHECK1-NEXT: entry: 747 // CHECK1-NEXT: [[I_ADDR:%.*]] = alloca i32*, align 8 748 // CHECK1-NEXT: store i32* [[I]], i32** [[I_ADDR]], align 8 749 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[I_ADDR]], align 8 750 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 751 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 752 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM]] 753 // CHECK1-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 754 // CHECK1-NEXT: ret void 755 // 756 // 757 // CHECK2-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 758 // CHECK2-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { 759 // CHECK2-NEXT: entry: 760 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 761 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 762 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 763 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 764 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 765 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 766 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 767 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 768 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 769 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 770 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 771 // CHECK2-NORMAL-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 772 // CHECK2-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 773 // CHECK2-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 774 // CHECK2-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 775 // CHECK2-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 776 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 777 // CHECK2-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 778 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 779 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 780 // CHECK2-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3:[0-9]+]]) 781 // CHECK2-IRBUILDER-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP0]], i32 66, i32 0, i32 4571423, i32 1, i32 1) 782 // CHECK2-NORMAL-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 66, i32 0, i32 4571423, i32 1, i32 1) 783 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 784 // CHECK2: omp.dispatch.cond: 785 // CHECK2-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3]]) 786 // CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 787 // CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 788 // CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 789 // CHECK2: omp.dispatch.body: 790 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 791 // CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_IV]], align 4 792 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 793 // CHECK2: omp.inner.for.cond: 794 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 795 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 796 // CHECK2-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP3]], [[TMP4]] 797 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 798 // CHECK2: omp.inner.for.body: 799 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 800 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP5]], 7 801 // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 802 // CHECK2-NEXT: store i32 [[SUB]], i32* [[I]], align 4 803 // CHECK2-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 804 // CHECK2-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 805 // CHECK2-NEXT: [[TMP6:%.*]] = load float*, float** [[B_ADDR]], align 8 806 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 807 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 808 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP6]], i64 [[IDXPROM]] 809 // CHECK2-NEXT: [[TMP8:%.*]] = load float, float* [[ARRAYIDX]], align 4 810 // CHECK2-NEXT: [[TMP9:%.*]] = load float*, float** [[C_ADDR]], align 8 811 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 812 // CHECK2-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP10]] to i64 813 // CHECK2-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP9]], i64 [[IDXPROM1]] 814 // CHECK2-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX2]], align 4 815 // CHECK2-NEXT: [[MUL3:%.*]] = fmul float [[TMP8]], [[TMP11]] 816 // CHECK2-NEXT: [[TMP12:%.*]] = load float*, float** [[D_ADDR]], align 8 817 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 818 // CHECK2-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP13]] to i64 819 // CHECK2-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM4]] 820 // CHECK2-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX5]], align 4 821 // CHECK2-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP14]] 822 // CHECK2-NEXT: [[TMP15:%.*]] = load float*, float** [[A_ADDR]], align 8 823 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 824 // CHECK2-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP16]] to i64 825 // CHECK2-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM7]] 826 // CHECK2-NEXT: store float [[MUL6]], float* [[ARRAYIDX8]], align 4 827 // CHECK2-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 828 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 829 // CHECK2: omp.body.continue: 830 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 831 // CHECK2: omp.inner.for.inc: 832 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 833 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP17]], 1 834 // CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 835 // CHECK2-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3]]) 836 // CHECK2-NEXT: call void @__kmpc_dispatch_fini_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 837 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 838 // CHECK2: omp.inner.for.end: 839 // CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 840 // CHECK2: omp.dispatch.inc: 841 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND]] 842 // CHECK2: omp.dispatch.end: 843 // CHECK2-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 844 // CHECK2-IRBUILDER-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4:[0-9]+]], i32 [[TMP0]]) 845 // CHECK2-NORMAL-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP0]]) 846 // CHECK2-NEXT: ret void 847 // 848 // 849 // CHECK2-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_ 850 // CHECK2-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 851 // CHECK2-NEXT: entry: 852 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 853 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 854 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 855 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 856 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 857 // CHECK2-NEXT: [[TMP:%.*]] = alloca i64, align 8 858 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 859 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 860 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 861 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 862 // CHECK2-NEXT: [[I:%.*]] = alloca i64, align 8 863 // CHECK2-NORMAL-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 864 // CHECK2-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 865 // CHECK2-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 866 // CHECK2-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 867 // CHECK2-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 868 // CHECK2-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 869 // CHECK2-NEXT: store i64 16908287, i64* [[DOTOMP_UB]], align 8 870 // CHECK2-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 871 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 872 // CHECK2-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB6:[0-9]+]]) 873 // CHECK2-NEXT: call void @__kmpc_dispatch_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1073741891, i64 0, i64 16908287, i64 1, i64 1) 874 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 875 // CHECK2: omp.dispatch.cond: 876 // CHECK2-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB6]]) 877 // CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 878 // CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 879 // CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 880 // CHECK2: omp.dispatch.body: 881 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 882 // CHECK2-NEXT: store i64 [[TMP2]], i64* [[DOTOMP_IV]], align 8 883 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 884 // CHECK2: omp.inner.for.cond: 885 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 886 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 887 // CHECK2-NEXT: [[ADD:%.*]] = add i64 [[TMP4]], 1 888 // CHECK2-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP3]], [[ADD]] 889 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 890 // CHECK2: omp.inner.for.body: 891 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 892 // CHECK2-NEXT: [[MUL:%.*]] = mul i64 [[TMP5]], 127 893 // CHECK2-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]] 894 // CHECK2-NEXT: store i64 [[ADD1]], i64* [[I]], align 8 895 // CHECK2-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 896 // CHECK2-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 897 // CHECK2-NEXT: [[TMP6:%.*]] = load float*, float** [[B_ADDR]], align 8 898 // CHECK2-NEXT: [[TMP7:%.*]] = load i64, i64* [[I]], align 8 899 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP6]], i64 [[TMP7]] 900 // CHECK2-NEXT: [[TMP8:%.*]] = load float, float* [[ARRAYIDX]], align 4 901 // CHECK2-NEXT: [[TMP9:%.*]] = load float*, float** [[C_ADDR]], align 8 902 // CHECK2-NEXT: [[TMP10:%.*]] = load i64, i64* [[I]], align 8 903 // CHECK2-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP9]], i64 [[TMP10]] 904 // CHECK2-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX2]], align 4 905 // CHECK2-NEXT: [[MUL3:%.*]] = fmul float [[TMP8]], [[TMP11]] 906 // CHECK2-NEXT: [[TMP12:%.*]] = load float*, float** [[D_ADDR]], align 8 907 // CHECK2-NEXT: [[TMP13:%.*]] = load i64, i64* [[I]], align 8 908 // CHECK2-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[TMP13]] 909 // CHECK2-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX4]], align 4 910 // CHECK2-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP14]] 911 // CHECK2-NEXT: [[TMP15:%.*]] = load float*, float** [[A_ADDR]], align 8 912 // CHECK2-NEXT: [[TMP16:%.*]] = load i64, i64* [[I]], align 8 913 // CHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[TMP16]] 914 // CHECK2-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4 915 // CHECK2-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 916 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 917 // CHECK2: omp.body.continue: 918 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 919 // CHECK2: omp.inner.for.inc: 920 // CHECK2-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 921 // CHECK2-NEXT: [[ADD7:%.*]] = add i64 [[TMP17]], 1 922 // CHECK2-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 923 // CHECK2-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB6]]) 924 // CHECK2-NEXT: call void @__kmpc_dispatch_fini_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 925 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 926 // CHECK2: omp.inner.for.end: 927 // CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 928 // CHECK2: omp.dispatch.inc: 929 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND]] 930 // CHECK2: omp.dispatch.end: 931 // CHECK2-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 932 // CHECK2-IRBUILDER-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[TMP0]]) 933 // CHECK2-NORMAL-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 934 // CHECK2-NEXT: ret void 935 // 936 // 937 // CHECK2-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_ 938 // CHECK2-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 939 // CHECK2-NEXT: entry: 940 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 941 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 942 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 943 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 944 // CHECK2-NEXT: [[X:%.*]] = alloca i32, align 4 945 // CHECK2-NEXT: [[Y:%.*]] = alloca i32, align 4 946 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 947 // CHECK2-NEXT: [[TMP:%.*]] = alloca i8, align 1 948 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 949 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 950 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8 951 // CHECK2-NEXT: [[I:%.*]] = alloca i8, align 1 952 // CHECK2-NEXT: [[X6:%.*]] = alloca i32, align 4 953 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 954 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 955 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 956 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 957 // CHECK2-NEXT: [[I8:%.*]] = alloca i8, align 1 958 // CHECK2-NEXT: [[X9:%.*]] = alloca i32, align 4 959 // CHECK2-NORMAL-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 960 // CHECK2-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 961 // CHECK2-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 962 // CHECK2-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 963 // CHECK2-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 964 // CHECK2-NEXT: store i32 0, i32* [[X]], align 4 965 // CHECK2-NEXT: store i32 0, i32* [[Y]], align 4 966 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[Y]], align 4 967 // CHECK2-NEXT: [[CONV:%.*]] = trunc i32 [[TMP1]] to i8 968 // CHECK2-NEXT: store i8 [[CONV]], i8* [[DOTCAPTURE_EXPR_]], align 1 969 // CHECK2-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 970 // CHECK2-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 971 // CHECK2-NEXT: [[SUB:%.*]] = sub i32 57, [[CONV3]] 972 // CHECK2-NEXT: [[ADD:%.*]] = add i32 [[SUB]], 1 973 // CHECK2-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 974 // CHECK2-NEXT: [[CONV4:%.*]] = zext i32 [[DIV]] to i64 975 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV4]], 11 976 // CHECK2-NEXT: [[SUB5:%.*]] = sub nsw i64 [[MUL]], 1 977 // CHECK2-NEXT: store i64 [[SUB5]], i64* [[DOTCAPTURE_EXPR_2]], align 8 978 // CHECK2-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 979 // CHECK2-NEXT: store i8 [[TMP3]], i8* [[I]], align 1 980 // CHECK2-NEXT: store i32 11, i32* [[X6]], align 4 981 // CHECK2-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 982 // CHECK2-NEXT: [[CONV7:%.*]] = sext i8 [[TMP4]] to i32 983 // CHECK2-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV7]], 57 984 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 985 // CHECK2: omp.precond.then: 986 // CHECK2-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 987 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 988 // CHECK2-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_UB]], align 8 989 // CHECK2-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 990 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 991 // CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 992 // CHECK2-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB8:[0-9]+]]) 993 // CHECK2-NEXT: call void @__kmpc_dispatch_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1073741894, i64 0, i64 [[TMP6]], i64 1, i64 1) 994 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 995 // CHECK2: omp.dispatch.cond: 996 // CHECK2-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB8]]) 997 // CHECK2-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_dispatch_next_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 998 // CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0 999 // CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 1000 // CHECK2: omp.dispatch.body: 1001 // CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 1002 // CHECK2-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 1003 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1004 // CHECK2: omp.inner.for.cond: 1005 // CHECK2-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1006 // CHECK2-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1007 // CHECK2-NEXT: [[CMP10:%.*]] = icmp sle i64 [[TMP9]], [[TMP10]] 1008 // CHECK2-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1009 // CHECK2: omp.inner.for.body: 1010 // CHECK2-NEXT: [[TMP11:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 1011 // CHECK2-NEXT: [[CONV11:%.*]] = sext i8 [[TMP11]] to i64 1012 // CHECK2-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1013 // CHECK2-NEXT: [[DIV12:%.*]] = sdiv i64 [[TMP12]], 11 1014 // CHECK2-NEXT: [[MUL13:%.*]] = mul nsw i64 [[DIV12]], 1 1015 // CHECK2-NEXT: [[ADD14:%.*]] = add nsw i64 [[CONV11]], [[MUL13]] 1016 // CHECK2-NEXT: [[CONV15:%.*]] = trunc i64 [[ADD14]] to i8 1017 // CHECK2-NEXT: store i8 [[CONV15]], i8* [[I8]], align 1 1018 // CHECK2-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1019 // CHECK2-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1020 // CHECK2-NEXT: [[DIV16:%.*]] = sdiv i64 [[TMP14]], 11 1021 // CHECK2-NEXT: [[MUL17:%.*]] = mul nsw i64 [[DIV16]], 11 1022 // CHECK2-NEXT: [[SUB18:%.*]] = sub nsw i64 [[TMP13]], [[MUL17]] 1023 // CHECK2-NEXT: [[MUL19:%.*]] = mul nsw i64 [[SUB18]], 1 1024 // CHECK2-NEXT: [[SUB20:%.*]] = sub nsw i64 11, [[MUL19]] 1025 // CHECK2-NEXT: [[CONV21:%.*]] = trunc i64 [[SUB20]] to i32 1026 // CHECK2-NEXT: store i32 [[CONV21]], i32* [[X9]], align 4 1027 // CHECK2-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1028 // CHECK2-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 1029 // CHECK2-NEXT: [[TMP15:%.*]] = load float*, float** [[B_ADDR]], align 8 1030 // CHECK2-NEXT: [[TMP16:%.*]] = load i8, i8* [[I8]], align 1 1031 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP16]] to i64 1032 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM]] 1033 // CHECK2-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4 1034 // CHECK2-NEXT: [[TMP18:%.*]] = load float*, float** [[C_ADDR]], align 8 1035 // CHECK2-NEXT: [[TMP19:%.*]] = load i8, i8* [[I8]], align 1 1036 // CHECK2-NEXT: [[IDXPROM22:%.*]] = sext i8 [[TMP19]] to i64 1037 // CHECK2-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM22]] 1038 // CHECK2-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX23]], align 4 1039 // CHECK2-NEXT: [[MUL24:%.*]] = fmul float [[TMP17]], [[TMP20]] 1040 // CHECK2-NEXT: [[TMP21:%.*]] = load float*, float** [[D_ADDR]], align 8 1041 // CHECK2-NEXT: [[TMP22:%.*]] = load i8, i8* [[I8]], align 1 1042 // CHECK2-NEXT: [[IDXPROM25:%.*]] = sext i8 [[TMP22]] to i64 1043 // CHECK2-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM25]] 1044 // CHECK2-NEXT: [[TMP23:%.*]] = load float, float* [[ARRAYIDX26]], align 4 1045 // CHECK2-NEXT: [[MUL27:%.*]] = fmul float [[MUL24]], [[TMP23]] 1046 // CHECK2-NEXT: [[TMP24:%.*]] = load float*, float** [[A_ADDR]], align 8 1047 // CHECK2-NEXT: [[TMP25:%.*]] = load i8, i8* [[I8]], align 1 1048 // CHECK2-NEXT: [[IDXPROM28:%.*]] = sext i8 [[TMP25]] to i64 1049 // CHECK2-NEXT: [[ARRAYIDX29:%.*]] = getelementptr inbounds float, float* [[TMP24]], i64 [[IDXPROM28]] 1050 // CHECK2-NEXT: store float [[MUL27]], float* [[ARRAYIDX29]], align 4 1051 // CHECK2-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 1052 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1053 // CHECK2: omp.body.continue: 1054 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1055 // CHECK2: omp.inner.for.inc: 1056 // CHECK2-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1057 // CHECK2-NEXT: [[ADD30:%.*]] = add nsw i64 [[TMP26]], 1 1058 // CHECK2-NEXT: store i64 [[ADD30]], i64* [[DOTOMP_IV]], align 8 1059 // CHECK2-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB8]]) 1060 // CHECK2-NEXT: call void @__kmpc_dispatch_fini_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 1061 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 1062 // CHECK2: omp.inner.for.end: 1063 // CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1064 // CHECK2: omp.dispatch.inc: 1065 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND]] 1066 // CHECK2: omp.dispatch.end: 1067 // CHECK2-NEXT: br label [[OMP_PRECOND_END]] 1068 // CHECK2: omp.precond.end: 1069 // CHECK2-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1070 // CHECK2-IRBUILDER-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[TMP0]]) 1071 // CHECK2-NORMAL-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 1072 // CHECK2-NEXT: ret void 1073 // 1074 // 1075 // CHECK2-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_ 1076 // CHECK2-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 1077 // CHECK2-NEXT: entry: 1078 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 1079 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 1080 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 1081 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 1082 // CHECK2-NEXT: [[X:%.*]] = alloca i32, align 4 1083 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1084 // CHECK2-NEXT: [[TMP:%.*]] = alloca i8, align 1 1085 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1086 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1087 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1088 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1089 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1090 // CHECK2-NEXT: [[I:%.*]] = alloca i8, align 1 1091 // CHECK2-NEXT: [[X2:%.*]] = alloca i32, align 4 1092 // CHECK2-NORMAL-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1093 // CHECK2-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 1094 // CHECK2-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 1095 // CHECK2-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 1096 // CHECK2-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 1097 // CHECK2-NEXT: store i32 0, i32* [[X]], align 4 1098 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1099 // CHECK2-NEXT: store i32 199, i32* [[DOTOMP_UB]], align 4 1100 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1101 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1102 // CHECK2-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB10:[0-9]+]]) 1103 // CHECK2-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1073741893, i32 0, i32 199, i32 1, i32 1) 1104 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 1105 // CHECK2: omp.dispatch.cond: 1106 // CHECK2-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB10]]) 1107 // CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 1108 // CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 1109 // CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 1110 // CHECK2: omp.dispatch.body: 1111 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1112 // CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_IV]], align 4 1113 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1114 // CHECK2: omp.inner.for.cond: 1115 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1116 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1117 // CHECK2-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP3]], [[TMP4]] 1118 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1119 // CHECK2: omp.inner.for.body: 1120 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1121 // CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 20 1122 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 1123 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 48, [[MUL]] 1124 // CHECK2-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i8 1125 // CHECK2-NEXT: store i8 [[CONV]], i8* [[I]], align 1 1126 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1127 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1128 // CHECK2-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP7]], 20 1129 // CHECK2-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 20 1130 // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP6]], [[MUL4]] 1131 // CHECK2-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 1132 // CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 -10, [[MUL5]] 1133 // CHECK2-NEXT: store i32 [[ADD6]], i32* [[X2]], align 4 1134 // CHECK2-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1135 // CHECK2-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 1136 // CHECK2-NEXT: [[TMP8:%.*]] = load float*, float** [[B_ADDR]], align 8 1137 // CHECK2-NEXT: [[TMP9:%.*]] = load i8, i8* [[I]], align 1 1138 // CHECK2-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP9]] to i64 1139 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[IDXPROM]] 1140 // CHECK2-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX]], align 4 1141 // CHECK2-NEXT: [[TMP11:%.*]] = load float*, float** [[C_ADDR]], align 8 1142 // CHECK2-NEXT: [[TMP12:%.*]] = load i8, i8* [[I]], align 1 1143 // CHECK2-NEXT: [[IDXPROM7:%.*]] = zext i8 [[TMP12]] to i64 1144 // CHECK2-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[IDXPROM7]] 1145 // CHECK2-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX8]], align 4 1146 // CHECK2-NEXT: [[MUL9:%.*]] = fmul float [[TMP10]], [[TMP13]] 1147 // CHECK2-NEXT: [[TMP14:%.*]] = load float*, float** [[D_ADDR]], align 8 1148 // CHECK2-NEXT: [[TMP15:%.*]] = load i8, i8* [[I]], align 1 1149 // CHECK2-NEXT: [[IDXPROM10:%.*]] = zext i8 [[TMP15]] to i64 1150 // CHECK2-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM10]] 1151 // CHECK2-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX11]], align 4 1152 // CHECK2-NEXT: [[MUL12:%.*]] = fmul float [[MUL9]], [[TMP16]] 1153 // CHECK2-NEXT: [[TMP17:%.*]] = load float*, float** [[A_ADDR]], align 8 1154 // CHECK2-NEXT: [[TMP18:%.*]] = load i8, i8* [[I]], align 1 1155 // CHECK2-NEXT: [[IDXPROM13:%.*]] = zext i8 [[TMP18]] to i64 1156 // CHECK2-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM13]] 1157 // CHECK2-NEXT: store float [[MUL12]], float* [[ARRAYIDX14]], align 4 1158 // CHECK2-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 1159 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1160 // CHECK2: omp.body.continue: 1161 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1162 // CHECK2: omp.inner.for.inc: 1163 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1164 // CHECK2-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP19]], 1 1165 // CHECK2-NEXT: store i32 [[ADD15]], i32* [[DOTOMP_IV]], align 4 1166 // CHECK2-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB10]]) 1167 // CHECK2-NEXT: call void @__kmpc_dispatch_fini_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 1168 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 1169 // CHECK2: omp.inner.for.end: 1170 // CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1171 // CHECK2: omp.dispatch.inc: 1172 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND]] 1173 // CHECK2: omp.dispatch.end: 1174 // CHECK2-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1175 // CHECK2-IRBUILDER-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[TMP0]]) 1176 // CHECK2-NORMAL-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 1177 // CHECK2-NEXT: ret void 1178 // 1179 // 1180 // CHECK2-LABEL: define {{[^@]+}}@_Z8foo_simdii 1181 // CHECK2-SAME: (i32 [[LOW:%.*]], i32 [[UP:%.*]]) #[[ATTR0]] { 1182 // CHECK2-NEXT: entry: 1183 // CHECK2-NEXT: [[LOW_ADDR:%.*]] = alloca i32, align 4 1184 // CHECK2-NEXT: [[UP_ADDR:%.*]] = alloca i32, align 4 1185 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 1186 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1187 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 1188 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 1189 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 1190 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1191 // CHECK2-NEXT: [[I5:%.*]] = alloca i32, align 4 1192 // CHECK2-NEXT: [[DOTOMP_IV16:%.*]] = alloca i32, align 4 1193 // CHECK2-NEXT: [[_TMP17:%.*]] = alloca i32, align 4 1194 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_18:%.*]] = alloca i32, align 4 1195 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_19:%.*]] = alloca i32, align 4 1196 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_20:%.*]] = alloca i32, align 4 1197 // CHECK2-NEXT: [[I26:%.*]] = alloca i32, align 4 1198 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1199 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1200 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1201 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1202 // CHECK2-NEXT: [[I28:%.*]] = alloca i32, align 4 1203 // CHECK2-NORMAL-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1204 // CHECK2-NEXT: store i32 [[LOW]], i32* [[LOW_ADDR]], align 4 1205 // CHECK2-NEXT: store i32 [[UP]], i32* [[UP_ADDR]], align 4 1206 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[LOW_ADDR]], align 4 1207 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 1208 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[UP_ADDR]], align 4 1209 // CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 1210 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 1211 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1212 // CHECK2-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] 1213 // CHECK2-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1 1214 // CHECK2-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1 1215 // CHECK2-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 1216 // CHECK2-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1 1217 // CHECK2-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4 1218 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1219 // CHECK2-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 1220 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1221 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 1222 // CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] 1223 // CHECK2-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]] 1224 // CHECK2: simd.if.then: 1225 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IV]], align 4 1226 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1227 // CHECK2: omp.inner.for.cond: 1228 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 1229 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !3 1230 // CHECK2-NEXT: [[ADD6:%.*]] = add i32 [[TMP9]], 1 1231 // CHECK2-NEXT: [[CMP7:%.*]] = icmp ult i32 [[TMP8]], [[ADD6]] 1232 // CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1233 // CHECK2: omp.inner.for.body: 1234 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !3 1235 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 1236 // CHECK2-NEXT: [[MUL:%.*]] = mul i32 [[TMP11]], 1 1237 // CHECK2-NEXT: [[ADD8:%.*]] = add i32 [[TMP10]], [[MUL]] 1238 // CHECK2-NEXT: store i32 [[ADD8]], i32* [[I5]], align 4, !llvm.access.group !3 1239 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[I5]], align 4, !llvm.access.group !3 1240 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64 1241 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM]] 1242 // CHECK2-NEXT: store float 0.000000e+00, float* [[ARRAYIDX]], align 4, !llvm.access.group !3 1243 // CHECK2-NEXT: call void @__captured_stmt(i32* [[I5]]), !llvm.access.group !3 1244 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1245 // CHECK2: omp.body.continue: 1246 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1247 // CHECK2: omp.inner.for.inc: 1248 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 1249 // CHECK2-NEXT: [[ADD9:%.*]] = add i32 [[TMP13]], 1 1250 // CHECK2-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 1251 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 1252 // CHECK2: omp.inner.for.end: 1253 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1254 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 1255 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1256 // CHECK2-NEXT: [[SUB10:%.*]] = sub i32 [[TMP15]], [[TMP16]] 1257 // CHECK2-NEXT: [[SUB11:%.*]] = sub i32 [[SUB10]], 1 1258 // CHECK2-NEXT: [[ADD12:%.*]] = add i32 [[SUB11]], 1 1259 // CHECK2-NEXT: [[DIV13:%.*]] = udiv i32 [[ADD12]], 1 1260 // CHECK2-NEXT: [[MUL14:%.*]] = mul i32 [[DIV13]], 1 1261 // CHECK2-NEXT: [[ADD15:%.*]] = add i32 [[TMP14]], [[MUL14]] 1262 // CHECK2-NEXT: store i32 [[ADD15]], i32* [[I5]], align 4 1263 // CHECK2-NEXT: br label [[SIMD_IF_END]] 1264 // CHECK2: simd.if.end: 1265 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[LOW_ADDR]], align 4 1266 // CHECK2-NEXT: store i32 [[TMP17]], i32* [[DOTCAPTURE_EXPR_18]], align 4 1267 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[UP_ADDR]], align 4 1268 // CHECK2-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_19]], align 4 1269 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 1270 // CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 1271 // CHECK2-NEXT: [[SUB21:%.*]] = sub i32 [[TMP19]], [[TMP20]] 1272 // CHECK2-NEXT: [[SUB22:%.*]] = sub i32 [[SUB21]], 1 1273 // CHECK2-NEXT: [[ADD23:%.*]] = add i32 [[SUB22]], 1 1274 // CHECK2-NEXT: [[DIV24:%.*]] = udiv i32 [[ADD23]], 1 1275 // CHECK2-NEXT: [[SUB25:%.*]] = sub i32 [[DIV24]], 1 1276 // CHECK2-NEXT: store i32 [[SUB25]], i32* [[DOTCAPTURE_EXPR_20]], align 4 1277 // CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 1278 // CHECK2-NEXT: store i32 [[TMP21]], i32* [[I26]], align 4 1279 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 1280 // CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 1281 // CHECK2-NEXT: [[CMP27:%.*]] = icmp slt i32 [[TMP22]], [[TMP23]] 1282 // CHECK2-NEXT: br i1 [[CMP27]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 1283 // CHECK2: omp.precond.then: 1284 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1285 // CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_20]], align 4 1286 // CHECK2-NEXT: store i32 [[TMP24]], i32* [[DOTOMP_UB]], align 4 1287 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1288 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1289 // CHECK2-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_20]], align 4 1290 // CHECK2-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB12:[0-9]+]]) 1291 // CHECK2-NEXT: call void @__kmpc_dispatch_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 66, i32 0, i32 [[TMP25]], i32 1, i32 1) 1292 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 1293 // CHECK2: omp.dispatch.cond: 1294 // CHECK2-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB12]]) 1295 // CHECK2-NEXT: [[TMP26:%.*]] = call i32 @__kmpc_dispatch_next_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 1296 // CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP26]], 0 1297 // CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 1298 // CHECK2: omp.dispatch.body: 1299 // CHECK2-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1300 // CHECK2-NEXT: store i32 [[TMP27]], i32* [[DOTOMP_IV16]], align 4 1301 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND29:%.*]] 1302 // CHECK2-IRBUILDER: omp.inner.for.cond30: 1303 // CHECK2-NORMAL: omp.inner.for.cond29: 1304 // CHECK2-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV16]], align 4, !llvm.access.group !7 1305 // CHECK2-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !7 1306 // CHECK2-NEXT: [[ADD30:%.*]] = add i32 [[TMP29]], 1 1307 // CHECK2-NEXT: [[CMP31:%.*]] = icmp ult i32 [[TMP28]], [[ADD30]] 1308 // CHECK2-NEXT: br i1 [[CMP31]], label [[OMP_INNER_FOR_BODY32:%.*]], label [[OMP_INNER_FOR_END40:%.*]] 1309 // CHECK2-IRBUILDER: omp.inner.for.body33: 1310 // CHECK2-NORMAL: omp.inner.for.body32: 1311 // CHECK2-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4, !llvm.access.group !7 1312 // CHECK2-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV16]], align 4, !llvm.access.group !7 1313 // CHECK2-NEXT: [[MUL33:%.*]] = mul i32 [[TMP31]], 1 1314 // CHECK2-NEXT: [[ADD34:%.*]] = add i32 [[TMP30]], [[MUL33]] 1315 // CHECK2-NEXT: store i32 [[ADD34]], i32* [[I28]], align 4, !llvm.access.group !7 1316 // CHECK2-NEXT: [[TMP32:%.*]] = load i32, i32* [[I28]], align 4, !llvm.access.group !7 1317 // CHECK2-NEXT: [[IDXPROM35:%.*]] = sext i32 [[TMP32]] to i64 1318 // CHECK2-NEXT: [[ARRAYIDX36:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM35]] 1319 // CHECK2-NEXT: store float 0.000000e+00, float* [[ARRAYIDX36]], align 4, !llvm.access.group !7 1320 // CHECK2-NEXT: call void @__captured_stmt.1(i32* [[I28]]), !llvm.access.group !7 1321 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE37:%.*]] 1322 // CHECK2-IRBUILDER: omp.body.continue38: 1323 // CHECK2-NORMAL: omp.body.continue37: 1324 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC38:%.*]] 1325 // CHECK2-IRBUILDER: omp.inner.for.inc39: 1326 // CHECK2-NORMAL: omp.inner.for.inc38: 1327 // CHECK2-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_IV16]], align 4, !llvm.access.group !7 1328 // CHECK2-NEXT: [[ADD39:%.*]] = add i32 [[TMP33]], 1 1329 // CHECK2-NEXT: store i32 [[ADD39]], i32* [[DOTOMP_IV16]], align 4, !llvm.access.group !7 1330 // CHECK2-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB12]]) 1331 // CHECK2-NEXT: call void @__kmpc_dispatch_fini_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]), !llvm.access.group !7 1332 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND29]], !llvm.loop [[LOOP8:![0-9]+]] 1333 // CHECK2-IRBUILDER: omp.inner.for.end42: 1334 // CHECK2-NORMAL: omp.inner.for.end40: 1335 // CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1336 // CHECK2: omp.dispatch.inc: 1337 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND]] 1338 // CHECK2: omp.dispatch.end: 1339 // CHECK2-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 1340 // CHECK2-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 1341 // CHECK2-NEXT: br i1 [[TMP35]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1342 // CHECK2: .omp.final.then: 1343 // CHECK2-NEXT: [[TMP36:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 1344 // CHECK2-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 1345 // CHECK2-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 1346 // CHECK2-NEXT: [[SUB41:%.*]] = sub i32 [[TMP37]], [[TMP38]] 1347 // CHECK2-NEXT: [[SUB42:%.*]] = sub i32 [[SUB41]], 1 1348 // CHECK2-NEXT: [[ADD43:%.*]] = add i32 [[SUB42]], 1 1349 // CHECK2-NEXT: [[DIV44:%.*]] = udiv i32 [[ADD43]], 1 1350 // CHECK2-NEXT: [[MUL45:%.*]] = mul i32 [[DIV44]], 1 1351 // CHECK2-NEXT: [[ADD46:%.*]] = add i32 [[TMP36]], [[MUL45]] 1352 // CHECK2-NEXT: store i32 [[ADD46]], i32* [[I28]], align 4 1353 // CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]] 1354 // CHECK2: .omp.final.done: 1355 // CHECK2-NEXT: br label [[OMP_PRECOND_END]] 1356 // CHECK2: omp.precond.end: 1357 // CHECK2-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1358 // CHECK2-IRBUILDER-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[TMP0]]) 1359 // CHECK2-NORMAL-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 1360 // CHECK2-NEXT: ret void 1361 // 1362 // 1363 // CHECK2-LABEL: define {{[^@]+}}@__captured_stmt 1364 // CHECK2-SAME: (i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR3:[0-9]+]] { 1365 // CHECK2-NEXT: entry: 1366 // CHECK2-NEXT: [[I_ADDR:%.*]] = alloca i32*, align 8 1367 // CHECK2-NEXT: store i32* [[I]], i32** [[I_ADDR]], align 8 1368 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[I_ADDR]], align 8 1369 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 1370 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 1371 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM]] 1372 // CHECK2-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 1373 // CHECK2-NEXT: ret void 1374 // 1375 // 1376 // CHECK2-LABEL: define {{[^@]+}}@__captured_stmt.1 1377 // CHECK2-SAME: (i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR3]] { 1378 // CHECK2-NEXT: entry: 1379 // CHECK2-NEXT: [[I_ADDR:%.*]] = alloca i32*, align 8 1380 // CHECK2-NEXT: store i32* [[I]], i32** [[I_ADDR]], align 8 1381 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[I_ADDR]], align 8 1382 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 1383 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 1384 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM]] 1385 // CHECK2-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 1386 // CHECK2-NEXT: ret void 1387 // 1388 // 1389 // CHECK3-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 1390 // CHECK3-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { 1391 // CHECK3-NEXT: entry: 1392 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 1393 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 1394 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 1395 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 1396 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1397 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1398 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1399 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1400 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1401 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1402 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1403 // CHECK3-NORMAL-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 1404 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 1405 // CHECK3-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 1406 // CHECK3-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 1407 // CHECK3-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 1408 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1409 // CHECK3-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 1410 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1411 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1412 // CHECK3-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3:[0-9]+]]) 1413 // CHECK3-IRBUILDER-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP0]], i32 66, i32 0, i32 4571423, i32 1, i32 1) 1414 // CHECK3-NORMAL-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 66, i32 0, i32 4571423, i32 1, i32 1) 1415 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 1416 // CHECK3: omp.dispatch.cond: 1417 // CHECK3-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3]]) 1418 // CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 1419 // CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 1420 // CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 1421 // CHECK3: omp.dispatch.body: 1422 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1423 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_IV]], align 4 1424 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1425 // CHECK3: omp.inner.for.cond: 1426 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1427 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1428 // CHECK3-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP3]], [[TMP4]] 1429 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1430 // CHECK3: omp.inner.for.body: 1431 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1432 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP5]], 7 1433 // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 1434 // CHECK3-NEXT: store i32 [[SUB]], i32* [[I]], align 4 1435 // CHECK3-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1436 // CHECK3-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 1437 // CHECK3-NEXT: [[TMP6:%.*]] = load float*, float** [[B_ADDR]], align 8 1438 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 1439 // CHECK3-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 1440 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP6]], i64 [[IDXPROM]] 1441 // CHECK3-NEXT: [[TMP8:%.*]] = load float, float* [[ARRAYIDX]], align 4 1442 // CHECK3-NEXT: [[TMP9:%.*]] = load float*, float** [[C_ADDR]], align 8 1443 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 1444 // CHECK3-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP10]] to i64 1445 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP9]], i64 [[IDXPROM1]] 1446 // CHECK3-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX2]], align 4 1447 // CHECK3-NEXT: [[MUL3:%.*]] = fmul float [[TMP8]], [[TMP11]] 1448 // CHECK3-NEXT: [[TMP12:%.*]] = load float*, float** [[D_ADDR]], align 8 1449 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 1450 // CHECK3-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP13]] to i64 1451 // CHECK3-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM4]] 1452 // CHECK3-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX5]], align 4 1453 // CHECK3-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP14]] 1454 // CHECK3-NEXT: [[TMP15:%.*]] = load float*, float** [[A_ADDR]], align 8 1455 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 1456 // CHECK3-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP16]] to i64 1457 // CHECK3-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM7]] 1458 // CHECK3-NEXT: store float [[MUL6]], float* [[ARRAYIDX8]], align 4 1459 // CHECK3-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 1460 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1461 // CHECK3: omp.body.continue: 1462 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1463 // CHECK3: omp.inner.for.inc: 1464 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1465 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP17]], 1 1466 // CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 1467 // CHECK3-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3]]) 1468 // CHECK3-NEXT: call void @__kmpc_dispatch_fini_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 1469 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 1470 // CHECK3: omp.inner.for.end: 1471 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1472 // CHECK3: omp.dispatch.inc: 1473 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]] 1474 // CHECK3: omp.dispatch.end: 1475 // CHECK3-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1476 // CHECK3-IRBUILDER-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4:[0-9]+]], i32 [[TMP0]]) 1477 // CHECK3-NORMAL-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP0]]) 1478 // CHECK3-NEXT: ret void 1479 // 1480 // 1481 // CHECK3-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_ 1482 // CHECK3-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 1483 // CHECK3-NEXT: entry: 1484 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 1485 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 1486 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 1487 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 1488 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 1489 // CHECK3-NEXT: [[TMP:%.*]] = alloca i64, align 8 1490 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 1491 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 1492 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 1493 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1494 // CHECK3-NEXT: [[I:%.*]] = alloca i64, align 8 1495 // CHECK3-NORMAL-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1496 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 1497 // CHECK3-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 1498 // CHECK3-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 1499 // CHECK3-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 1500 // CHECK3-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 1501 // CHECK3-NEXT: store i64 16908287, i64* [[DOTOMP_UB]], align 8 1502 // CHECK3-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 1503 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1504 // CHECK3-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB6:[0-9]+]]) 1505 // CHECK3-NEXT: call void @__kmpc_dispatch_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 67, i64 0, i64 16908287, i64 1, i64 1) 1506 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 1507 // CHECK3: omp.dispatch.cond: 1508 // CHECK3-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB6]]) 1509 // CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 1510 // CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 1511 // CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 1512 // CHECK3: omp.dispatch.body: 1513 // CHECK3-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 1514 // CHECK3-NEXT: store i64 [[TMP2]], i64* [[DOTOMP_IV]], align 8 1515 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1516 // CHECK3: omp.inner.for.cond: 1517 // CHECK3-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1518 // CHECK3-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1519 // CHECK3-NEXT: [[ADD:%.*]] = add i64 [[TMP4]], 1 1520 // CHECK3-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP3]], [[ADD]] 1521 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1522 // CHECK3: omp.inner.for.body: 1523 // CHECK3-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1524 // CHECK3-NEXT: [[MUL:%.*]] = mul i64 [[TMP5]], 127 1525 // CHECK3-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]] 1526 // CHECK3-NEXT: store i64 [[ADD1]], i64* [[I]], align 8 1527 // CHECK3-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1528 // CHECK3-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 1529 // CHECK3-NEXT: [[TMP6:%.*]] = load float*, float** [[B_ADDR]], align 8 1530 // CHECK3-NEXT: [[TMP7:%.*]] = load i64, i64* [[I]], align 8 1531 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP6]], i64 [[TMP7]] 1532 // CHECK3-NEXT: [[TMP8:%.*]] = load float, float* [[ARRAYIDX]], align 4 1533 // CHECK3-NEXT: [[TMP9:%.*]] = load float*, float** [[C_ADDR]], align 8 1534 // CHECK3-NEXT: [[TMP10:%.*]] = load i64, i64* [[I]], align 8 1535 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP9]], i64 [[TMP10]] 1536 // CHECK3-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX2]], align 4 1537 // CHECK3-NEXT: [[MUL3:%.*]] = fmul float [[TMP8]], [[TMP11]] 1538 // CHECK3-NEXT: [[TMP12:%.*]] = load float*, float** [[D_ADDR]], align 8 1539 // CHECK3-NEXT: [[TMP13:%.*]] = load i64, i64* [[I]], align 8 1540 // CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[TMP13]] 1541 // CHECK3-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX4]], align 4 1542 // CHECK3-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP14]] 1543 // CHECK3-NEXT: [[TMP15:%.*]] = load float*, float** [[A_ADDR]], align 8 1544 // CHECK3-NEXT: [[TMP16:%.*]] = load i64, i64* [[I]], align 8 1545 // CHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[TMP16]] 1546 // CHECK3-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4 1547 // CHECK3-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 1548 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1549 // CHECK3: omp.body.continue: 1550 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1551 // CHECK3: omp.inner.for.inc: 1552 // CHECK3-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1553 // CHECK3-NEXT: [[ADD7:%.*]] = add i64 [[TMP17]], 1 1554 // CHECK3-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 1555 // CHECK3-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB6]]) 1556 // CHECK3-NEXT: call void @__kmpc_dispatch_fini_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 1557 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 1558 // CHECK3: omp.inner.for.end: 1559 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1560 // CHECK3: omp.dispatch.inc: 1561 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]] 1562 // CHECK3: omp.dispatch.end: 1563 // CHECK3-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1564 // CHECK3-IRBUILDER-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[TMP0]]) 1565 // CHECK3-NORMAL-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 1566 // CHECK3-NEXT: ret void 1567 // 1568 // 1569 // CHECK3-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_ 1570 // CHECK3-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 1571 // CHECK3-NEXT: entry: 1572 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 1573 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 1574 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 1575 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 1576 // CHECK3-NEXT: [[X:%.*]] = alloca i32, align 4 1577 // CHECK3-NEXT: [[Y:%.*]] = alloca i32, align 4 1578 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 1579 // CHECK3-NEXT: [[TMP:%.*]] = alloca i8, align 1 1580 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1581 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 1582 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8 1583 // CHECK3-NEXT: [[I:%.*]] = alloca i8, align 1 1584 // CHECK3-NEXT: [[X6:%.*]] = alloca i32, align 4 1585 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 1586 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 1587 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 1588 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1589 // CHECK3-NEXT: [[I8:%.*]] = alloca i8, align 1 1590 // CHECK3-NEXT: [[X9:%.*]] = alloca i32, align 4 1591 // CHECK3-NORMAL-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1592 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 1593 // CHECK3-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 1594 // CHECK3-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 1595 // CHECK3-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 1596 // CHECK3-NEXT: store i32 0, i32* [[X]], align 4 1597 // CHECK3-NEXT: store i32 0, i32* [[Y]], align 4 1598 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[Y]], align 4 1599 // CHECK3-NEXT: [[CONV:%.*]] = trunc i32 [[TMP1]] to i8 1600 // CHECK3-NEXT: store i8 [[CONV]], i8* [[DOTCAPTURE_EXPR_]], align 1 1601 // CHECK3-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 1602 // CHECK3-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 1603 // CHECK3-NEXT: [[SUB:%.*]] = sub i32 57, [[CONV3]] 1604 // CHECK3-NEXT: [[ADD:%.*]] = add i32 [[SUB]], 1 1605 // CHECK3-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 1606 // CHECK3-NEXT: [[CONV4:%.*]] = zext i32 [[DIV]] to i64 1607 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV4]], 11 1608 // CHECK3-NEXT: [[SUB5:%.*]] = sub nsw i64 [[MUL]], 1 1609 // CHECK3-NEXT: store i64 [[SUB5]], i64* [[DOTCAPTURE_EXPR_2]], align 8 1610 // CHECK3-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 1611 // CHECK3-NEXT: store i8 [[TMP3]], i8* [[I]], align 1 1612 // CHECK3-NEXT: store i32 11, i32* [[X6]], align 4 1613 // CHECK3-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 1614 // CHECK3-NEXT: [[CONV7:%.*]] = sext i8 [[TMP4]] to i32 1615 // CHECK3-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV7]], 57 1616 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 1617 // CHECK3: omp.precond.then: 1618 // CHECK3-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 1619 // CHECK3-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 1620 // CHECK3-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_UB]], align 8 1621 // CHECK3-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 1622 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1623 // CHECK3-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 1624 // CHECK3-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB8:[0-9]+]]) 1625 // CHECK3-NEXT: call void @__kmpc_dispatch_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 70, i64 0, i64 [[TMP6]], i64 1, i64 1) 1626 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 1627 // CHECK3: omp.dispatch.cond: 1628 // CHECK3-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB8]]) 1629 // CHECK3-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_dispatch_next_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 1630 // CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0 1631 // CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 1632 // CHECK3: omp.dispatch.body: 1633 // CHECK3-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 1634 // CHECK3-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 1635 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1636 // CHECK3: omp.inner.for.cond: 1637 // CHECK3-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1638 // CHECK3-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1639 // CHECK3-NEXT: [[CMP10:%.*]] = icmp sle i64 [[TMP9]], [[TMP10]] 1640 // CHECK3-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1641 // CHECK3: omp.inner.for.body: 1642 // CHECK3-NEXT: [[TMP11:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 1643 // CHECK3-NEXT: [[CONV11:%.*]] = sext i8 [[TMP11]] to i64 1644 // CHECK3-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1645 // CHECK3-NEXT: [[DIV12:%.*]] = sdiv i64 [[TMP12]], 11 1646 // CHECK3-NEXT: [[MUL13:%.*]] = mul nsw i64 [[DIV12]], 1 1647 // CHECK3-NEXT: [[ADD14:%.*]] = add nsw i64 [[CONV11]], [[MUL13]] 1648 // CHECK3-NEXT: [[CONV15:%.*]] = trunc i64 [[ADD14]] to i8 1649 // CHECK3-NEXT: store i8 [[CONV15]], i8* [[I8]], align 1 1650 // CHECK3-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1651 // CHECK3-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1652 // CHECK3-NEXT: [[DIV16:%.*]] = sdiv i64 [[TMP14]], 11 1653 // CHECK3-NEXT: [[MUL17:%.*]] = mul nsw i64 [[DIV16]], 11 1654 // CHECK3-NEXT: [[SUB18:%.*]] = sub nsw i64 [[TMP13]], [[MUL17]] 1655 // CHECK3-NEXT: [[MUL19:%.*]] = mul nsw i64 [[SUB18]], 1 1656 // CHECK3-NEXT: [[SUB20:%.*]] = sub nsw i64 11, [[MUL19]] 1657 // CHECK3-NEXT: [[CONV21:%.*]] = trunc i64 [[SUB20]] to i32 1658 // CHECK3-NEXT: store i32 [[CONV21]], i32* [[X9]], align 4 1659 // CHECK3-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1660 // CHECK3-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 1661 // CHECK3-NEXT: [[TMP15:%.*]] = load float*, float** [[B_ADDR]], align 8 1662 // CHECK3-NEXT: [[TMP16:%.*]] = load i8, i8* [[I8]], align 1 1663 // CHECK3-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP16]] to i64 1664 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM]] 1665 // CHECK3-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4 1666 // CHECK3-NEXT: [[TMP18:%.*]] = load float*, float** [[C_ADDR]], align 8 1667 // CHECK3-NEXT: [[TMP19:%.*]] = load i8, i8* [[I8]], align 1 1668 // CHECK3-NEXT: [[IDXPROM22:%.*]] = sext i8 [[TMP19]] to i64 1669 // CHECK3-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM22]] 1670 // CHECK3-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX23]], align 4 1671 // CHECK3-NEXT: [[MUL24:%.*]] = fmul float [[TMP17]], [[TMP20]] 1672 // CHECK3-NEXT: [[TMP21:%.*]] = load float*, float** [[D_ADDR]], align 8 1673 // CHECK3-NEXT: [[TMP22:%.*]] = load i8, i8* [[I8]], align 1 1674 // CHECK3-NEXT: [[IDXPROM25:%.*]] = sext i8 [[TMP22]] to i64 1675 // CHECK3-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM25]] 1676 // CHECK3-NEXT: [[TMP23:%.*]] = load float, float* [[ARRAYIDX26]], align 4 1677 // CHECK3-NEXT: [[MUL27:%.*]] = fmul float [[MUL24]], [[TMP23]] 1678 // CHECK3-NEXT: [[TMP24:%.*]] = load float*, float** [[A_ADDR]], align 8 1679 // CHECK3-NEXT: [[TMP25:%.*]] = load i8, i8* [[I8]], align 1 1680 // CHECK3-NEXT: [[IDXPROM28:%.*]] = sext i8 [[TMP25]] to i64 1681 // CHECK3-NEXT: [[ARRAYIDX29:%.*]] = getelementptr inbounds float, float* [[TMP24]], i64 [[IDXPROM28]] 1682 // CHECK3-NEXT: store float [[MUL27]], float* [[ARRAYIDX29]], align 4 1683 // CHECK3-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 1684 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1685 // CHECK3: omp.body.continue: 1686 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1687 // CHECK3: omp.inner.for.inc: 1688 // CHECK3-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1689 // CHECK3-NEXT: [[ADD30:%.*]] = add nsw i64 [[TMP26]], 1 1690 // CHECK3-NEXT: store i64 [[ADD30]], i64* [[DOTOMP_IV]], align 8 1691 // CHECK3-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB8]]) 1692 // CHECK3-NEXT: call void @__kmpc_dispatch_fini_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 1693 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 1694 // CHECK3: omp.inner.for.end: 1695 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1696 // CHECK3: omp.dispatch.inc: 1697 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]] 1698 // CHECK3: omp.dispatch.end: 1699 // CHECK3-NEXT: br label [[OMP_PRECOND_END]] 1700 // CHECK3: omp.precond.end: 1701 // CHECK3-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1702 // CHECK3-IRBUILDER-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[TMP0]]) 1703 // CHECK3-NORMAL-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 1704 // CHECK3-NEXT: ret void 1705 // 1706 // 1707 // CHECK3-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_ 1708 // CHECK3-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 1709 // CHECK3-NEXT: entry: 1710 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 1711 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 1712 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 1713 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 1714 // CHECK3-NEXT: [[X:%.*]] = alloca i32, align 4 1715 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1716 // CHECK3-NEXT: [[TMP:%.*]] = alloca i8, align 1 1717 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1718 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1719 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1720 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1721 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1722 // CHECK3-NEXT: [[I:%.*]] = alloca i8, align 1 1723 // CHECK3-NEXT: [[X2:%.*]] = alloca i32, align 4 1724 // CHECK3-NORMAL-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1725 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 1726 // CHECK3-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 1727 // CHECK3-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 1728 // CHECK3-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 1729 // CHECK3-NEXT: store i32 0, i32* [[X]], align 4 1730 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1731 // CHECK3-NEXT: store i32 199, i32* [[DOTOMP_UB]], align 4 1732 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1733 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1734 // CHECK3-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB10:[0-9]+]]) 1735 // CHECK3-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 69, i32 0, i32 199, i32 1, i32 1) 1736 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 1737 // CHECK3: omp.dispatch.cond: 1738 // CHECK3-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB10]]) 1739 // CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 1740 // CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 1741 // CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 1742 // CHECK3: omp.dispatch.body: 1743 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1744 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_IV]], align 4 1745 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1746 // CHECK3: omp.inner.for.cond: 1747 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1748 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1749 // CHECK3-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP3]], [[TMP4]] 1750 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1751 // CHECK3: omp.inner.for.body: 1752 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1753 // CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 20 1754 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 1755 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 48, [[MUL]] 1756 // CHECK3-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i8 1757 // CHECK3-NEXT: store i8 [[CONV]], i8* [[I]], align 1 1758 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1759 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1760 // CHECK3-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP7]], 20 1761 // CHECK3-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 20 1762 // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP6]], [[MUL4]] 1763 // CHECK3-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 1764 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 -10, [[MUL5]] 1765 // CHECK3-NEXT: store i32 [[ADD6]], i32* [[X2]], align 4 1766 // CHECK3-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1767 // CHECK3-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 1768 // CHECK3-NEXT: [[TMP8:%.*]] = load float*, float** [[B_ADDR]], align 8 1769 // CHECK3-NEXT: [[TMP9:%.*]] = load i8, i8* [[I]], align 1 1770 // CHECK3-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP9]] to i64 1771 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[IDXPROM]] 1772 // CHECK3-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX]], align 4 1773 // CHECK3-NEXT: [[TMP11:%.*]] = load float*, float** [[C_ADDR]], align 8 1774 // CHECK3-NEXT: [[TMP12:%.*]] = load i8, i8* [[I]], align 1 1775 // CHECK3-NEXT: [[IDXPROM7:%.*]] = zext i8 [[TMP12]] to i64 1776 // CHECK3-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[IDXPROM7]] 1777 // CHECK3-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX8]], align 4 1778 // CHECK3-NEXT: [[MUL9:%.*]] = fmul float [[TMP10]], [[TMP13]] 1779 // CHECK3-NEXT: [[TMP14:%.*]] = load float*, float** [[D_ADDR]], align 8 1780 // CHECK3-NEXT: [[TMP15:%.*]] = load i8, i8* [[I]], align 1 1781 // CHECK3-NEXT: [[IDXPROM10:%.*]] = zext i8 [[TMP15]] to i64 1782 // CHECK3-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM10]] 1783 // CHECK3-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX11]], align 4 1784 // CHECK3-NEXT: [[MUL12:%.*]] = fmul float [[MUL9]], [[TMP16]] 1785 // CHECK3-NEXT: [[TMP17:%.*]] = load float*, float** [[A_ADDR]], align 8 1786 // CHECK3-NEXT: [[TMP18:%.*]] = load i8, i8* [[I]], align 1 1787 // CHECK3-NEXT: [[IDXPROM13:%.*]] = zext i8 [[TMP18]] to i64 1788 // CHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM13]] 1789 // CHECK3-NEXT: store float [[MUL12]], float* [[ARRAYIDX14]], align 4 1790 // CHECK3-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 1791 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1792 // CHECK3: omp.body.continue: 1793 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1794 // CHECK3: omp.inner.for.inc: 1795 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1796 // CHECK3-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP19]], 1 1797 // CHECK3-NEXT: store i32 [[ADD15]], i32* [[DOTOMP_IV]], align 4 1798 // CHECK3-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB10]]) 1799 // CHECK3-NEXT: call void @__kmpc_dispatch_fini_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 1800 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 1801 // CHECK3: omp.inner.for.end: 1802 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1803 // CHECK3: omp.dispatch.inc: 1804 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]] 1805 // CHECK3: omp.dispatch.end: 1806 // CHECK3-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1807 // CHECK3-IRBUILDER-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[TMP0]]) 1808 // CHECK3-NORMAL-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 1809 // CHECK3-NEXT: ret void 1810 // 1811 // 1812 // CHECK3-LABEL: define {{[^@]+}}@_Z8foo_simdii 1813 // CHECK3-SAME: (i32 [[LOW:%.*]], i32 [[UP:%.*]]) #[[ATTR0]] { 1814 // CHECK3-NEXT: entry: 1815 // CHECK3-NEXT: [[LOW_ADDR:%.*]] = alloca i32, align 4 1816 // CHECK3-NEXT: [[UP_ADDR:%.*]] = alloca i32, align 4 1817 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1818 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1819 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 1820 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 1821 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1822 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1823 // CHECK3-NEXT: [[I5:%.*]] = alloca i32, align 4 1824 // CHECK3-NEXT: [[DOTOMP_IV16:%.*]] = alloca i32, align 4 1825 // CHECK3-NEXT: [[_TMP17:%.*]] = alloca i32, align 4 1826 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_18:%.*]] = alloca i32, align 4 1827 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_19:%.*]] = alloca i32, align 4 1828 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_20:%.*]] = alloca i32, align 4 1829 // CHECK3-NEXT: [[I26:%.*]] = alloca i32, align 4 1830 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1831 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1832 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1833 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1834 // CHECK3-NEXT: [[I28:%.*]] = alloca i32, align 4 1835 // CHECK3-NORMAL-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1836 // CHECK3-NEXT: store i32 [[LOW]], i32* [[LOW_ADDR]], align 4 1837 // CHECK3-NEXT: store i32 [[UP]], i32* [[UP_ADDR]], align 4 1838 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[LOW_ADDR]], align 4 1839 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 1840 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[UP_ADDR]], align 4 1841 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 1842 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 1843 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1844 // CHECK3-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] 1845 // CHECK3-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1 1846 // CHECK3-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1 1847 // CHECK3-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 1848 // CHECK3-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1 1849 // CHECK3-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4 1850 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1851 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 1852 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1853 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 1854 // CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] 1855 // CHECK3-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]] 1856 // CHECK3: simd.if.then: 1857 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IV]], align 4 1858 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1859 // CHECK3: omp.inner.for.cond: 1860 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 1861 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !3 1862 // CHECK3-NEXT: [[ADD6:%.*]] = add i32 [[TMP9]], 1 1863 // CHECK3-NEXT: [[CMP7:%.*]] = icmp ult i32 [[TMP8]], [[ADD6]] 1864 // CHECK3-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1865 // CHECK3: omp.inner.for.body: 1866 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !3 1867 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 1868 // CHECK3-NEXT: [[MUL:%.*]] = mul i32 [[TMP11]], 1 1869 // CHECK3-NEXT: [[ADD8:%.*]] = add i32 [[TMP10]], [[MUL]] 1870 // CHECK3-NEXT: store i32 [[ADD8]], i32* [[I5]], align 4, !llvm.access.group !3 1871 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[I5]], align 4, !llvm.access.group !3 1872 // CHECK3-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64 1873 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM]] 1874 // CHECK3-NEXT: store float 0.000000e+00, float* [[ARRAYIDX]], align 4, !llvm.access.group !3 1875 // CHECK3-NEXT: call void @__captured_stmt(i32* [[I5]]), !llvm.access.group !3 1876 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1877 // CHECK3: omp.body.continue: 1878 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1879 // CHECK3: omp.inner.for.inc: 1880 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 1881 // CHECK3-NEXT: [[ADD9:%.*]] = add i32 [[TMP13]], 1 1882 // CHECK3-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 1883 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 1884 // CHECK3: omp.inner.for.end: 1885 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1886 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 1887 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1888 // CHECK3-NEXT: [[SUB10:%.*]] = sub i32 [[TMP15]], [[TMP16]] 1889 // CHECK3-NEXT: [[SUB11:%.*]] = sub i32 [[SUB10]], 1 1890 // CHECK3-NEXT: [[ADD12:%.*]] = add i32 [[SUB11]], 1 1891 // CHECK3-NEXT: [[DIV13:%.*]] = udiv i32 [[ADD12]], 1 1892 // CHECK3-NEXT: [[MUL14:%.*]] = mul i32 [[DIV13]], 1 1893 // CHECK3-NEXT: [[ADD15:%.*]] = add i32 [[TMP14]], [[MUL14]] 1894 // CHECK3-NEXT: store i32 [[ADD15]], i32* [[I5]], align 4 1895 // CHECK3-NEXT: br label [[SIMD_IF_END]] 1896 // CHECK3: simd.if.end: 1897 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[LOW_ADDR]], align 4 1898 // CHECK3-NEXT: store i32 [[TMP17]], i32* [[DOTCAPTURE_EXPR_18]], align 4 1899 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[UP_ADDR]], align 4 1900 // CHECK3-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_19]], align 4 1901 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 1902 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 1903 // CHECK3-NEXT: [[SUB21:%.*]] = sub i32 [[TMP19]], [[TMP20]] 1904 // CHECK3-NEXT: [[SUB22:%.*]] = sub i32 [[SUB21]], 1 1905 // CHECK3-NEXT: [[ADD23:%.*]] = add i32 [[SUB22]], 1 1906 // CHECK3-NEXT: [[DIV24:%.*]] = udiv i32 [[ADD23]], 1 1907 // CHECK3-NEXT: [[SUB25:%.*]] = sub i32 [[DIV24]], 1 1908 // CHECK3-NEXT: store i32 [[SUB25]], i32* [[DOTCAPTURE_EXPR_20]], align 4 1909 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 1910 // CHECK3-NEXT: store i32 [[TMP21]], i32* [[I26]], align 4 1911 // CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 1912 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 1913 // CHECK3-NEXT: [[CMP27:%.*]] = icmp slt i32 [[TMP22]], [[TMP23]] 1914 // CHECK3-NEXT: br i1 [[CMP27]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 1915 // CHECK3: omp.precond.then: 1916 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1917 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_20]], align 4 1918 // CHECK3-NEXT: store i32 [[TMP24]], i32* [[DOTOMP_UB]], align 4 1919 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1920 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1921 // CHECK3-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_20]], align 4 1922 // CHECK3-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB12:[0-9]+]]) 1923 // CHECK3-NEXT: call void @__kmpc_dispatch_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 66, i32 0, i32 [[TMP25]], i32 1, i32 1) 1924 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 1925 // CHECK3: omp.dispatch.cond: 1926 // CHECK3-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB12]]) 1927 // CHECK3-NEXT: [[TMP26:%.*]] = call i32 @__kmpc_dispatch_next_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 1928 // CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP26]], 0 1929 // CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 1930 // CHECK3: omp.dispatch.body: 1931 // CHECK3-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1932 // CHECK3-NEXT: store i32 [[TMP27]], i32* [[DOTOMP_IV16]], align 4 1933 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND29:%.*]] 1934 // CHECK3-IRBUILDER: omp.inner.for.cond30: 1935 // CHECK3-NORMAL: omp.inner.for.cond29: 1936 // CHECK3-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV16]], align 4, !llvm.access.group !7 1937 // CHECK3-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !7 1938 // CHECK3-NEXT: [[ADD30:%.*]] = add i32 [[TMP29]], 1 1939 // CHECK3-NEXT: [[CMP31:%.*]] = icmp ult i32 [[TMP28]], [[ADD30]] 1940 // CHECK3-NEXT: br i1 [[CMP31]], label [[OMP_INNER_FOR_BODY32:%.*]], label [[OMP_INNER_FOR_END40:%.*]] 1941 // CHECK3-IRBUILDER: omp.inner.for.body33: 1942 // CHECK3-NORMAL: omp.inner.for.body32: 1943 // CHECK3-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4, !llvm.access.group !7 1944 // CHECK3-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV16]], align 4, !llvm.access.group !7 1945 // CHECK3-NEXT: [[MUL33:%.*]] = mul i32 [[TMP31]], 1 1946 // CHECK3-NEXT: [[ADD34:%.*]] = add i32 [[TMP30]], [[MUL33]] 1947 // CHECK3-NEXT: store i32 [[ADD34]], i32* [[I28]], align 4, !llvm.access.group !7 1948 // CHECK3-NEXT: [[TMP32:%.*]] = load i32, i32* [[I28]], align 4, !llvm.access.group !7 1949 // CHECK3-NEXT: [[IDXPROM35:%.*]] = sext i32 [[TMP32]] to i64 1950 // CHECK3-NEXT: [[ARRAYIDX36:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM35]] 1951 // CHECK3-NEXT: store float 0.000000e+00, float* [[ARRAYIDX36]], align 4, !llvm.access.group !7 1952 // CHECK3-NEXT: call void @__captured_stmt.1(i32* [[I28]]), !llvm.access.group !7 1953 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE37:%.*]] 1954 // CHECK3-IRBUILDER: omp.body.continue38: 1955 // CHECK3-NORMAL: omp.body.continue37: 1956 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC38:%.*]] 1957 // CHECK3-IRBUILDER: omp.inner.for.inc39: 1958 // CHECK3-NORMAL: omp.inner.for.inc38: 1959 // CHECK3-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_IV16]], align 4, !llvm.access.group !7 1960 // CHECK3-NEXT: [[ADD39:%.*]] = add i32 [[TMP33]], 1 1961 // CHECK3-NEXT: store i32 [[ADD39]], i32* [[DOTOMP_IV16]], align 4, !llvm.access.group !7 1962 // CHECK3-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB12]]) 1963 // CHECK3-NEXT: call void @__kmpc_dispatch_fini_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]), !llvm.access.group !7 1964 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND29]], !llvm.loop [[LOOP8:![0-9]+]] 1965 // CHECK3-IRBUILDER: omp.inner.for.end42: 1966 // CHECK3-NORMAL: omp.inner.for.end40: 1967 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1968 // CHECK3: omp.dispatch.inc: 1969 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]] 1970 // CHECK3: omp.dispatch.end: 1971 // CHECK3-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 1972 // CHECK3-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 1973 // CHECK3-NEXT: br i1 [[TMP35]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1974 // CHECK3: .omp.final.then: 1975 // CHECK3-NEXT: [[TMP36:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 1976 // CHECK3-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 1977 // CHECK3-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 1978 // CHECK3-NEXT: [[SUB41:%.*]] = sub i32 [[TMP37]], [[TMP38]] 1979 // CHECK3-NEXT: [[SUB42:%.*]] = sub i32 [[SUB41]], 1 1980 // CHECK3-NEXT: [[ADD43:%.*]] = add i32 [[SUB42]], 1 1981 // CHECK3-NEXT: [[DIV44:%.*]] = udiv i32 [[ADD43]], 1 1982 // CHECK3-NEXT: [[MUL45:%.*]] = mul i32 [[DIV44]], 1 1983 // CHECK3-NEXT: [[ADD46:%.*]] = add i32 [[TMP36]], [[MUL45]] 1984 // CHECK3-NEXT: store i32 [[ADD46]], i32* [[I28]], align 4 1985 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 1986 // CHECK3: .omp.final.done: 1987 // CHECK3-NEXT: br label [[OMP_PRECOND_END]] 1988 // CHECK3: omp.precond.end: 1989 // CHECK3-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1990 // CHECK3-IRBUILDER-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[TMP0]]) 1991 // CHECK3-NORMAL-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 1992 // CHECK3-NEXT: ret void 1993 // 1994 // 1995 // CHECK3-LABEL: define {{[^@]+}}@__captured_stmt 1996 // CHECK3-SAME: (i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR3:[0-9]+]] { 1997 // CHECK3-NEXT: entry: 1998 // CHECK3-NEXT: [[I_ADDR:%.*]] = alloca i32*, align 8 1999 // CHECK3-NEXT: store i32* [[I]], i32** [[I_ADDR]], align 8 2000 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[I_ADDR]], align 8 2001 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 2002 // CHECK3-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 2003 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM]] 2004 // CHECK3-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 2005 // CHECK3-NEXT: ret void 2006 // 2007 // 2008 // CHECK3-LABEL: define {{[^@]+}}@__captured_stmt.1 2009 // CHECK3-SAME: (i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR3]] { 2010 // CHECK3-NEXT: entry: 2011 // CHECK3-NEXT: [[I_ADDR:%.*]] = alloca i32*, align 8 2012 // CHECK3-NEXT: store i32* [[I]], i32** [[I_ADDR]], align 8 2013 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[I_ADDR]], align 8 2014 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 2015 // CHECK3-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 2016 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM]] 2017 // CHECK3-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 2018 // CHECK3-NEXT: ret void 2019 // 2020 // 2021 // CHECK4-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 2022 // CHECK4-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { 2023 // CHECK4-NEXT: entry: 2024 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 2025 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 2026 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 2027 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 2028 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2029 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 2030 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2031 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2032 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2033 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2034 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 2035 // CHECK4-NORMAL-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 2036 // CHECK4-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 2037 // CHECK4-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 2038 // CHECK4-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 2039 // CHECK4-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 2040 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2041 // CHECK4-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 2042 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2043 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2044 // CHECK4-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3:[0-9]+]]) 2045 // CHECK4-IRBUILDER-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP0]], i32 66, i32 0, i32 4571423, i32 1, i32 1) 2046 // CHECK4-NORMAL-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 66, i32 0, i32 4571423, i32 1, i32 1) 2047 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 2048 // CHECK4: omp.dispatch.cond: 2049 // CHECK4-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3]]) 2050 // CHECK4-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 2051 // CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 2052 // CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 2053 // CHECK4: omp.dispatch.body: 2054 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2055 // CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_IV]], align 4 2056 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2057 // CHECK4: omp.inner.for.cond: 2058 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2059 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2060 // CHECK4-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP3]], [[TMP4]] 2061 // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2062 // CHECK4: omp.inner.for.body: 2063 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2064 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP5]], 7 2065 // CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 2066 // CHECK4-NEXT: store i32 [[SUB]], i32* [[I]], align 4 2067 // CHECK4-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2068 // CHECK4-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 2069 // CHECK4-NEXT: [[TMP6:%.*]] = load float*, float** [[B_ADDR]], align 8 2070 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 2071 // CHECK4-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 2072 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP6]], i64 [[IDXPROM]] 2073 // CHECK4-NEXT: [[TMP8:%.*]] = load float, float* [[ARRAYIDX]], align 4 2074 // CHECK4-NEXT: [[TMP9:%.*]] = load float*, float** [[C_ADDR]], align 8 2075 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 2076 // CHECK4-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP10]] to i64 2077 // CHECK4-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP9]], i64 [[IDXPROM1]] 2078 // CHECK4-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX2]], align 4 2079 // CHECK4-NEXT: [[MUL3:%.*]] = fmul float [[TMP8]], [[TMP11]] 2080 // CHECK4-NEXT: [[TMP12:%.*]] = load float*, float** [[D_ADDR]], align 8 2081 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 2082 // CHECK4-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP13]] to i64 2083 // CHECK4-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM4]] 2084 // CHECK4-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX5]], align 4 2085 // CHECK4-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP14]] 2086 // CHECK4-NEXT: [[TMP15:%.*]] = load float*, float** [[A_ADDR]], align 8 2087 // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 2088 // CHECK4-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP16]] to i64 2089 // CHECK4-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM7]] 2090 // CHECK4-NEXT: store float [[MUL6]], float* [[ARRAYIDX8]], align 4 2091 // CHECK4-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 2092 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2093 // CHECK4: omp.body.continue: 2094 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2095 // CHECK4: omp.inner.for.inc: 2096 // CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2097 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP17]], 1 2098 // CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 2099 // CHECK4-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3]]) 2100 // CHECK4-NEXT: call void @__kmpc_dispatch_fini_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 2101 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] 2102 // CHECK4: omp.inner.for.end: 2103 // CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2104 // CHECK4: omp.dispatch.inc: 2105 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND]] 2106 // CHECK4: omp.dispatch.end: 2107 // CHECK4-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2108 // CHECK4-IRBUILDER-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4:[0-9]+]], i32 [[TMP0]]) 2109 // CHECK4-NORMAL-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP0]]) 2110 // CHECK4-NEXT: ret void 2111 // 2112 // 2113 // CHECK4-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_ 2114 // CHECK4-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 2115 // CHECK4-NEXT: entry: 2116 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 2117 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 2118 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 2119 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 2120 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 2121 // CHECK4-NEXT: [[TMP:%.*]] = alloca i64, align 8 2122 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 2123 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 2124 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 2125 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2126 // CHECK4-NEXT: [[I:%.*]] = alloca i64, align 8 2127 // CHECK4-NORMAL-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2128 // CHECK4-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 2129 // CHECK4-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 2130 // CHECK4-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 2131 // CHECK4-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 2132 // CHECK4-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 2133 // CHECK4-NEXT: store i64 16908287, i64* [[DOTOMP_UB]], align 8 2134 // CHECK4-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 2135 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2136 // CHECK4-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB6:[0-9]+]]) 2137 // CHECK4-NEXT: call void @__kmpc_dispatch_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 67, i64 0, i64 16908287, i64 1, i64 1) 2138 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 2139 // CHECK4: omp.dispatch.cond: 2140 // CHECK4-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB6]]) 2141 // CHECK4-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 2142 // CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 2143 // CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 2144 // CHECK4: omp.dispatch.body: 2145 // CHECK4-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 2146 // CHECK4-NEXT: store i64 [[TMP2]], i64* [[DOTOMP_IV]], align 8 2147 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2148 // CHECK4: omp.inner.for.cond: 2149 // CHECK4-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2150 // CHECK4-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 2151 // CHECK4-NEXT: [[ADD:%.*]] = add i64 [[TMP4]], 1 2152 // CHECK4-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP3]], [[ADD]] 2153 // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2154 // CHECK4: omp.inner.for.body: 2155 // CHECK4-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2156 // CHECK4-NEXT: [[MUL:%.*]] = mul i64 [[TMP5]], 127 2157 // CHECK4-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]] 2158 // CHECK4-NEXT: store i64 [[ADD1]], i64* [[I]], align 8 2159 // CHECK4-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2160 // CHECK4-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 2161 // CHECK4-NEXT: [[TMP6:%.*]] = load float*, float** [[B_ADDR]], align 8 2162 // CHECK4-NEXT: [[TMP7:%.*]] = load i64, i64* [[I]], align 8 2163 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP6]], i64 [[TMP7]] 2164 // CHECK4-NEXT: [[TMP8:%.*]] = load float, float* [[ARRAYIDX]], align 4 2165 // CHECK4-NEXT: [[TMP9:%.*]] = load float*, float** [[C_ADDR]], align 8 2166 // CHECK4-NEXT: [[TMP10:%.*]] = load i64, i64* [[I]], align 8 2167 // CHECK4-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP9]], i64 [[TMP10]] 2168 // CHECK4-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX2]], align 4 2169 // CHECK4-NEXT: [[MUL3:%.*]] = fmul float [[TMP8]], [[TMP11]] 2170 // CHECK4-NEXT: [[TMP12:%.*]] = load float*, float** [[D_ADDR]], align 8 2171 // CHECK4-NEXT: [[TMP13:%.*]] = load i64, i64* [[I]], align 8 2172 // CHECK4-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[TMP13]] 2173 // CHECK4-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX4]], align 4 2174 // CHECK4-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP14]] 2175 // CHECK4-NEXT: [[TMP15:%.*]] = load float*, float** [[A_ADDR]], align 8 2176 // CHECK4-NEXT: [[TMP16:%.*]] = load i64, i64* [[I]], align 8 2177 // CHECK4-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[TMP16]] 2178 // CHECK4-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4 2179 // CHECK4-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 2180 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2181 // CHECK4: omp.body.continue: 2182 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2183 // CHECK4: omp.inner.for.inc: 2184 // CHECK4-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2185 // CHECK4-NEXT: [[ADD7:%.*]] = add i64 [[TMP17]], 1 2186 // CHECK4-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 2187 // CHECK4-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB6]]) 2188 // CHECK4-NEXT: call void @__kmpc_dispatch_fini_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 2189 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] 2190 // CHECK4: omp.inner.for.end: 2191 // CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2192 // CHECK4: omp.dispatch.inc: 2193 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND]] 2194 // CHECK4: omp.dispatch.end: 2195 // CHECK4-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2196 // CHECK4-IRBUILDER-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[TMP0]]) 2197 // CHECK4-NORMAL-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 2198 // CHECK4-NEXT: ret void 2199 // 2200 // 2201 // CHECK4-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_ 2202 // CHECK4-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 2203 // CHECK4-NEXT: entry: 2204 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 2205 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 2206 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 2207 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 2208 // CHECK4-NEXT: [[X:%.*]] = alloca i32, align 4 2209 // CHECK4-NEXT: [[Y:%.*]] = alloca i32, align 4 2210 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 2211 // CHECK4-NEXT: [[TMP:%.*]] = alloca i8, align 1 2212 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2213 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 2214 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8 2215 // CHECK4-NEXT: [[I:%.*]] = alloca i8, align 1 2216 // CHECK4-NEXT: [[X6:%.*]] = alloca i32, align 4 2217 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 2218 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 2219 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 2220 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2221 // CHECK4-NEXT: [[I8:%.*]] = alloca i8, align 1 2222 // CHECK4-NEXT: [[X9:%.*]] = alloca i32, align 4 2223 // CHECK4-NORMAL-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2224 // CHECK4-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 2225 // CHECK4-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 2226 // CHECK4-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 2227 // CHECK4-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 2228 // CHECK4-NEXT: store i32 0, i32* [[X]], align 4 2229 // CHECK4-NEXT: store i32 0, i32* [[Y]], align 4 2230 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[Y]], align 4 2231 // CHECK4-NEXT: [[CONV:%.*]] = trunc i32 [[TMP1]] to i8 2232 // CHECK4-NEXT: store i8 [[CONV]], i8* [[DOTCAPTURE_EXPR_]], align 1 2233 // CHECK4-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 2234 // CHECK4-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 2235 // CHECK4-NEXT: [[SUB:%.*]] = sub i32 57, [[CONV3]] 2236 // CHECK4-NEXT: [[ADD:%.*]] = add i32 [[SUB]], 1 2237 // CHECK4-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 2238 // CHECK4-NEXT: [[CONV4:%.*]] = zext i32 [[DIV]] to i64 2239 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV4]], 11 2240 // CHECK4-NEXT: [[SUB5:%.*]] = sub nsw i64 [[MUL]], 1 2241 // CHECK4-NEXT: store i64 [[SUB5]], i64* [[DOTCAPTURE_EXPR_2]], align 8 2242 // CHECK4-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 2243 // CHECK4-NEXT: store i8 [[TMP3]], i8* [[I]], align 1 2244 // CHECK4-NEXT: store i32 11, i32* [[X6]], align 4 2245 // CHECK4-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 2246 // CHECK4-NEXT: [[CONV7:%.*]] = sext i8 [[TMP4]] to i32 2247 // CHECK4-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV7]], 57 2248 // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 2249 // CHECK4: omp.precond.then: 2250 // CHECK4-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 2251 // CHECK4-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 2252 // CHECK4-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_UB]], align 8 2253 // CHECK4-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 2254 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2255 // CHECK4-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 2256 // CHECK4-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB8:[0-9]+]]) 2257 // CHECK4-NEXT: call void @__kmpc_dispatch_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 70, i64 0, i64 [[TMP6]], i64 1, i64 1) 2258 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 2259 // CHECK4: omp.dispatch.cond: 2260 // CHECK4-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB8]]) 2261 // CHECK4-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_dispatch_next_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 2262 // CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0 2263 // CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 2264 // CHECK4: omp.dispatch.body: 2265 // CHECK4-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 2266 // CHECK4-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 2267 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2268 // CHECK4: omp.inner.for.cond: 2269 // CHECK4-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2270 // CHECK4-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 2271 // CHECK4-NEXT: [[CMP10:%.*]] = icmp sle i64 [[TMP9]], [[TMP10]] 2272 // CHECK4-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2273 // CHECK4: omp.inner.for.body: 2274 // CHECK4-NEXT: [[TMP11:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 2275 // CHECK4-NEXT: [[CONV11:%.*]] = sext i8 [[TMP11]] to i64 2276 // CHECK4-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2277 // CHECK4-NEXT: [[DIV12:%.*]] = sdiv i64 [[TMP12]], 11 2278 // CHECK4-NEXT: [[MUL13:%.*]] = mul nsw i64 [[DIV12]], 1 2279 // CHECK4-NEXT: [[ADD14:%.*]] = add nsw i64 [[CONV11]], [[MUL13]] 2280 // CHECK4-NEXT: [[CONV15:%.*]] = trunc i64 [[ADD14]] to i8 2281 // CHECK4-NEXT: store i8 [[CONV15]], i8* [[I8]], align 1 2282 // CHECK4-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2283 // CHECK4-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2284 // CHECK4-NEXT: [[DIV16:%.*]] = sdiv i64 [[TMP14]], 11 2285 // CHECK4-NEXT: [[MUL17:%.*]] = mul nsw i64 [[DIV16]], 11 2286 // CHECK4-NEXT: [[SUB18:%.*]] = sub nsw i64 [[TMP13]], [[MUL17]] 2287 // CHECK4-NEXT: [[MUL19:%.*]] = mul nsw i64 [[SUB18]], 1 2288 // CHECK4-NEXT: [[SUB20:%.*]] = sub nsw i64 11, [[MUL19]] 2289 // CHECK4-NEXT: [[CONV21:%.*]] = trunc i64 [[SUB20]] to i32 2290 // CHECK4-NEXT: store i32 [[CONV21]], i32* [[X9]], align 4 2291 // CHECK4-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2292 // CHECK4-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 2293 // CHECK4-NEXT: [[TMP15:%.*]] = load float*, float** [[B_ADDR]], align 8 2294 // CHECK4-NEXT: [[TMP16:%.*]] = load i8, i8* [[I8]], align 1 2295 // CHECK4-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP16]] to i64 2296 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM]] 2297 // CHECK4-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4 2298 // CHECK4-NEXT: [[TMP18:%.*]] = load float*, float** [[C_ADDR]], align 8 2299 // CHECK4-NEXT: [[TMP19:%.*]] = load i8, i8* [[I8]], align 1 2300 // CHECK4-NEXT: [[IDXPROM22:%.*]] = sext i8 [[TMP19]] to i64 2301 // CHECK4-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM22]] 2302 // CHECK4-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX23]], align 4 2303 // CHECK4-NEXT: [[MUL24:%.*]] = fmul float [[TMP17]], [[TMP20]] 2304 // CHECK4-NEXT: [[TMP21:%.*]] = load float*, float** [[D_ADDR]], align 8 2305 // CHECK4-NEXT: [[TMP22:%.*]] = load i8, i8* [[I8]], align 1 2306 // CHECK4-NEXT: [[IDXPROM25:%.*]] = sext i8 [[TMP22]] to i64 2307 // CHECK4-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM25]] 2308 // CHECK4-NEXT: [[TMP23:%.*]] = load float, float* [[ARRAYIDX26]], align 4 2309 // CHECK4-NEXT: [[MUL27:%.*]] = fmul float [[MUL24]], [[TMP23]] 2310 // CHECK4-NEXT: [[TMP24:%.*]] = load float*, float** [[A_ADDR]], align 8 2311 // CHECK4-NEXT: [[TMP25:%.*]] = load i8, i8* [[I8]], align 1 2312 // CHECK4-NEXT: [[IDXPROM28:%.*]] = sext i8 [[TMP25]] to i64 2313 // CHECK4-NEXT: [[ARRAYIDX29:%.*]] = getelementptr inbounds float, float* [[TMP24]], i64 [[IDXPROM28]] 2314 // CHECK4-NEXT: store float [[MUL27]], float* [[ARRAYIDX29]], align 4 2315 // CHECK4-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 2316 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2317 // CHECK4: omp.body.continue: 2318 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2319 // CHECK4: omp.inner.for.inc: 2320 // CHECK4-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2321 // CHECK4-NEXT: [[ADD30:%.*]] = add nsw i64 [[TMP26]], 1 2322 // CHECK4-NEXT: store i64 [[ADD30]], i64* [[DOTOMP_IV]], align 8 2323 // CHECK4-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB8]]) 2324 // CHECK4-NEXT: call void @__kmpc_dispatch_fini_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 2325 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] 2326 // CHECK4: omp.inner.for.end: 2327 // CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2328 // CHECK4: omp.dispatch.inc: 2329 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND]] 2330 // CHECK4: omp.dispatch.end: 2331 // CHECK4-NEXT: br label [[OMP_PRECOND_END]] 2332 // CHECK4: omp.precond.end: 2333 // CHECK4-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2334 // CHECK4-IRBUILDER-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[TMP0]]) 2335 // CHECK4-NORMAL-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 2336 // CHECK4-NEXT: ret void 2337 // 2338 // 2339 // CHECK4-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_ 2340 // CHECK4-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 2341 // CHECK4-NEXT: entry: 2342 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 2343 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 2344 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 2345 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 2346 // CHECK4-NEXT: [[X:%.*]] = alloca i32, align 4 2347 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2348 // CHECK4-NEXT: [[TMP:%.*]] = alloca i8, align 1 2349 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2350 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2351 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2352 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2353 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2354 // CHECK4-NEXT: [[I:%.*]] = alloca i8, align 1 2355 // CHECK4-NEXT: [[X2:%.*]] = alloca i32, align 4 2356 // CHECK4-NORMAL-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2357 // CHECK4-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 2358 // CHECK4-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 2359 // CHECK4-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 2360 // CHECK4-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 2361 // CHECK4-NEXT: store i32 0, i32* [[X]], align 4 2362 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2363 // CHECK4-NEXT: store i32 199, i32* [[DOTOMP_UB]], align 4 2364 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2365 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2366 // CHECK4-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB10:[0-9]+]]) 2367 // CHECK4-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 69, i32 0, i32 199, i32 1, i32 1) 2368 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 2369 // CHECK4: omp.dispatch.cond: 2370 // CHECK4-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB10]]) 2371 // CHECK4-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 2372 // CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 2373 // CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 2374 // CHECK4: omp.dispatch.body: 2375 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2376 // CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_IV]], align 4 2377 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2378 // CHECK4: omp.inner.for.cond: 2379 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2380 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2381 // CHECK4-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP3]], [[TMP4]] 2382 // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2383 // CHECK4: omp.inner.for.body: 2384 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2385 // CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 20 2386 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 2387 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 48, [[MUL]] 2388 // CHECK4-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i8 2389 // CHECK4-NEXT: store i8 [[CONV]], i8* [[I]], align 1 2390 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2391 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2392 // CHECK4-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP7]], 20 2393 // CHECK4-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 20 2394 // CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP6]], [[MUL4]] 2395 // CHECK4-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 2396 // CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 -10, [[MUL5]] 2397 // CHECK4-NEXT: store i32 [[ADD6]], i32* [[X2]], align 4 2398 // CHECK4-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2399 // CHECK4-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 2400 // CHECK4-NEXT: [[TMP8:%.*]] = load float*, float** [[B_ADDR]], align 8 2401 // CHECK4-NEXT: [[TMP9:%.*]] = load i8, i8* [[I]], align 1 2402 // CHECK4-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP9]] to i64 2403 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[IDXPROM]] 2404 // CHECK4-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX]], align 4 2405 // CHECK4-NEXT: [[TMP11:%.*]] = load float*, float** [[C_ADDR]], align 8 2406 // CHECK4-NEXT: [[TMP12:%.*]] = load i8, i8* [[I]], align 1 2407 // CHECK4-NEXT: [[IDXPROM7:%.*]] = zext i8 [[TMP12]] to i64 2408 // CHECK4-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[IDXPROM7]] 2409 // CHECK4-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX8]], align 4 2410 // CHECK4-NEXT: [[MUL9:%.*]] = fmul float [[TMP10]], [[TMP13]] 2411 // CHECK4-NEXT: [[TMP14:%.*]] = load float*, float** [[D_ADDR]], align 8 2412 // CHECK4-NEXT: [[TMP15:%.*]] = load i8, i8* [[I]], align 1 2413 // CHECK4-NEXT: [[IDXPROM10:%.*]] = zext i8 [[TMP15]] to i64 2414 // CHECK4-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM10]] 2415 // CHECK4-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX11]], align 4 2416 // CHECK4-NEXT: [[MUL12:%.*]] = fmul float [[MUL9]], [[TMP16]] 2417 // CHECK4-NEXT: [[TMP17:%.*]] = load float*, float** [[A_ADDR]], align 8 2418 // CHECK4-NEXT: [[TMP18:%.*]] = load i8, i8* [[I]], align 1 2419 // CHECK4-NEXT: [[IDXPROM13:%.*]] = zext i8 [[TMP18]] to i64 2420 // CHECK4-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM13]] 2421 // CHECK4-NEXT: store float [[MUL12]], float* [[ARRAYIDX14]], align 4 2422 // CHECK4-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 2423 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2424 // CHECK4: omp.body.continue: 2425 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2426 // CHECK4: omp.inner.for.inc: 2427 // CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2428 // CHECK4-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP19]], 1 2429 // CHECK4-NEXT: store i32 [[ADD15]], i32* [[DOTOMP_IV]], align 4 2430 // CHECK4-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB10]]) 2431 // CHECK4-NEXT: call void @__kmpc_dispatch_fini_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 2432 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] 2433 // CHECK4: omp.inner.for.end: 2434 // CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2435 // CHECK4: omp.dispatch.inc: 2436 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND]] 2437 // CHECK4: omp.dispatch.end: 2438 // CHECK4-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2439 // CHECK4-IRBUILDER-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[TMP0]]) 2440 // CHECK4-NORMAL-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 2441 // CHECK4-NEXT: ret void 2442 // 2443 // 2444 // CHECK4-LABEL: define {{[^@]+}}@_Z8foo_simdii 2445 // CHECK4-SAME: (i32 [[LOW:%.*]], i32 [[UP:%.*]]) #[[ATTR0]] { 2446 // CHECK4-NEXT: entry: 2447 // CHECK4-NEXT: [[LOW_ADDR:%.*]] = alloca i32, align 4 2448 // CHECK4-NEXT: [[UP_ADDR:%.*]] = alloca i32, align 4 2449 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 2450 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 2451 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 2452 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 2453 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 2454 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2455 // CHECK4-NEXT: [[I5:%.*]] = alloca i32, align 4 2456 // CHECK4-NEXT: [[DOTOMP_IV16:%.*]] = alloca i32, align 4 2457 // CHECK4-NEXT: [[_TMP17:%.*]] = alloca i32, align 4 2458 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_18:%.*]] = alloca i32, align 4 2459 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_19:%.*]] = alloca i32, align 4 2460 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_20:%.*]] = alloca i32, align 4 2461 // CHECK4-NEXT: [[I26:%.*]] = alloca i32, align 4 2462 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2463 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2464 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2465 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2466 // CHECK4-NEXT: [[I28:%.*]] = alloca i32, align 4 2467 // CHECK4-NORMAL-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2468 // CHECK4-NEXT: store i32 [[LOW]], i32* [[LOW_ADDR]], align 4 2469 // CHECK4-NEXT: store i32 [[UP]], i32* [[UP_ADDR]], align 4 2470 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[LOW_ADDR]], align 4 2471 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 2472 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[UP_ADDR]], align 4 2473 // CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 2474 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 2475 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 2476 // CHECK4-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] 2477 // CHECK4-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1 2478 // CHECK4-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1 2479 // CHECK4-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 2480 // CHECK4-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1 2481 // CHECK4-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4 2482 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 2483 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 2484 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 2485 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 2486 // CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] 2487 // CHECK4-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]] 2488 // CHECK4: simd.if.then: 2489 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IV]], align 4 2490 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2491 // CHECK4: omp.inner.for.cond: 2492 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 2493 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !3 2494 // CHECK4-NEXT: [[ADD6:%.*]] = add i32 [[TMP9]], 1 2495 // CHECK4-NEXT: [[CMP7:%.*]] = icmp ult i32 [[TMP8]], [[ADD6]] 2496 // CHECK4-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2497 // CHECK4: omp.inner.for.body: 2498 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !3 2499 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 2500 // CHECK4-NEXT: [[MUL:%.*]] = mul i32 [[TMP11]], 1 2501 // CHECK4-NEXT: [[ADD8:%.*]] = add i32 [[TMP10]], [[MUL]] 2502 // CHECK4-NEXT: store i32 [[ADD8]], i32* [[I5]], align 4, !llvm.access.group !3 2503 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[I5]], align 4, !llvm.access.group !3 2504 // CHECK4-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64 2505 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM]] 2506 // CHECK4-NEXT: store float 0.000000e+00, float* [[ARRAYIDX]], align 4, !llvm.access.group !3 2507 // CHECK4-NEXT: call void @__captured_stmt(i32* [[I5]]), !llvm.access.group !3 2508 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2509 // CHECK4: omp.body.continue: 2510 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2511 // CHECK4: omp.inner.for.inc: 2512 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 2513 // CHECK4-NEXT: [[ADD9:%.*]] = add i32 [[TMP13]], 1 2514 // CHECK4-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 2515 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 2516 // CHECK4: omp.inner.for.end: 2517 // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 2518 // CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 2519 // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 2520 // CHECK4-NEXT: [[SUB10:%.*]] = sub i32 [[TMP15]], [[TMP16]] 2521 // CHECK4-NEXT: [[SUB11:%.*]] = sub i32 [[SUB10]], 1 2522 // CHECK4-NEXT: [[ADD12:%.*]] = add i32 [[SUB11]], 1 2523 // CHECK4-NEXT: [[DIV13:%.*]] = udiv i32 [[ADD12]], 1 2524 // CHECK4-NEXT: [[MUL14:%.*]] = mul i32 [[DIV13]], 1 2525 // CHECK4-NEXT: [[ADD15:%.*]] = add i32 [[TMP14]], [[MUL14]] 2526 // CHECK4-NEXT: store i32 [[ADD15]], i32* [[I5]], align 4 2527 // CHECK4-NEXT: br label [[SIMD_IF_END]] 2528 // CHECK4: simd.if.end: 2529 // CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[LOW_ADDR]], align 4 2530 // CHECK4-NEXT: store i32 [[TMP17]], i32* [[DOTCAPTURE_EXPR_18]], align 4 2531 // CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[UP_ADDR]], align 4 2532 // CHECK4-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_19]], align 4 2533 // CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 2534 // CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 2535 // CHECK4-NEXT: [[SUB21:%.*]] = sub i32 [[TMP19]], [[TMP20]] 2536 // CHECK4-NEXT: [[SUB22:%.*]] = sub i32 [[SUB21]], 1 2537 // CHECK4-NEXT: [[ADD23:%.*]] = add i32 [[SUB22]], 1 2538 // CHECK4-NEXT: [[DIV24:%.*]] = udiv i32 [[ADD23]], 1 2539 // CHECK4-NEXT: [[SUB25:%.*]] = sub i32 [[DIV24]], 1 2540 // CHECK4-NEXT: store i32 [[SUB25]], i32* [[DOTCAPTURE_EXPR_20]], align 4 2541 // CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 2542 // CHECK4-NEXT: store i32 [[TMP21]], i32* [[I26]], align 4 2543 // CHECK4-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 2544 // CHECK4-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 2545 // CHECK4-NEXT: [[CMP27:%.*]] = icmp slt i32 [[TMP22]], [[TMP23]] 2546 // CHECK4-NEXT: br i1 [[CMP27]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 2547 // CHECK4: omp.precond.then: 2548 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2549 // CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_20]], align 4 2550 // CHECK4-NEXT: store i32 [[TMP24]], i32* [[DOTOMP_UB]], align 4 2551 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2552 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2553 // CHECK4-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_20]], align 4 2554 // CHECK4-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB12:[0-9]+]]) 2555 // CHECK4-NEXT: call void @__kmpc_dispatch_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 66, i32 0, i32 [[TMP25]], i32 1, i32 1) 2556 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 2557 // CHECK4: omp.dispatch.cond: 2558 // CHECK4-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB12]]) 2559 // CHECK4-NEXT: [[TMP26:%.*]] = call i32 @__kmpc_dispatch_next_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 2560 // CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP26]], 0 2561 // CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 2562 // CHECK4: omp.dispatch.body: 2563 // CHECK4-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2564 // CHECK4-NEXT: store i32 [[TMP27]], i32* [[DOTOMP_IV16]], align 4 2565 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND29:%.*]] 2566 // CHECK4-IRBUILDER: omp.inner.for.cond30: 2567 // CHECK4-NORMAL: omp.inner.for.cond29: 2568 // CHECK4-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV16]], align 4, !llvm.access.group !7 2569 // CHECK4-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !7 2570 // CHECK4-NEXT: [[ADD30:%.*]] = add i32 [[TMP29]], 1 2571 // CHECK4-NEXT: [[CMP31:%.*]] = icmp ult i32 [[TMP28]], [[ADD30]] 2572 // CHECK4-NEXT: br i1 [[CMP31]], label [[OMP_INNER_FOR_BODY32:%.*]], label [[OMP_INNER_FOR_END40:%.*]] 2573 // CHECK4-IRBUILDER: omp.inner.for.body33: 2574 // CHECK4-NORMAL: omp.inner.for.body32: 2575 // CHECK4-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4, !llvm.access.group !7 2576 // CHECK4-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV16]], align 4, !llvm.access.group !7 2577 // CHECK4-NEXT: [[MUL33:%.*]] = mul i32 [[TMP31]], 1 2578 // CHECK4-NEXT: [[ADD34:%.*]] = add i32 [[TMP30]], [[MUL33]] 2579 // CHECK4-NEXT: store i32 [[ADD34]], i32* [[I28]], align 4, !llvm.access.group !7 2580 // CHECK4-NEXT: [[TMP32:%.*]] = load i32, i32* [[I28]], align 4, !llvm.access.group !7 2581 // CHECK4-NEXT: [[IDXPROM35:%.*]] = sext i32 [[TMP32]] to i64 2582 // CHECK4-NEXT: [[ARRAYIDX36:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM35]] 2583 // CHECK4-NEXT: store float 0.000000e+00, float* [[ARRAYIDX36]], align 4, !llvm.access.group !7 2584 // CHECK4-NEXT: call void @__captured_stmt.1(i32* [[I28]]), !llvm.access.group !7 2585 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE37:%.*]] 2586 // CHECK4-IRBUILDER: omp.body.continue38: 2587 // CHECK4-NORMAL: omp.body.continue37: 2588 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC38:%.*]] 2589 // CHECK4-IRBUILDER: omp.inner.for.inc39: 2590 // CHECK4-NORMAL: omp.inner.for.inc38: 2591 // CHECK4-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_IV16]], align 4, !llvm.access.group !7 2592 // CHECK4-NEXT: [[ADD39:%.*]] = add i32 [[TMP33]], 1 2593 // CHECK4-NEXT: store i32 [[ADD39]], i32* [[DOTOMP_IV16]], align 4, !llvm.access.group !7 2594 // CHECK4-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB12]]) 2595 // CHECK4-NEXT: call void @__kmpc_dispatch_fini_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]), !llvm.access.group !7 2596 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND29]], !llvm.loop [[LOOP8:![0-9]+]] 2597 // CHECK4-IRBUILDER: omp.inner.for.end42: 2598 // CHECK4-NORMAL: omp.inner.for.end40: 2599 // CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2600 // CHECK4: omp.dispatch.inc: 2601 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND]] 2602 // CHECK4: omp.dispatch.end: 2603 // CHECK4-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 2604 // CHECK4-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 2605 // CHECK4-NEXT: br i1 [[TMP35]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2606 // CHECK4: .omp.final.then: 2607 // CHECK4-NEXT: [[TMP36:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 2608 // CHECK4-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 2609 // CHECK4-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 2610 // CHECK4-NEXT: [[SUB41:%.*]] = sub i32 [[TMP37]], [[TMP38]] 2611 // CHECK4-NEXT: [[SUB42:%.*]] = sub i32 [[SUB41]], 1 2612 // CHECK4-NEXT: [[ADD43:%.*]] = add i32 [[SUB42]], 1 2613 // CHECK4-NEXT: [[DIV44:%.*]] = udiv i32 [[ADD43]], 1 2614 // CHECK4-NEXT: [[MUL45:%.*]] = mul i32 [[DIV44]], 1 2615 // CHECK4-NEXT: [[ADD46:%.*]] = add i32 [[TMP36]], [[MUL45]] 2616 // CHECK4-NEXT: store i32 [[ADD46]], i32* [[I28]], align 4 2617 // CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]] 2618 // CHECK4: .omp.final.done: 2619 // CHECK4-NEXT: br label [[OMP_PRECOND_END]] 2620 // CHECK4: omp.precond.end: 2621 // CHECK4-IRBUILDER-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2622 // CHECK4-IRBUILDER-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[TMP0]]) 2623 // CHECK4-NORMAL-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 2624 // CHECK4-NEXT: ret void 2625 // 2626 // 2627 // CHECK4-LABEL: define {{[^@]+}}@__captured_stmt 2628 // CHECK4-SAME: (i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR3:[0-9]+]] { 2629 // CHECK4-NEXT: entry: 2630 // CHECK4-NEXT: [[I_ADDR:%.*]] = alloca i32*, align 8 2631 // CHECK4-NEXT: store i32* [[I]], i32** [[I_ADDR]], align 8 2632 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[I_ADDR]], align 8 2633 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 2634 // CHECK4-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 2635 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM]] 2636 // CHECK4-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 2637 // CHECK4-NEXT: ret void 2638 // 2639 // 2640 // CHECK4-LABEL: define {{[^@]+}}@__captured_stmt.1 2641 // CHECK4-SAME: (i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR3]] { 2642 // CHECK4-NEXT: entry: 2643 // CHECK4-NEXT: [[I_ADDR:%.*]] = alloca i32*, align 8 2644 // CHECK4-NEXT: store i32* [[I]], i32** [[I_ADDR]], align 8 2645 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[I_ADDR]], align 8 2646 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 2647 // CHECK4-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 2648 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM]] 2649 // CHECK4-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 2650 // CHECK4-NEXT: ret void 2651 // 2652 // 2653 // CHECK5-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 2654 // CHECK5-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { 2655 // CHECK5-NEXT: entry: 2656 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 2657 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 2658 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 2659 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 2660 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 2661 // CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 2662 // CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 2663 // CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 2664 // CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 2665 // CHECK5-NEXT: store i32 32000000, i32* [[I]], align 4 2666 // CHECK5-NEXT: br label [[FOR_COND:%.*]] 2667 // CHECK5: for.cond: 2668 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 2669 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 33 2670 // CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 2671 // CHECK5: for.body: 2672 // CHECK5-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 2673 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 2674 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 2675 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] 2676 // CHECK5-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 2677 // CHECK5-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 2678 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 2679 // CHECK5-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64 2680 // CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] 2681 // CHECK5-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 2682 // CHECK5-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] 2683 // CHECK5-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 2684 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 2685 // CHECK5-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64 2686 // CHECK5-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] 2687 // CHECK5-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 2688 // CHECK5-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] 2689 // CHECK5-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 2690 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 2691 // CHECK5-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64 2692 // CHECK5-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] 2693 // CHECK5-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 2694 // CHECK5-NEXT: br label [[FOR_INC:%.*]] 2695 // CHECK5: for.inc: 2696 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 2697 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], -7 2698 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 2699 // CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] 2700 // CHECK5: for.end: 2701 // CHECK5-NEXT: ret void 2702 // 2703 // 2704 // CHECK5-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_ 2705 // CHECK5-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 2706 // CHECK5-NEXT: entry: 2707 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 2708 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 2709 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 2710 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 2711 // CHECK5-NEXT: [[I:%.*]] = alloca i64, align 8 2712 // CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 2713 // CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 2714 // CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 2715 // CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 2716 // CHECK5-NEXT: store i64 131071, i64* [[I]], align 8 2717 // CHECK5-NEXT: br label [[FOR_COND:%.*]] 2718 // CHECK5: for.cond: 2719 // CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 2720 // CHECK5-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP0]], 2147483647 2721 // CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 2722 // CHECK5: for.body: 2723 // CHECK5-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 2724 // CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[I]], align 8 2725 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[TMP2]] 2726 // CHECK5-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 2727 // CHECK5-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 2728 // CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[I]], align 8 2729 // CHECK5-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[TMP5]] 2730 // CHECK5-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 2731 // CHECK5-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] 2732 // CHECK5-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 2733 // CHECK5-NEXT: [[TMP8:%.*]] = load i64, i64* [[I]], align 8 2734 // CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[TMP8]] 2735 // CHECK5-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 2736 // CHECK5-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] 2737 // CHECK5-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 2738 // CHECK5-NEXT: [[TMP11:%.*]] = load i64, i64* [[I]], align 8 2739 // CHECK5-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[TMP11]] 2740 // CHECK5-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 2741 // CHECK5-NEXT: br label [[FOR_INC:%.*]] 2742 // CHECK5: for.inc: 2743 // CHECK5-NEXT: [[TMP12:%.*]] = load i64, i64* [[I]], align 8 2744 // CHECK5-NEXT: [[ADD:%.*]] = add i64 [[TMP12]], 127 2745 // CHECK5-NEXT: store i64 [[ADD]], i64* [[I]], align 8 2746 // CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 2747 // CHECK5: for.end: 2748 // CHECK5-NEXT: ret void 2749 // 2750 // 2751 // CHECK5-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_ 2752 // CHECK5-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 2753 // CHECK5-NEXT: entry: 2754 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 2755 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 2756 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 2757 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 2758 // CHECK5-NEXT: [[X:%.*]] = alloca i32, align 4 2759 // CHECK5-NEXT: [[Y:%.*]] = alloca i32, align 4 2760 // CHECK5-NEXT: [[I:%.*]] = alloca i8, align 1 2761 // CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 2762 // CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 2763 // CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 2764 // CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 2765 // CHECK5-NEXT: store i32 0, i32* [[X]], align 4 2766 // CHECK5-NEXT: store i32 0, i32* [[Y]], align 4 2767 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[Y]], align 4 2768 // CHECK5-NEXT: [[CONV:%.*]] = trunc i32 [[TMP0]] to i8 2769 // CHECK5-NEXT: store i8 [[CONV]], i8* [[I]], align 1 2770 // CHECK5-NEXT: br label [[FOR_COND:%.*]] 2771 // CHECK5: for.cond: 2772 // CHECK5-NEXT: [[TMP1:%.*]] = load i8, i8* [[I]], align 1 2773 // CHECK5-NEXT: [[CONV1:%.*]] = sext i8 [[TMP1]] to i32 2774 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV1]], 57 2775 // CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END13:%.*]] 2776 // CHECK5: for.body: 2777 // CHECK5-NEXT: store i32 11, i32* [[X]], align 4 2778 // CHECK5-NEXT: br label [[FOR_COND2:%.*]] 2779 // CHECK5: for.cond2: 2780 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[X]], align 4 2781 // CHECK5-NEXT: [[CMP3:%.*]] = icmp ugt i32 [[TMP2]], 0 2782 // CHECK5-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END:%.*]] 2783 // CHECK5: for.body4: 2784 // CHECK5-NEXT: [[TMP3:%.*]] = load float*, float** [[B_ADDR]], align 8 2785 // CHECK5-NEXT: [[TMP4:%.*]] = load i8, i8* [[I]], align 1 2786 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP4]] to i64 2787 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP3]], i64 [[IDXPROM]] 2788 // CHECK5-NEXT: [[TMP5:%.*]] = load float, float* [[ARRAYIDX]], align 4 2789 // CHECK5-NEXT: [[TMP6:%.*]] = load float*, float** [[C_ADDR]], align 8 2790 // CHECK5-NEXT: [[TMP7:%.*]] = load i8, i8* [[I]], align 1 2791 // CHECK5-NEXT: [[IDXPROM5:%.*]] = sext i8 [[TMP7]] to i64 2792 // CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP6]], i64 [[IDXPROM5]] 2793 // CHECK5-NEXT: [[TMP8:%.*]] = load float, float* [[ARRAYIDX6]], align 4 2794 // CHECK5-NEXT: [[MUL:%.*]] = fmul float [[TMP5]], [[TMP8]] 2795 // CHECK5-NEXT: [[TMP9:%.*]] = load float*, float** [[D_ADDR]], align 8 2796 // CHECK5-NEXT: [[TMP10:%.*]] = load i8, i8* [[I]], align 1 2797 // CHECK5-NEXT: [[IDXPROM7:%.*]] = sext i8 [[TMP10]] to i64 2798 // CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP9]], i64 [[IDXPROM7]] 2799 // CHECK5-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX8]], align 4 2800 // CHECK5-NEXT: [[MUL9:%.*]] = fmul float [[MUL]], [[TMP11]] 2801 // CHECK5-NEXT: [[TMP12:%.*]] = load float*, float** [[A_ADDR]], align 8 2802 // CHECK5-NEXT: [[TMP13:%.*]] = load i8, i8* [[I]], align 1 2803 // CHECK5-NEXT: [[IDXPROM10:%.*]] = sext i8 [[TMP13]] to i64 2804 // CHECK5-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM10]] 2805 // CHECK5-NEXT: store float [[MUL9]], float* [[ARRAYIDX11]], align 4 2806 // CHECK5-NEXT: br label [[FOR_INC:%.*]] 2807 // CHECK5: for.inc: 2808 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[X]], align 4 2809 // CHECK5-NEXT: [[DEC:%.*]] = add i32 [[TMP14]], -1 2810 // CHECK5-NEXT: store i32 [[DEC]], i32* [[X]], align 4 2811 // CHECK5-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP5:![0-9]+]] 2812 // CHECK5: for.end: 2813 // CHECK5-NEXT: br label [[FOR_INC12:%.*]] 2814 // CHECK5: for.inc12: 2815 // CHECK5-NEXT: [[TMP15:%.*]] = load i8, i8* [[I]], align 1 2816 // CHECK5-NEXT: [[INC:%.*]] = add i8 [[TMP15]], 1 2817 // CHECK5-NEXT: store i8 [[INC]], i8* [[I]], align 1 2818 // CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 2819 // CHECK5: for.end13: 2820 // CHECK5-NEXT: ret void 2821 // 2822 // 2823 // CHECK5-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_ 2824 // CHECK5-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 2825 // CHECK5-NEXT: entry: 2826 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 2827 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 2828 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 2829 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 2830 // CHECK5-NEXT: [[X:%.*]] = alloca i32, align 4 2831 // CHECK5-NEXT: [[I:%.*]] = alloca i8, align 1 2832 // CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 2833 // CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 2834 // CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 2835 // CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 2836 // CHECK5-NEXT: store i32 0, i32* [[X]], align 4 2837 // CHECK5-NEXT: store i8 48, i8* [[I]], align 1 2838 // CHECK5-NEXT: br label [[FOR_COND:%.*]] 2839 // CHECK5: for.cond: 2840 // CHECK5-NEXT: [[TMP0:%.*]] = load i8, i8* [[I]], align 1 2841 // CHECK5-NEXT: [[CONV:%.*]] = zext i8 [[TMP0]] to i32 2842 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV]], 57 2843 // CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END13:%.*]] 2844 // CHECK5: for.body: 2845 // CHECK5-NEXT: store i32 -10, i32* [[X]], align 4 2846 // CHECK5-NEXT: br label [[FOR_COND1:%.*]] 2847 // CHECK5: for.cond1: 2848 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[X]], align 4 2849 // CHECK5-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP1]], 10 2850 // CHECK5-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] 2851 // CHECK5: for.body3: 2852 // CHECK5-NEXT: [[TMP2:%.*]] = load float*, float** [[B_ADDR]], align 8 2853 // CHECK5-NEXT: [[TMP3:%.*]] = load i8, i8* [[I]], align 1 2854 // CHECK5-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP3]] to i64 2855 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 [[IDXPROM]] 2856 // CHECK5-NEXT: [[TMP4:%.*]] = load float, float* [[ARRAYIDX]], align 4 2857 // CHECK5-NEXT: [[TMP5:%.*]] = load float*, float** [[C_ADDR]], align 8 2858 // CHECK5-NEXT: [[TMP6:%.*]] = load i8, i8* [[I]], align 1 2859 // CHECK5-NEXT: [[IDXPROM4:%.*]] = zext i8 [[TMP6]] to i64 2860 // CHECK5-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP5]], i64 [[IDXPROM4]] 2861 // CHECK5-NEXT: [[TMP7:%.*]] = load float, float* [[ARRAYIDX5]], align 4 2862 // CHECK5-NEXT: [[MUL:%.*]] = fmul float [[TMP4]], [[TMP7]] 2863 // CHECK5-NEXT: [[TMP8:%.*]] = load float*, float** [[D_ADDR]], align 8 2864 // CHECK5-NEXT: [[TMP9:%.*]] = load i8, i8* [[I]], align 1 2865 // CHECK5-NEXT: [[IDXPROM6:%.*]] = zext i8 [[TMP9]] to i64 2866 // CHECK5-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[IDXPROM6]] 2867 // CHECK5-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 2868 // CHECK5-NEXT: [[MUL8:%.*]] = fmul float [[MUL]], [[TMP10]] 2869 // CHECK5-NEXT: [[TMP11:%.*]] = load float*, float** [[A_ADDR]], align 8 2870 // CHECK5-NEXT: [[TMP12:%.*]] = load i8, i8* [[I]], align 1 2871 // CHECK5-NEXT: [[IDXPROM9:%.*]] = zext i8 [[TMP12]] to i64 2872 // CHECK5-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[IDXPROM9]] 2873 // CHECK5-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4 2874 // CHECK5-NEXT: br label [[FOR_INC:%.*]] 2875 // CHECK5: for.inc: 2876 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[X]], align 4 2877 // CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP13]], 1 2878 // CHECK5-NEXT: store i32 [[INC]], i32* [[X]], align 4 2879 // CHECK5-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP7:![0-9]+]] 2880 // CHECK5: for.end: 2881 // CHECK5-NEXT: br label [[FOR_INC11:%.*]] 2882 // CHECK5: for.inc11: 2883 // CHECK5-NEXT: [[TMP14:%.*]] = load i8, i8* [[I]], align 1 2884 // CHECK5-NEXT: [[INC12:%.*]] = add i8 [[TMP14]], 1 2885 // CHECK5-NEXT: store i8 [[INC12]], i8* [[I]], align 1 2886 // CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] 2887 // CHECK5: for.end13: 2888 // CHECK5-NEXT: ret void 2889 // 2890 // 2891 // CHECK5-LABEL: define {{[^@]+}}@_Z8foo_simdii 2892 // CHECK5-SAME: (i32 [[LOW:%.*]], i32 [[UP:%.*]]) #[[ATTR0]] { 2893 // CHECK5-NEXT: entry: 2894 // CHECK5-NEXT: [[LOW_ADDR:%.*]] = alloca i32, align 4 2895 // CHECK5-NEXT: [[UP_ADDR:%.*]] = alloca i32, align 4 2896 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 2897 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 2898 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 2899 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 2900 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 2901 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2902 // CHECK5-NEXT: [[I5:%.*]] = alloca i32, align 4 2903 // CHECK5-NEXT: [[_TMP18:%.*]] = alloca i32, align 4 2904 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_19:%.*]] = alloca i32, align 4 2905 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_20:%.*]] = alloca i32, align 4 2906 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_21:%.*]] = alloca i32, align 4 2907 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2908 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2909 // CHECK5-NEXT: [[I27:%.*]] = alloca i32, align 4 2910 // CHECK5-NEXT: [[DOTOMP_IV30:%.*]] = alloca i32, align 4 2911 // CHECK5-NEXT: [[I31:%.*]] = alloca i32, align 4 2912 // CHECK5-NEXT: store i32 [[LOW]], i32* [[LOW_ADDR]], align 4 2913 // CHECK5-NEXT: store i32 [[UP]], i32* [[UP_ADDR]], align 4 2914 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[LOW_ADDR]], align 4 2915 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 2916 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[UP_ADDR]], align 4 2917 // CHECK5-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_1]], align 4 2918 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 2919 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 2920 // CHECK5-NEXT: [[SUB:%.*]] = sub i32 [[TMP2]], [[TMP3]] 2921 // CHECK5-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1 2922 // CHECK5-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1 2923 // CHECK5-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 2924 // CHECK5-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1 2925 // CHECK5-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4 2926 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 2927 // CHECK5-NEXT: store i32 [[TMP4]], i32* [[I]], align 4 2928 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 2929 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 2930 // CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], [[TMP6]] 2931 // CHECK5-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]] 2932 // CHECK5: simd.if.then: 2933 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IV]], align 4 2934 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2935 // CHECK5: omp.inner.for.cond: 2936 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 2937 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !9 2938 // CHECK5-NEXT: [[ADD6:%.*]] = add i32 [[TMP8]], 1 2939 // CHECK5-NEXT: [[CMP7:%.*]] = icmp ult i32 [[TMP7]], [[ADD6]] 2940 // CHECK5-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2941 // CHECK5: omp.inner.for.body: 2942 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !9 2943 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 2944 // CHECK5-NEXT: [[MUL:%.*]] = mul i32 [[TMP10]], 1 2945 // CHECK5-NEXT: [[ADD8:%.*]] = add i32 [[TMP9]], [[MUL]] 2946 // CHECK5-NEXT: store i32 [[ADD8]], i32* [[I5]], align 4, !llvm.access.group !9 2947 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[I5]], align 4, !llvm.access.group !9 2948 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 2949 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM]] 2950 // CHECK5-NEXT: store float 0.000000e+00, float* [[ARRAYIDX]], align 4, !llvm.access.group !9 2951 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[I5]], align 4, !llvm.access.group !9 2952 // CHECK5-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP12]] to i64 2953 // CHECK5-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM9]] 2954 // CHECK5-NEXT: store float 1.000000e+00, float* [[ARRAYIDX10]], align 4, !llvm.access.group !9 2955 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2956 // CHECK5: omp.body.continue: 2957 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2958 // CHECK5: omp.inner.for.inc: 2959 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 2960 // CHECK5-NEXT: [[ADD11:%.*]] = add i32 [[TMP13]], 1 2961 // CHECK5-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 2962 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] 2963 // CHECK5: omp.inner.for.end: 2964 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 2965 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 2966 // CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 2967 // CHECK5-NEXT: [[SUB12:%.*]] = sub i32 [[TMP15]], [[TMP16]] 2968 // CHECK5-NEXT: [[SUB13:%.*]] = sub i32 [[SUB12]], 1 2969 // CHECK5-NEXT: [[ADD14:%.*]] = add i32 [[SUB13]], 1 2970 // CHECK5-NEXT: [[DIV15:%.*]] = udiv i32 [[ADD14]], 1 2971 // CHECK5-NEXT: [[MUL16:%.*]] = mul i32 [[DIV15]], 1 2972 // CHECK5-NEXT: [[ADD17:%.*]] = add i32 [[TMP14]], [[MUL16]] 2973 // CHECK5-NEXT: store i32 [[ADD17]], i32* [[I5]], align 4 2974 // CHECK5-NEXT: br label [[SIMD_IF_END]] 2975 // CHECK5: simd.if.end: 2976 // CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[LOW_ADDR]], align 4 2977 // CHECK5-NEXT: store i32 [[TMP17]], i32* [[DOTCAPTURE_EXPR_19]], align 4 2978 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[UP_ADDR]], align 4 2979 // CHECK5-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_20]], align 4 2980 // CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_20]], align 4 2981 // CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 2982 // CHECK5-NEXT: [[SUB22:%.*]] = sub i32 [[TMP19]], [[TMP20]] 2983 // CHECK5-NEXT: [[SUB23:%.*]] = sub i32 [[SUB22]], 1 2984 // CHECK5-NEXT: [[ADD24:%.*]] = add i32 [[SUB23]], 1 2985 // CHECK5-NEXT: [[DIV25:%.*]] = udiv i32 [[ADD24]], 1 2986 // CHECK5-NEXT: [[SUB26:%.*]] = sub i32 [[DIV25]], 1 2987 // CHECK5-NEXT: store i32 [[SUB26]], i32* [[DOTCAPTURE_EXPR_21]], align 4 2988 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2989 // CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_21]], align 4 2990 // CHECK5-NEXT: store i32 [[TMP21]], i32* [[DOTOMP_UB]], align 4 2991 // CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 2992 // CHECK5-NEXT: store i32 [[TMP22]], i32* [[I27]], align 4 2993 // CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 2994 // CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_20]], align 4 2995 // CHECK5-NEXT: [[CMP28:%.*]] = icmp slt i32 [[TMP23]], [[TMP24]] 2996 // CHECK5-NEXT: br i1 [[CMP28]], label [[SIMD_IF_THEN29:%.*]], label [[SIMD_IF_END52:%.*]] 2997 // CHECK5: simd.if.then29: 2998 // CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2999 // CHECK5-NEXT: store i32 [[TMP25]], i32* [[DOTOMP_IV30]], align 4 3000 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND32:%.*]] 3001 // CHECK5: omp.inner.for.cond32: 3002 // CHECK5-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_IV30]], align 4, !llvm.access.group !13 3003 // CHECK5-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 3004 // CHECK5-NEXT: [[ADD33:%.*]] = add i32 [[TMP27]], 1 3005 // CHECK5-NEXT: [[CMP34:%.*]] = icmp ult i32 [[TMP26]], [[ADD33]] 3006 // CHECK5-NEXT: br i1 [[CMP34]], label [[OMP_INNER_FOR_BODY35:%.*]], label [[OMP_INNER_FOR_END45:%.*]] 3007 // CHECK5: omp.inner.for.body35: 3008 // CHECK5-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4, !llvm.access.group !13 3009 // CHECK5-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV30]], align 4, !llvm.access.group !13 3010 // CHECK5-NEXT: [[MUL36:%.*]] = mul i32 [[TMP29]], 1 3011 // CHECK5-NEXT: [[ADD37:%.*]] = add i32 [[TMP28]], [[MUL36]] 3012 // CHECK5-NEXT: store i32 [[ADD37]], i32* [[I31]], align 4, !llvm.access.group !13 3013 // CHECK5-NEXT: [[TMP30:%.*]] = load i32, i32* [[I31]], align 4, !llvm.access.group !13 3014 // CHECK5-NEXT: [[IDXPROM38:%.*]] = sext i32 [[TMP30]] to i64 3015 // CHECK5-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM38]] 3016 // CHECK5-NEXT: store float 0.000000e+00, float* [[ARRAYIDX39]], align 4, !llvm.access.group !13 3017 // CHECK5-NEXT: [[TMP31:%.*]] = load i32, i32* [[I31]], align 4, !llvm.access.group !13 3018 // CHECK5-NEXT: [[IDXPROM40:%.*]] = sext i32 [[TMP31]] to i64 3019 // CHECK5-NEXT: [[ARRAYIDX41:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM40]] 3020 // CHECK5-NEXT: store float 1.000000e+00, float* [[ARRAYIDX41]], align 4, !llvm.access.group !13 3021 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE42:%.*]] 3022 // CHECK5: omp.body.continue42: 3023 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC43:%.*]] 3024 // CHECK5: omp.inner.for.inc43: 3025 // CHECK5-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IV30]], align 4, !llvm.access.group !13 3026 // CHECK5-NEXT: [[ADD44:%.*]] = add i32 [[TMP32]], 1 3027 // CHECK5-NEXT: store i32 [[ADD44]], i32* [[DOTOMP_IV30]], align 4, !llvm.access.group !13 3028 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND32]], !llvm.loop [[LOOP14:![0-9]+]] 3029 // CHECK5: omp.inner.for.end45: 3030 // CHECK5-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 3031 // CHECK5-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_20]], align 4 3032 // CHECK5-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 3033 // CHECK5-NEXT: [[SUB46:%.*]] = sub i32 [[TMP34]], [[TMP35]] 3034 // CHECK5-NEXT: [[SUB47:%.*]] = sub i32 [[SUB46]], 1 3035 // CHECK5-NEXT: [[ADD48:%.*]] = add i32 [[SUB47]], 1 3036 // CHECK5-NEXT: [[DIV49:%.*]] = udiv i32 [[ADD48]], 1 3037 // CHECK5-NEXT: [[MUL50:%.*]] = mul i32 [[DIV49]], 1 3038 // CHECK5-NEXT: [[ADD51:%.*]] = add i32 [[TMP33]], [[MUL50]] 3039 // CHECK5-NEXT: store i32 [[ADD51]], i32* [[I31]], align 4 3040 // CHECK5-NEXT: br label [[SIMD_IF_END52]] 3041 // CHECK5: simd.if.end52: 3042 // CHECK5-NEXT: ret void 3043 // 3044 // 3045 // CHECK6-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 3046 // CHECK6-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { 3047 // CHECK6-NEXT: entry: 3048 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 3049 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 3050 // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 3051 // CHECK6-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 3052 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 3053 // CHECK6-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 3054 // CHECK6-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 3055 // CHECK6-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 3056 // CHECK6-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 3057 // CHECK6-NEXT: store i32 32000000, i32* [[I]], align 4 3058 // CHECK6-NEXT: br label [[FOR_COND:%.*]] 3059 // CHECK6: for.cond: 3060 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 3061 // CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 33 3062 // CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 3063 // CHECK6: for.body: 3064 // CHECK6-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 3065 // CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 3066 // CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 3067 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] 3068 // CHECK6-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 3069 // CHECK6-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 3070 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 3071 // CHECK6-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64 3072 // CHECK6-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] 3073 // CHECK6-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 3074 // CHECK6-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] 3075 // CHECK6-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 3076 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 3077 // CHECK6-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64 3078 // CHECK6-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] 3079 // CHECK6-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 3080 // CHECK6-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] 3081 // CHECK6-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 3082 // CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 3083 // CHECK6-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64 3084 // CHECK6-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] 3085 // CHECK6-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 3086 // CHECK6-NEXT: br label [[FOR_INC:%.*]] 3087 // CHECK6: for.inc: 3088 // CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 3089 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], -7 3090 // CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 3091 // CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] 3092 // CHECK6: for.end: 3093 // CHECK6-NEXT: ret void 3094 // 3095 // 3096 // CHECK6-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_ 3097 // CHECK6-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 3098 // CHECK6-NEXT: entry: 3099 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 3100 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 3101 // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 3102 // CHECK6-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 3103 // CHECK6-NEXT: [[I:%.*]] = alloca i64, align 8 3104 // CHECK6-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 3105 // CHECK6-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 3106 // CHECK6-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 3107 // CHECK6-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 3108 // CHECK6-NEXT: store i64 131071, i64* [[I]], align 8 3109 // CHECK6-NEXT: br label [[FOR_COND:%.*]] 3110 // CHECK6: for.cond: 3111 // CHECK6-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 3112 // CHECK6-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP0]], 2147483647 3113 // CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 3114 // CHECK6: for.body: 3115 // CHECK6-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 3116 // CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[I]], align 8 3117 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[TMP2]] 3118 // CHECK6-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 3119 // CHECK6-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 3120 // CHECK6-NEXT: [[TMP5:%.*]] = load i64, i64* [[I]], align 8 3121 // CHECK6-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[TMP5]] 3122 // CHECK6-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 3123 // CHECK6-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] 3124 // CHECK6-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 3125 // CHECK6-NEXT: [[TMP8:%.*]] = load i64, i64* [[I]], align 8 3126 // CHECK6-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[TMP8]] 3127 // CHECK6-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 3128 // CHECK6-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] 3129 // CHECK6-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 3130 // CHECK6-NEXT: [[TMP11:%.*]] = load i64, i64* [[I]], align 8 3131 // CHECK6-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[TMP11]] 3132 // CHECK6-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 3133 // CHECK6-NEXT: br label [[FOR_INC:%.*]] 3134 // CHECK6: for.inc: 3135 // CHECK6-NEXT: [[TMP12:%.*]] = load i64, i64* [[I]], align 8 3136 // CHECK6-NEXT: [[ADD:%.*]] = add i64 [[TMP12]], 127 3137 // CHECK6-NEXT: store i64 [[ADD]], i64* [[I]], align 8 3138 // CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 3139 // CHECK6: for.end: 3140 // CHECK6-NEXT: ret void 3141 // 3142 // 3143 // CHECK6-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_ 3144 // CHECK6-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 3145 // CHECK6-NEXT: entry: 3146 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 3147 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 3148 // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 3149 // CHECK6-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 3150 // CHECK6-NEXT: [[X:%.*]] = alloca i32, align 4 3151 // CHECK6-NEXT: [[Y:%.*]] = alloca i32, align 4 3152 // CHECK6-NEXT: [[I:%.*]] = alloca i8, align 1 3153 // CHECK6-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 3154 // CHECK6-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 3155 // CHECK6-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 3156 // CHECK6-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 3157 // CHECK6-NEXT: store i32 0, i32* [[X]], align 4 3158 // CHECK6-NEXT: store i32 0, i32* [[Y]], align 4 3159 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[Y]], align 4 3160 // CHECK6-NEXT: [[CONV:%.*]] = trunc i32 [[TMP0]] to i8 3161 // CHECK6-NEXT: store i8 [[CONV]], i8* [[I]], align 1 3162 // CHECK6-NEXT: br label [[FOR_COND:%.*]] 3163 // CHECK6: for.cond: 3164 // CHECK6-NEXT: [[TMP1:%.*]] = load i8, i8* [[I]], align 1 3165 // CHECK6-NEXT: [[CONV1:%.*]] = sext i8 [[TMP1]] to i32 3166 // CHECK6-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV1]], 57 3167 // CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END13:%.*]] 3168 // CHECK6: for.body: 3169 // CHECK6-NEXT: store i32 11, i32* [[X]], align 4 3170 // CHECK6-NEXT: br label [[FOR_COND2:%.*]] 3171 // CHECK6: for.cond2: 3172 // CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[X]], align 4 3173 // CHECK6-NEXT: [[CMP3:%.*]] = icmp ugt i32 [[TMP2]], 0 3174 // CHECK6-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END:%.*]] 3175 // CHECK6: for.body4: 3176 // CHECK6-NEXT: [[TMP3:%.*]] = load float*, float** [[B_ADDR]], align 8 3177 // CHECK6-NEXT: [[TMP4:%.*]] = load i8, i8* [[I]], align 1 3178 // CHECK6-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP4]] to i64 3179 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP3]], i64 [[IDXPROM]] 3180 // CHECK6-NEXT: [[TMP5:%.*]] = load float, float* [[ARRAYIDX]], align 4 3181 // CHECK6-NEXT: [[TMP6:%.*]] = load float*, float** [[C_ADDR]], align 8 3182 // CHECK6-NEXT: [[TMP7:%.*]] = load i8, i8* [[I]], align 1 3183 // CHECK6-NEXT: [[IDXPROM5:%.*]] = sext i8 [[TMP7]] to i64 3184 // CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP6]], i64 [[IDXPROM5]] 3185 // CHECK6-NEXT: [[TMP8:%.*]] = load float, float* [[ARRAYIDX6]], align 4 3186 // CHECK6-NEXT: [[MUL:%.*]] = fmul float [[TMP5]], [[TMP8]] 3187 // CHECK6-NEXT: [[TMP9:%.*]] = load float*, float** [[D_ADDR]], align 8 3188 // CHECK6-NEXT: [[TMP10:%.*]] = load i8, i8* [[I]], align 1 3189 // CHECK6-NEXT: [[IDXPROM7:%.*]] = sext i8 [[TMP10]] to i64 3190 // CHECK6-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP9]], i64 [[IDXPROM7]] 3191 // CHECK6-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX8]], align 4 3192 // CHECK6-NEXT: [[MUL9:%.*]] = fmul float [[MUL]], [[TMP11]] 3193 // CHECK6-NEXT: [[TMP12:%.*]] = load float*, float** [[A_ADDR]], align 8 3194 // CHECK6-NEXT: [[TMP13:%.*]] = load i8, i8* [[I]], align 1 3195 // CHECK6-NEXT: [[IDXPROM10:%.*]] = sext i8 [[TMP13]] to i64 3196 // CHECK6-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM10]] 3197 // CHECK6-NEXT: store float [[MUL9]], float* [[ARRAYIDX11]], align 4 3198 // CHECK6-NEXT: br label [[FOR_INC:%.*]] 3199 // CHECK6: for.inc: 3200 // CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[X]], align 4 3201 // CHECK6-NEXT: [[DEC:%.*]] = add i32 [[TMP14]], -1 3202 // CHECK6-NEXT: store i32 [[DEC]], i32* [[X]], align 4 3203 // CHECK6-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP5:![0-9]+]] 3204 // CHECK6: for.end: 3205 // CHECK6-NEXT: br label [[FOR_INC12:%.*]] 3206 // CHECK6: for.inc12: 3207 // CHECK6-NEXT: [[TMP15:%.*]] = load i8, i8* [[I]], align 1 3208 // CHECK6-NEXT: [[INC:%.*]] = add i8 [[TMP15]], 1 3209 // CHECK6-NEXT: store i8 [[INC]], i8* [[I]], align 1 3210 // CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 3211 // CHECK6: for.end13: 3212 // CHECK6-NEXT: ret void 3213 // 3214 // 3215 // CHECK6-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_ 3216 // CHECK6-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 3217 // CHECK6-NEXT: entry: 3218 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 3219 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 3220 // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 3221 // CHECK6-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 3222 // CHECK6-NEXT: [[X:%.*]] = alloca i32, align 4 3223 // CHECK6-NEXT: [[I:%.*]] = alloca i8, align 1 3224 // CHECK6-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 3225 // CHECK6-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 3226 // CHECK6-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 3227 // CHECK6-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 3228 // CHECK6-NEXT: store i32 0, i32* [[X]], align 4 3229 // CHECK6-NEXT: store i8 48, i8* [[I]], align 1 3230 // CHECK6-NEXT: br label [[FOR_COND:%.*]] 3231 // CHECK6: for.cond: 3232 // CHECK6-NEXT: [[TMP0:%.*]] = load i8, i8* [[I]], align 1 3233 // CHECK6-NEXT: [[CONV:%.*]] = zext i8 [[TMP0]] to i32 3234 // CHECK6-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV]], 57 3235 // CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END13:%.*]] 3236 // CHECK6: for.body: 3237 // CHECK6-NEXT: store i32 -10, i32* [[X]], align 4 3238 // CHECK6-NEXT: br label [[FOR_COND1:%.*]] 3239 // CHECK6: for.cond1: 3240 // CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[X]], align 4 3241 // CHECK6-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP1]], 10 3242 // CHECK6-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] 3243 // CHECK6: for.body3: 3244 // CHECK6-NEXT: [[TMP2:%.*]] = load float*, float** [[B_ADDR]], align 8 3245 // CHECK6-NEXT: [[TMP3:%.*]] = load i8, i8* [[I]], align 1 3246 // CHECK6-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP3]] to i64 3247 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 [[IDXPROM]] 3248 // CHECK6-NEXT: [[TMP4:%.*]] = load float, float* [[ARRAYIDX]], align 4 3249 // CHECK6-NEXT: [[TMP5:%.*]] = load float*, float** [[C_ADDR]], align 8 3250 // CHECK6-NEXT: [[TMP6:%.*]] = load i8, i8* [[I]], align 1 3251 // CHECK6-NEXT: [[IDXPROM4:%.*]] = zext i8 [[TMP6]] to i64 3252 // CHECK6-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP5]], i64 [[IDXPROM4]] 3253 // CHECK6-NEXT: [[TMP7:%.*]] = load float, float* [[ARRAYIDX5]], align 4 3254 // CHECK6-NEXT: [[MUL:%.*]] = fmul float [[TMP4]], [[TMP7]] 3255 // CHECK6-NEXT: [[TMP8:%.*]] = load float*, float** [[D_ADDR]], align 8 3256 // CHECK6-NEXT: [[TMP9:%.*]] = load i8, i8* [[I]], align 1 3257 // CHECK6-NEXT: [[IDXPROM6:%.*]] = zext i8 [[TMP9]] to i64 3258 // CHECK6-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[IDXPROM6]] 3259 // CHECK6-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 3260 // CHECK6-NEXT: [[MUL8:%.*]] = fmul float [[MUL]], [[TMP10]] 3261 // CHECK6-NEXT: [[TMP11:%.*]] = load float*, float** [[A_ADDR]], align 8 3262 // CHECK6-NEXT: [[TMP12:%.*]] = load i8, i8* [[I]], align 1 3263 // CHECK6-NEXT: [[IDXPROM9:%.*]] = zext i8 [[TMP12]] to i64 3264 // CHECK6-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[IDXPROM9]] 3265 // CHECK6-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4 3266 // CHECK6-NEXT: br label [[FOR_INC:%.*]] 3267 // CHECK6: for.inc: 3268 // CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[X]], align 4 3269 // CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP13]], 1 3270 // CHECK6-NEXT: store i32 [[INC]], i32* [[X]], align 4 3271 // CHECK6-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP7:![0-9]+]] 3272 // CHECK6: for.end: 3273 // CHECK6-NEXT: br label [[FOR_INC11:%.*]] 3274 // CHECK6: for.inc11: 3275 // CHECK6-NEXT: [[TMP14:%.*]] = load i8, i8* [[I]], align 1 3276 // CHECK6-NEXT: [[INC12:%.*]] = add i8 [[TMP14]], 1 3277 // CHECK6-NEXT: store i8 [[INC12]], i8* [[I]], align 1 3278 // CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] 3279 // CHECK6: for.end13: 3280 // CHECK6-NEXT: ret void 3281 // 3282 // 3283 // CHECK6-LABEL: define {{[^@]+}}@_Z8foo_simdii 3284 // CHECK6-SAME: (i32 [[LOW:%.*]], i32 [[UP:%.*]]) #[[ATTR0]] { 3285 // CHECK6-NEXT: entry: 3286 // CHECK6-NEXT: [[LOW_ADDR:%.*]] = alloca i32, align 4 3287 // CHECK6-NEXT: [[UP_ADDR:%.*]] = alloca i32, align 4 3288 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 3289 // CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 3290 // CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 3291 // CHECK6-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 3292 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 3293 // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3294 // CHECK6-NEXT: [[I5:%.*]] = alloca i32, align 4 3295 // CHECK6-NEXT: [[_TMP18:%.*]] = alloca i32, align 4 3296 // CHECK6-NEXT: [[DOTCAPTURE_EXPR_19:%.*]] = alloca i32, align 4 3297 // CHECK6-NEXT: [[DOTCAPTURE_EXPR_20:%.*]] = alloca i32, align 4 3298 // CHECK6-NEXT: [[DOTCAPTURE_EXPR_21:%.*]] = alloca i32, align 4 3299 // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3300 // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3301 // CHECK6-NEXT: [[I27:%.*]] = alloca i32, align 4 3302 // CHECK6-NEXT: [[DOTOMP_IV30:%.*]] = alloca i32, align 4 3303 // CHECK6-NEXT: [[I31:%.*]] = alloca i32, align 4 3304 // CHECK6-NEXT: store i32 [[LOW]], i32* [[LOW_ADDR]], align 4 3305 // CHECK6-NEXT: store i32 [[UP]], i32* [[UP_ADDR]], align 4 3306 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[LOW_ADDR]], align 4 3307 // CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 3308 // CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[UP_ADDR]], align 4 3309 // CHECK6-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_1]], align 4 3310 // CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 3311 // CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3312 // CHECK6-NEXT: [[SUB:%.*]] = sub i32 [[TMP2]], [[TMP3]] 3313 // CHECK6-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1 3314 // CHECK6-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1 3315 // CHECK6-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 3316 // CHECK6-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1 3317 // CHECK6-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4 3318 // CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3319 // CHECK6-NEXT: store i32 [[TMP4]], i32* [[I]], align 4 3320 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3321 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 3322 // CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], [[TMP6]] 3323 // CHECK6-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]] 3324 // CHECK6: simd.if.then: 3325 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IV]], align 4 3326 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3327 // CHECK6: omp.inner.for.cond: 3328 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 3329 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !9 3330 // CHECK6-NEXT: [[ADD6:%.*]] = add i32 [[TMP8]], 1 3331 // CHECK6-NEXT: [[CMP7:%.*]] = icmp ult i32 [[TMP7]], [[ADD6]] 3332 // CHECK6-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3333 // CHECK6: omp.inner.for.body: 3334 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !9 3335 // CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 3336 // CHECK6-NEXT: [[MUL:%.*]] = mul i32 [[TMP10]], 1 3337 // CHECK6-NEXT: [[ADD8:%.*]] = add i32 [[TMP9]], [[MUL]] 3338 // CHECK6-NEXT: store i32 [[ADD8]], i32* [[I5]], align 4, !llvm.access.group !9 3339 // CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[I5]], align 4, !llvm.access.group !9 3340 // CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 3341 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM]] 3342 // CHECK6-NEXT: store float 0.000000e+00, float* [[ARRAYIDX]], align 4, !llvm.access.group !9 3343 // CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[I5]], align 4, !llvm.access.group !9 3344 // CHECK6-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP12]] to i64 3345 // CHECK6-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM9]] 3346 // CHECK6-NEXT: store float 1.000000e+00, float* [[ARRAYIDX10]], align 4, !llvm.access.group !9 3347 // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3348 // CHECK6: omp.body.continue: 3349 // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3350 // CHECK6: omp.inner.for.inc: 3351 // CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 3352 // CHECK6-NEXT: [[ADD11:%.*]] = add i32 [[TMP13]], 1 3353 // CHECK6-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 3354 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] 3355 // CHECK6: omp.inner.for.end: 3356 // CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3357 // CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 3358 // CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3359 // CHECK6-NEXT: [[SUB12:%.*]] = sub i32 [[TMP15]], [[TMP16]] 3360 // CHECK6-NEXT: [[SUB13:%.*]] = sub i32 [[SUB12]], 1 3361 // CHECK6-NEXT: [[ADD14:%.*]] = add i32 [[SUB13]], 1 3362 // CHECK6-NEXT: [[DIV15:%.*]] = udiv i32 [[ADD14]], 1 3363 // CHECK6-NEXT: [[MUL16:%.*]] = mul i32 [[DIV15]], 1 3364 // CHECK6-NEXT: [[ADD17:%.*]] = add i32 [[TMP14]], [[MUL16]] 3365 // CHECK6-NEXT: store i32 [[ADD17]], i32* [[I5]], align 4 3366 // CHECK6-NEXT: br label [[SIMD_IF_END]] 3367 // CHECK6: simd.if.end: 3368 // CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[LOW_ADDR]], align 4 3369 // CHECK6-NEXT: store i32 [[TMP17]], i32* [[DOTCAPTURE_EXPR_19]], align 4 3370 // CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[UP_ADDR]], align 4 3371 // CHECK6-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_20]], align 4 3372 // CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_20]], align 4 3373 // CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 3374 // CHECK6-NEXT: [[SUB22:%.*]] = sub i32 [[TMP19]], [[TMP20]] 3375 // CHECK6-NEXT: [[SUB23:%.*]] = sub i32 [[SUB22]], 1 3376 // CHECK6-NEXT: [[ADD24:%.*]] = add i32 [[SUB23]], 1 3377 // CHECK6-NEXT: [[DIV25:%.*]] = udiv i32 [[ADD24]], 1 3378 // CHECK6-NEXT: [[SUB26:%.*]] = sub i32 [[DIV25]], 1 3379 // CHECK6-NEXT: store i32 [[SUB26]], i32* [[DOTCAPTURE_EXPR_21]], align 4 3380 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3381 // CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_21]], align 4 3382 // CHECK6-NEXT: store i32 [[TMP21]], i32* [[DOTOMP_UB]], align 4 3383 // CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 3384 // CHECK6-NEXT: store i32 [[TMP22]], i32* [[I27]], align 4 3385 // CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 3386 // CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_20]], align 4 3387 // CHECK6-NEXT: [[CMP28:%.*]] = icmp slt i32 [[TMP23]], [[TMP24]] 3388 // CHECK6-NEXT: br i1 [[CMP28]], label [[SIMD_IF_THEN29:%.*]], label [[SIMD_IF_END52:%.*]] 3389 // CHECK6: simd.if.then29: 3390 // CHECK6-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3391 // CHECK6-NEXT: store i32 [[TMP25]], i32* [[DOTOMP_IV30]], align 4 3392 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND32:%.*]] 3393 // CHECK6: omp.inner.for.cond32: 3394 // CHECK6-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_IV30]], align 4, !llvm.access.group !13 3395 // CHECK6-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 3396 // CHECK6-NEXT: [[ADD33:%.*]] = add i32 [[TMP27]], 1 3397 // CHECK6-NEXT: [[CMP34:%.*]] = icmp ult i32 [[TMP26]], [[ADD33]] 3398 // CHECK6-NEXT: br i1 [[CMP34]], label [[OMP_INNER_FOR_BODY35:%.*]], label [[OMP_INNER_FOR_END45:%.*]] 3399 // CHECK6: omp.inner.for.body35: 3400 // CHECK6-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4, !llvm.access.group !13 3401 // CHECK6-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV30]], align 4, !llvm.access.group !13 3402 // CHECK6-NEXT: [[MUL36:%.*]] = mul i32 [[TMP29]], 1 3403 // CHECK6-NEXT: [[ADD37:%.*]] = add i32 [[TMP28]], [[MUL36]] 3404 // CHECK6-NEXT: store i32 [[ADD37]], i32* [[I31]], align 4, !llvm.access.group !13 3405 // CHECK6-NEXT: [[TMP30:%.*]] = load i32, i32* [[I31]], align 4, !llvm.access.group !13 3406 // CHECK6-NEXT: [[IDXPROM38:%.*]] = sext i32 [[TMP30]] to i64 3407 // CHECK6-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM38]] 3408 // CHECK6-NEXT: store float 0.000000e+00, float* [[ARRAYIDX39]], align 4, !llvm.access.group !13 3409 // CHECK6-NEXT: [[TMP31:%.*]] = load i32, i32* [[I31]], align 4, !llvm.access.group !13 3410 // CHECK6-NEXT: [[IDXPROM40:%.*]] = sext i32 [[TMP31]] to i64 3411 // CHECK6-NEXT: [[ARRAYIDX41:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM40]] 3412 // CHECK6-NEXT: store float 1.000000e+00, float* [[ARRAYIDX41]], align 4, !llvm.access.group !13 3413 // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE42:%.*]] 3414 // CHECK6: omp.body.continue42: 3415 // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC43:%.*]] 3416 // CHECK6: omp.inner.for.inc43: 3417 // CHECK6-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IV30]], align 4, !llvm.access.group !13 3418 // CHECK6-NEXT: [[ADD44:%.*]] = add i32 [[TMP32]], 1 3419 // CHECK6-NEXT: store i32 [[ADD44]], i32* [[DOTOMP_IV30]], align 4, !llvm.access.group !13 3420 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND32]], !llvm.loop [[LOOP14:![0-9]+]] 3421 // CHECK6: omp.inner.for.end45: 3422 // CHECK6-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 3423 // CHECK6-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_20]], align 4 3424 // CHECK6-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 3425 // CHECK6-NEXT: [[SUB46:%.*]] = sub i32 [[TMP34]], [[TMP35]] 3426 // CHECK6-NEXT: [[SUB47:%.*]] = sub i32 [[SUB46]], 1 3427 // CHECK6-NEXT: [[ADD48:%.*]] = add i32 [[SUB47]], 1 3428 // CHECK6-NEXT: [[DIV49:%.*]] = udiv i32 [[ADD48]], 1 3429 // CHECK6-NEXT: [[MUL50:%.*]] = mul i32 [[DIV49]], 1 3430 // CHECK6-NEXT: [[ADD51:%.*]] = add i32 [[TMP33]], [[MUL50]] 3431 // CHECK6-NEXT: store i32 [[ADD51]], i32* [[I31]], align 4 3432 // CHECK6-NEXT: br label [[SIMD_IF_END52]] 3433 // CHECK6: simd.if.end52: 3434 // CHECK6-NEXT: ret void 3435 // 3436