1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-function-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" --prefix-filecheck-ir-name _ 2 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK1 3 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s 4 // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 5 6 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -fopenmp-version=45 -o - | FileCheck %s --check-prefix=CHECK3 7 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -fopenmp-version=45 -o %t %s 8 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 9 10 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK5 11 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s 12 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 13 // expected-no-diagnostics 14 #ifndef HEADER 15 #define HEADER 16 17 void static_not_chunked(float *a, float *b, float *c, float *d) { 18 #pragma omp for schedule(static) ordered 19 20 // Loop header 21 22 for (int i = 32000000; i > 33; i += -7) { 23 // Start of body: calculate i from IV: 24 25 // ... start of ordered region ... 26 // ... loop body ... 27 // End of body: store into a[i]: 28 // ... end of ordered region ... 29 #pragma omp ordered 30 a[i] = b[i] * c[i] * d[i]; 31 } 32 } 33 34 void dynamic1(float *a, float *b, float *c, float *d) { 35 #pragma omp for schedule(dynamic) ordered 36 37 // Loop header 38 39 for (unsigned long long i = 131071; i < 2147483647; i += 127) { 40 // Start of body: calculate i from IV: 41 42 // ... start of ordered region ... 43 // ... loop body ... 44 // End of body: store into a[i]: 45 // ... end of ordered region ... 46 #pragma omp ordered threads 47 a[i] = b[i] * c[i] * d[i]; 48 49 // ... end iteration for ordered loop ... 50 } 51 } 52 53 void test_auto(float *a, float *b, float *c, float *d) { 54 unsigned int x = 0; 55 unsigned int y = 0; 56 #pragma omp for schedule(auto) collapse(2) ordered 57 58 // Loop header 59 60 // FIXME: When the iteration count of some nested loop is not a known constant, 61 // we should pre-calculate it, like we do for the total number of iterations! 62 for (char i = static_cast<char>(y); i <= '9'; ++i) 63 for (x = 11; x > 0; --x) { 64 // Start of body: indices are calculated from IV: 65 66 // ... start of ordered region ... 67 // ... loop body ... 68 // End of body: store into a[i]: 69 // ... end of ordered region ... 70 #pragma omp ordered 71 a[i] = b[i] * c[i] * d[i]; 72 73 // ... end iteration for ordered loop ... 74 } 75 } 76 77 void runtime(float *a, float *b, float *c, float *d) { 78 int x = 0; 79 #pragma omp for collapse(2) schedule(runtime) ordered 80 81 // Loop header 82 83 for (unsigned char i = '0' ; i <= '9'; ++i) 84 for (x = -10; x < 10; ++x) { 85 // Start of body: indices are calculated from IV: 86 87 // ... start of ordered region ... 88 // ... loop body ... 89 // End of body: store into a[i]: 90 // ... end of ordered region ... 91 #pragma omp ordered threads 92 a[i] = b[i] * c[i] * d[i]; 93 94 // ... end iteration for ordered loop ... 95 } 96 } 97 98 float f[10]; 99 void foo_simd(int low, int up) { 100 #pragma omp simd 101 for (int i = low; i < up; ++i) { 102 f[i] = 0.0; 103 #pragma omp ordered simd 104 f[i] = 1.0; 105 } 106 #pragma omp for simd ordered 107 for (int i = low; i < up; ++i) { 108 f[i] = 0.0; 109 #pragma omp ordered simd 110 f[i] = 1.0; 111 } 112 } 113 114 115 #endif // HEADER 116 117 // CHECK1-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 118 // CHECK1-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { 119 // CHECK1-NEXT: entry: 120 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 121 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 122 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 123 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 124 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 125 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 126 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 127 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 128 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 129 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 130 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 131 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 132 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 133 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 134 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 135 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 136 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 137 // CHECK1-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 138 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 139 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 140 // CHECK1-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 66, i32 0, i32 4571423, i32 1, i32 1) 141 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 142 // CHECK1: omp.dispatch.cond: 143 // CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 144 // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 145 // CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 146 // CHECK1: omp.dispatch.body: 147 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 148 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_IV]], align 4 149 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 150 // CHECK1: omp.inner.for.cond: 151 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 152 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 153 // CHECK1-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP3]], [[TMP4]] 154 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 155 // CHECK1: omp.inner.for.body: 156 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 157 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP5]], 7 158 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 159 // CHECK1-NEXT: store i32 [[SUB]], i32* [[I]], align 4 160 // CHECK1-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 161 // CHECK1-NEXT: [[TMP6:%.*]] = load float*, float** [[B_ADDR]], align 8 162 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 163 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 164 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP6]], i64 [[IDXPROM]] 165 // CHECK1-NEXT: [[TMP8:%.*]] = load float, float* [[ARRAYIDX]], align 4 166 // CHECK1-NEXT: [[TMP9:%.*]] = load float*, float** [[C_ADDR]], align 8 167 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 168 // CHECK1-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP10]] to i64 169 // CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP9]], i64 [[IDXPROM1]] 170 // CHECK1-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX2]], align 4 171 // CHECK1-NEXT: [[MUL3:%.*]] = fmul float [[TMP8]], [[TMP11]] 172 // CHECK1-NEXT: [[TMP12:%.*]] = load float*, float** [[D_ADDR]], align 8 173 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 174 // CHECK1-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP13]] to i64 175 // CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM4]] 176 // CHECK1-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX5]], align 4 177 // CHECK1-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP14]] 178 // CHECK1-NEXT: [[TMP15:%.*]] = load float*, float** [[A_ADDR]], align 8 179 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 180 // CHECK1-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP16]] to i64 181 // CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM7]] 182 // CHECK1-NEXT: store float [[MUL6]], float* [[ARRAYIDX8]], align 4 183 // CHECK1-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 184 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 185 // CHECK1: omp.body.continue: 186 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 187 // CHECK1: omp.inner.for.inc: 188 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 189 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP17]], 1 190 // CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 191 // CHECK1-NEXT: call void @__kmpc_dispatch_fini_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 192 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 193 // CHECK1: omp.inner.for.end: 194 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 195 // CHECK1: omp.dispatch.inc: 196 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 197 // CHECK1: omp.dispatch.end: 198 // CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP0]]) 199 // CHECK1-NEXT: ret void 200 // 201 // 202 // CHECK1-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_ 203 // CHECK1-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 204 // CHECK1-NEXT: entry: 205 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 206 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 207 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 208 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 209 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 210 // CHECK1-NEXT: [[TMP:%.*]] = alloca i64, align 8 211 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 212 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 213 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 214 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 215 // CHECK1-NEXT: [[I:%.*]] = alloca i64, align 8 216 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 217 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 218 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 219 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 220 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 221 // CHECK1-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 222 // CHECK1-NEXT: store i64 16908287, i64* [[DOTOMP_UB]], align 8 223 // CHECK1-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 224 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 225 // CHECK1-NEXT: call void @__kmpc_dispatch_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1073741891, i64 0, i64 16908287, i64 1, i64 1) 226 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 227 // CHECK1: omp.dispatch.cond: 228 // CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 229 // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 230 // CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 231 // CHECK1: omp.dispatch.body: 232 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 233 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[DOTOMP_IV]], align 8 234 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 235 // CHECK1: omp.inner.for.cond: 236 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 237 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 238 // CHECK1-NEXT: [[ADD:%.*]] = add i64 [[TMP4]], 1 239 // CHECK1-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP3]], [[ADD]] 240 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 241 // CHECK1: omp.inner.for.body: 242 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 243 // CHECK1-NEXT: [[MUL:%.*]] = mul i64 [[TMP5]], 127 244 // CHECK1-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]] 245 // CHECK1-NEXT: store i64 [[ADD1]], i64* [[I]], align 8 246 // CHECK1-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 247 // CHECK1-NEXT: [[TMP6:%.*]] = load float*, float** [[B_ADDR]], align 8 248 // CHECK1-NEXT: [[TMP7:%.*]] = load i64, i64* [[I]], align 8 249 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP6]], i64 [[TMP7]] 250 // CHECK1-NEXT: [[TMP8:%.*]] = load float, float* [[ARRAYIDX]], align 4 251 // CHECK1-NEXT: [[TMP9:%.*]] = load float*, float** [[C_ADDR]], align 8 252 // CHECK1-NEXT: [[TMP10:%.*]] = load i64, i64* [[I]], align 8 253 // CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP9]], i64 [[TMP10]] 254 // CHECK1-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX2]], align 4 255 // CHECK1-NEXT: [[MUL3:%.*]] = fmul float [[TMP8]], [[TMP11]] 256 // CHECK1-NEXT: [[TMP12:%.*]] = load float*, float** [[D_ADDR]], align 8 257 // CHECK1-NEXT: [[TMP13:%.*]] = load i64, i64* [[I]], align 8 258 // CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[TMP13]] 259 // CHECK1-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX4]], align 4 260 // CHECK1-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP14]] 261 // CHECK1-NEXT: [[TMP15:%.*]] = load float*, float** [[A_ADDR]], align 8 262 // CHECK1-NEXT: [[TMP16:%.*]] = load i64, i64* [[I]], align 8 263 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[TMP16]] 264 // CHECK1-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4 265 // CHECK1-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 266 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 267 // CHECK1: omp.body.continue: 268 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 269 // CHECK1: omp.inner.for.inc: 270 // CHECK1-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 271 // CHECK1-NEXT: [[ADD7:%.*]] = add i64 [[TMP17]], 1 272 // CHECK1-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 273 // CHECK1-NEXT: call void @__kmpc_dispatch_fini_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 274 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 275 // CHECK1: omp.inner.for.end: 276 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 277 // CHECK1: omp.dispatch.inc: 278 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 279 // CHECK1: omp.dispatch.end: 280 // CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 281 // CHECK1-NEXT: ret void 282 // 283 // 284 // CHECK1-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_ 285 // CHECK1-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 286 // CHECK1-NEXT: entry: 287 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 288 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 289 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 290 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 291 // CHECK1-NEXT: [[X:%.*]] = alloca i32, align 4 292 // CHECK1-NEXT: [[Y:%.*]] = alloca i32, align 4 293 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 294 // CHECK1-NEXT: [[TMP:%.*]] = alloca i8, align 1 295 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 296 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 297 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8 298 // CHECK1-NEXT: [[I:%.*]] = alloca i8, align 1 299 // CHECK1-NEXT: [[X6:%.*]] = alloca i32, align 4 300 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 301 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 302 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 303 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 304 // CHECK1-NEXT: [[I8:%.*]] = alloca i8, align 1 305 // CHECK1-NEXT: [[X9:%.*]] = alloca i32, align 4 306 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 307 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 308 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 309 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 310 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 311 // CHECK1-NEXT: store i32 0, i32* [[X]], align 4 312 // CHECK1-NEXT: store i32 0, i32* [[Y]], align 4 313 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[Y]], align 4 314 // CHECK1-NEXT: [[CONV:%.*]] = trunc i32 [[TMP1]] to i8 315 // CHECK1-NEXT: store i8 [[CONV]], i8* [[DOTCAPTURE_EXPR_]], align 1 316 // CHECK1-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 317 // CHECK1-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 318 // CHECK1-NEXT: [[SUB:%.*]] = sub i32 57, [[CONV3]] 319 // CHECK1-NEXT: [[ADD:%.*]] = add i32 [[SUB]], 1 320 // CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 321 // CHECK1-NEXT: [[CONV4:%.*]] = zext i32 [[DIV]] to i64 322 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV4]], 11 323 // CHECK1-NEXT: [[SUB5:%.*]] = sub nsw i64 [[MUL]], 1 324 // CHECK1-NEXT: store i64 [[SUB5]], i64* [[DOTCAPTURE_EXPR_2]], align 8 325 // CHECK1-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 326 // CHECK1-NEXT: store i8 [[TMP3]], i8* [[I]], align 1 327 // CHECK1-NEXT: store i32 11, i32* [[X6]], align 4 328 // CHECK1-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 329 // CHECK1-NEXT: [[CONV7:%.*]] = sext i8 [[TMP4]] to i32 330 // CHECK1-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV7]], 57 331 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 332 // CHECK1: omp.precond.then: 333 // CHECK1-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 334 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 335 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_UB]], align 8 336 // CHECK1-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 337 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 338 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 339 // CHECK1-NEXT: call void @__kmpc_dispatch_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1073741894, i64 0, i64 [[TMP6]], i64 1, i64 1) 340 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 341 // CHECK1: omp.dispatch.cond: 342 // CHECK1-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_dispatch_next_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 343 // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0 344 // CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 345 // CHECK1: omp.dispatch.body: 346 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 347 // CHECK1-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 348 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 349 // CHECK1: omp.inner.for.cond: 350 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 351 // CHECK1-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 352 // CHECK1-NEXT: [[CMP10:%.*]] = icmp sle i64 [[TMP9]], [[TMP10]] 353 // CHECK1-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 354 // CHECK1: omp.inner.for.body: 355 // CHECK1-NEXT: [[TMP11:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 356 // CHECK1-NEXT: [[CONV11:%.*]] = sext i8 [[TMP11]] to i64 357 // CHECK1-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 358 // CHECK1-NEXT: [[DIV12:%.*]] = sdiv i64 [[TMP12]], 11 359 // CHECK1-NEXT: [[MUL13:%.*]] = mul nsw i64 [[DIV12]], 1 360 // CHECK1-NEXT: [[ADD14:%.*]] = add nsw i64 [[CONV11]], [[MUL13]] 361 // CHECK1-NEXT: [[CONV15:%.*]] = trunc i64 [[ADD14]] to i8 362 // CHECK1-NEXT: store i8 [[CONV15]], i8* [[I8]], align 1 363 // CHECK1-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 364 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 365 // CHECK1-NEXT: [[DIV16:%.*]] = sdiv i64 [[TMP14]], 11 366 // CHECK1-NEXT: [[MUL17:%.*]] = mul nsw i64 [[DIV16]], 11 367 // CHECK1-NEXT: [[SUB18:%.*]] = sub nsw i64 [[TMP13]], [[MUL17]] 368 // CHECK1-NEXT: [[MUL19:%.*]] = mul nsw i64 [[SUB18]], 1 369 // CHECK1-NEXT: [[SUB20:%.*]] = sub nsw i64 11, [[MUL19]] 370 // CHECK1-NEXT: [[CONV21:%.*]] = trunc i64 [[SUB20]] to i32 371 // CHECK1-NEXT: store i32 [[CONV21]], i32* [[X9]], align 4 372 // CHECK1-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 373 // CHECK1-NEXT: [[TMP15:%.*]] = load float*, float** [[B_ADDR]], align 8 374 // CHECK1-NEXT: [[TMP16:%.*]] = load i8, i8* [[I8]], align 1 375 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP16]] to i64 376 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM]] 377 // CHECK1-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4 378 // CHECK1-NEXT: [[TMP18:%.*]] = load float*, float** [[C_ADDR]], align 8 379 // CHECK1-NEXT: [[TMP19:%.*]] = load i8, i8* [[I8]], align 1 380 // CHECK1-NEXT: [[IDXPROM22:%.*]] = sext i8 [[TMP19]] to i64 381 // CHECK1-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM22]] 382 // CHECK1-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX23]], align 4 383 // CHECK1-NEXT: [[MUL24:%.*]] = fmul float [[TMP17]], [[TMP20]] 384 // CHECK1-NEXT: [[TMP21:%.*]] = load float*, float** [[D_ADDR]], align 8 385 // CHECK1-NEXT: [[TMP22:%.*]] = load i8, i8* [[I8]], align 1 386 // CHECK1-NEXT: [[IDXPROM25:%.*]] = sext i8 [[TMP22]] to i64 387 // CHECK1-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM25]] 388 // CHECK1-NEXT: [[TMP23:%.*]] = load float, float* [[ARRAYIDX26]], align 4 389 // CHECK1-NEXT: [[MUL27:%.*]] = fmul float [[MUL24]], [[TMP23]] 390 // CHECK1-NEXT: [[TMP24:%.*]] = load float*, float** [[A_ADDR]], align 8 391 // CHECK1-NEXT: [[TMP25:%.*]] = load i8, i8* [[I8]], align 1 392 // CHECK1-NEXT: [[IDXPROM28:%.*]] = sext i8 [[TMP25]] to i64 393 // CHECK1-NEXT: [[ARRAYIDX29:%.*]] = getelementptr inbounds float, float* [[TMP24]], i64 [[IDXPROM28]] 394 // CHECK1-NEXT: store float [[MUL27]], float* [[ARRAYIDX29]], align 4 395 // CHECK1-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 396 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 397 // CHECK1: omp.body.continue: 398 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 399 // CHECK1: omp.inner.for.inc: 400 // CHECK1-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 401 // CHECK1-NEXT: [[ADD30:%.*]] = add nsw i64 [[TMP26]], 1 402 // CHECK1-NEXT: store i64 [[ADD30]], i64* [[DOTOMP_IV]], align 8 403 // CHECK1-NEXT: call void @__kmpc_dispatch_fini_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 404 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 405 // CHECK1: omp.inner.for.end: 406 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 407 // CHECK1: omp.dispatch.inc: 408 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 409 // CHECK1: omp.dispatch.end: 410 // CHECK1-NEXT: br label [[OMP_PRECOND_END]] 411 // CHECK1: omp.precond.end: 412 // CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 413 // CHECK1-NEXT: ret void 414 // 415 // 416 // CHECK1-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_ 417 // CHECK1-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 418 // CHECK1-NEXT: entry: 419 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 420 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 421 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 422 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 423 // CHECK1-NEXT: [[X:%.*]] = alloca i32, align 4 424 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 425 // CHECK1-NEXT: [[TMP:%.*]] = alloca i8, align 1 426 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 427 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 428 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 429 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 430 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 431 // CHECK1-NEXT: [[I:%.*]] = alloca i8, align 1 432 // CHECK1-NEXT: [[X2:%.*]] = alloca i32, align 4 433 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 434 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 435 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 436 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 437 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 438 // CHECK1-NEXT: store i32 0, i32* [[X]], align 4 439 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 440 // CHECK1-NEXT: store i32 199, i32* [[DOTOMP_UB]], align 4 441 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 442 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 443 // CHECK1-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1073741893, i32 0, i32 199, i32 1, i32 1) 444 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 445 // CHECK1: omp.dispatch.cond: 446 // CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 447 // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 448 // CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 449 // CHECK1: omp.dispatch.body: 450 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 451 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_IV]], align 4 452 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 453 // CHECK1: omp.inner.for.cond: 454 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 455 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 456 // CHECK1-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP3]], [[TMP4]] 457 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 458 // CHECK1: omp.inner.for.body: 459 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 460 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 20 461 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 462 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 48, [[MUL]] 463 // CHECK1-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i8 464 // CHECK1-NEXT: store i8 [[CONV]], i8* [[I]], align 1 465 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 466 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 467 // CHECK1-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP7]], 20 468 // CHECK1-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 20 469 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP6]], [[MUL4]] 470 // CHECK1-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 471 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 -10, [[MUL5]] 472 // CHECK1-NEXT: store i32 [[ADD6]], i32* [[X2]], align 4 473 // CHECK1-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 474 // CHECK1-NEXT: [[TMP8:%.*]] = load float*, float** [[B_ADDR]], align 8 475 // CHECK1-NEXT: [[TMP9:%.*]] = load i8, i8* [[I]], align 1 476 // CHECK1-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP9]] to i64 477 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[IDXPROM]] 478 // CHECK1-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX]], align 4 479 // CHECK1-NEXT: [[TMP11:%.*]] = load float*, float** [[C_ADDR]], align 8 480 // CHECK1-NEXT: [[TMP12:%.*]] = load i8, i8* [[I]], align 1 481 // CHECK1-NEXT: [[IDXPROM7:%.*]] = zext i8 [[TMP12]] to i64 482 // CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[IDXPROM7]] 483 // CHECK1-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX8]], align 4 484 // CHECK1-NEXT: [[MUL9:%.*]] = fmul float [[TMP10]], [[TMP13]] 485 // CHECK1-NEXT: [[TMP14:%.*]] = load float*, float** [[D_ADDR]], align 8 486 // CHECK1-NEXT: [[TMP15:%.*]] = load i8, i8* [[I]], align 1 487 // CHECK1-NEXT: [[IDXPROM10:%.*]] = zext i8 [[TMP15]] to i64 488 // CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM10]] 489 // CHECK1-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX11]], align 4 490 // CHECK1-NEXT: [[MUL12:%.*]] = fmul float [[MUL9]], [[TMP16]] 491 // CHECK1-NEXT: [[TMP17:%.*]] = load float*, float** [[A_ADDR]], align 8 492 // CHECK1-NEXT: [[TMP18:%.*]] = load i8, i8* [[I]], align 1 493 // CHECK1-NEXT: [[IDXPROM13:%.*]] = zext i8 [[TMP18]] to i64 494 // CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM13]] 495 // CHECK1-NEXT: store float [[MUL12]], float* [[ARRAYIDX14]], align 4 496 // CHECK1-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 497 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 498 // CHECK1: omp.body.continue: 499 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 500 // CHECK1: omp.inner.for.inc: 501 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 502 // CHECK1-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP19]], 1 503 // CHECK1-NEXT: store i32 [[ADD15]], i32* [[DOTOMP_IV]], align 4 504 // CHECK1-NEXT: call void @__kmpc_dispatch_fini_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 505 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 506 // CHECK1: omp.inner.for.end: 507 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 508 // CHECK1: omp.dispatch.inc: 509 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 510 // CHECK1: omp.dispatch.end: 511 // CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 512 // CHECK1-NEXT: ret void 513 // 514 // 515 // CHECK1-LABEL: define {{[^@]+}}@_Z8foo_simdii 516 // CHECK1-SAME: (i32 [[LOW:%.*]], i32 [[UP:%.*]]) #[[ATTR0]] { 517 // CHECK1-NEXT: entry: 518 // CHECK1-NEXT: [[LOW_ADDR:%.*]] = alloca i32, align 4 519 // CHECK1-NEXT: [[UP_ADDR:%.*]] = alloca i32, align 4 520 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 521 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 522 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 523 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 524 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 525 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 526 // CHECK1-NEXT: [[I5:%.*]] = alloca i32, align 4 527 // CHECK1-NEXT: [[DOTOMP_IV16:%.*]] = alloca i32, align 4 528 // CHECK1-NEXT: [[_TMP17:%.*]] = alloca i32, align 4 529 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_18:%.*]] = alloca i32, align 4 530 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_19:%.*]] = alloca i32, align 4 531 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_20:%.*]] = alloca i32, align 4 532 // CHECK1-NEXT: [[I26:%.*]] = alloca i32, align 4 533 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 534 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 535 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 536 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 537 // CHECK1-NEXT: [[I28:%.*]] = alloca i32, align 4 538 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 539 // CHECK1-NEXT: store i32 [[LOW]], i32* [[LOW_ADDR]], align 4 540 // CHECK1-NEXT: store i32 [[UP]], i32* [[UP_ADDR]], align 4 541 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[LOW_ADDR]], align 4 542 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 543 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[UP_ADDR]], align 4 544 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 545 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 546 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 547 // CHECK1-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] 548 // CHECK1-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1 549 // CHECK1-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1 550 // CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 551 // CHECK1-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1 552 // CHECK1-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4 553 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 554 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 555 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 556 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 557 // CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] 558 // CHECK1-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]] 559 // CHECK1: simd.if.then: 560 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IV]], align 4 561 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 562 // CHECK1: omp.inner.for.cond: 563 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 564 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !2 565 // CHECK1-NEXT: [[ADD6:%.*]] = add i32 [[TMP9]], 1 566 // CHECK1-NEXT: [[CMP7:%.*]] = icmp ult i32 [[TMP8]], [[ADD6]] 567 // CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 568 // CHECK1: omp.inner.for.body: 569 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !2 570 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 571 // CHECK1-NEXT: [[MUL:%.*]] = mul i32 [[TMP11]], 1 572 // CHECK1-NEXT: [[ADD8:%.*]] = add i32 [[TMP10]], [[MUL]] 573 // CHECK1-NEXT: store i32 [[ADD8]], i32* [[I5]], align 4, !llvm.access.group !2 574 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[I5]], align 4, !llvm.access.group !2 575 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64 576 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM]] 577 // CHECK1-NEXT: store float 0.000000e+00, float* [[ARRAYIDX]], align 4, !llvm.access.group !2 578 // CHECK1-NEXT: call void @__captured_stmt(i32* [[I5]]), !llvm.access.group !2 579 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 580 // CHECK1: omp.body.continue: 581 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 582 // CHECK1: omp.inner.for.inc: 583 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 584 // CHECK1-NEXT: [[ADD9:%.*]] = add i32 [[TMP13]], 1 585 // CHECK1-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 586 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 587 // CHECK1: omp.inner.for.end: 588 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 589 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 590 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 591 // CHECK1-NEXT: [[SUB10:%.*]] = sub i32 [[TMP15]], [[TMP16]] 592 // CHECK1-NEXT: [[SUB11:%.*]] = sub i32 [[SUB10]], 1 593 // CHECK1-NEXT: [[ADD12:%.*]] = add i32 [[SUB11]], 1 594 // CHECK1-NEXT: [[DIV13:%.*]] = udiv i32 [[ADD12]], 1 595 // CHECK1-NEXT: [[MUL14:%.*]] = mul i32 [[DIV13]], 1 596 // CHECK1-NEXT: [[ADD15:%.*]] = add i32 [[TMP14]], [[MUL14]] 597 // CHECK1-NEXT: store i32 [[ADD15]], i32* [[I5]], align 4 598 // CHECK1-NEXT: br label [[SIMD_IF_END]] 599 // CHECK1: simd.if.end: 600 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[LOW_ADDR]], align 4 601 // CHECK1-NEXT: store i32 [[TMP17]], i32* [[DOTCAPTURE_EXPR_18]], align 4 602 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[UP_ADDR]], align 4 603 // CHECK1-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_19]], align 4 604 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 605 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 606 // CHECK1-NEXT: [[SUB21:%.*]] = sub i32 [[TMP19]], [[TMP20]] 607 // CHECK1-NEXT: [[SUB22:%.*]] = sub i32 [[SUB21]], 1 608 // CHECK1-NEXT: [[ADD23:%.*]] = add i32 [[SUB22]], 1 609 // CHECK1-NEXT: [[DIV24:%.*]] = udiv i32 [[ADD23]], 1 610 // CHECK1-NEXT: [[SUB25:%.*]] = sub i32 [[DIV24]], 1 611 // CHECK1-NEXT: store i32 [[SUB25]], i32* [[DOTCAPTURE_EXPR_20]], align 4 612 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 613 // CHECK1-NEXT: store i32 [[TMP21]], i32* [[I26]], align 4 614 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 615 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 616 // CHECK1-NEXT: [[CMP27:%.*]] = icmp slt i32 [[TMP22]], [[TMP23]] 617 // CHECK1-NEXT: br i1 [[CMP27]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 618 // CHECK1: omp.precond.then: 619 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 620 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_20]], align 4 621 // CHECK1-NEXT: store i32 [[TMP24]], i32* [[DOTOMP_UB]], align 4 622 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 623 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 624 // CHECK1-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_20]], align 4 625 // CHECK1-NEXT: call void @__kmpc_dispatch_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 66, i32 0, i32 [[TMP25]], i32 1, i32 1) 626 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 627 // CHECK1: omp.dispatch.cond: 628 // CHECK1-NEXT: [[TMP26:%.*]] = call i32 @__kmpc_dispatch_next_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 629 // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP26]], 0 630 // CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 631 // CHECK1: omp.dispatch.body: 632 // CHECK1-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 633 // CHECK1-NEXT: store i32 [[TMP27]], i32* [[DOTOMP_IV16]], align 4 634 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND29:%.*]] 635 // CHECK1: omp.inner.for.cond29: 636 // CHECK1-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV16]], align 4 637 // CHECK1-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 638 // CHECK1-NEXT: [[ADD30:%.*]] = add i32 [[TMP29]], 1 639 // CHECK1-NEXT: [[CMP31:%.*]] = icmp ult i32 [[TMP28]], [[ADD30]] 640 // CHECK1-NEXT: br i1 [[CMP31]], label [[OMP_INNER_FOR_BODY32:%.*]], label [[OMP_INNER_FOR_END40:%.*]] 641 // CHECK1: omp.inner.for.body32: 642 // CHECK1-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 643 // CHECK1-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV16]], align 4 644 // CHECK1-NEXT: [[MUL33:%.*]] = mul i32 [[TMP31]], 1 645 // CHECK1-NEXT: [[ADD34:%.*]] = add i32 [[TMP30]], [[MUL33]] 646 // CHECK1-NEXT: store i32 [[ADD34]], i32* [[I28]], align 4 647 // CHECK1-NEXT: [[TMP32:%.*]] = load i32, i32* [[I28]], align 4 648 // CHECK1-NEXT: [[IDXPROM35:%.*]] = sext i32 [[TMP32]] to i64 649 // CHECK1-NEXT: [[ARRAYIDX36:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM35]] 650 // CHECK1-NEXT: store float 0.000000e+00, float* [[ARRAYIDX36]], align 4 651 // CHECK1-NEXT: call void @__captured_stmt.1(i32* [[I28]]) 652 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE37:%.*]] 653 // CHECK1: omp.body.continue37: 654 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC38:%.*]] 655 // CHECK1: omp.inner.for.inc38: 656 // CHECK1-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_IV16]], align 4 657 // CHECK1-NEXT: [[ADD39:%.*]] = add i32 [[TMP33]], 1 658 // CHECK1-NEXT: store i32 [[ADD39]], i32* [[DOTOMP_IV16]], align 4 659 // CHECK1-NEXT: call void @__kmpc_dispatch_fini_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 660 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND29]], !llvm.loop [[LOOP6:![0-9]+]] 661 // CHECK1: omp.inner.for.end40: 662 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 663 // CHECK1: omp.dispatch.inc: 664 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 665 // CHECK1: omp.dispatch.end: 666 // CHECK1-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 667 // CHECK1-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 668 // CHECK1-NEXT: br i1 [[TMP35]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 669 // CHECK1: .omp.final.then: 670 // CHECK1-NEXT: [[TMP36:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 671 // CHECK1-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 672 // CHECK1-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 673 // CHECK1-NEXT: [[SUB41:%.*]] = sub i32 [[TMP37]], [[TMP38]] 674 // CHECK1-NEXT: [[SUB42:%.*]] = sub i32 [[SUB41]], 1 675 // CHECK1-NEXT: [[ADD43:%.*]] = add i32 [[SUB42]], 1 676 // CHECK1-NEXT: [[DIV44:%.*]] = udiv i32 [[ADD43]], 1 677 // CHECK1-NEXT: [[MUL45:%.*]] = mul i32 [[DIV44]], 1 678 // CHECK1-NEXT: [[ADD46:%.*]] = add i32 [[TMP36]], [[MUL45]] 679 // CHECK1-NEXT: store i32 [[ADD46]], i32* [[I28]], align 4 680 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 681 // CHECK1: .omp.final.done: 682 // CHECK1-NEXT: br label [[OMP_PRECOND_END]] 683 // CHECK1: omp.precond.end: 684 // CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 685 // CHECK1-NEXT: ret void 686 // 687 // 688 // CHECK1-LABEL: define {{[^@]+}}@__captured_stmt 689 // CHECK1-SAME: (i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR3:[0-9]+]] { 690 // CHECK1-NEXT: entry: 691 // CHECK1-NEXT: [[I_ADDR:%.*]] = alloca i32*, align 8 692 // CHECK1-NEXT: store i32* [[I]], i32** [[I_ADDR]], align 8 693 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[I_ADDR]], align 8 694 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 695 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 696 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM]] 697 // CHECK1-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 698 // CHECK1-NEXT: ret void 699 // 700 // 701 // CHECK1-LABEL: define {{[^@]+}}@__captured_stmt.1 702 // CHECK1-SAME: (i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR3]] { 703 // CHECK1-NEXT: entry: 704 // CHECK1-NEXT: [[I_ADDR:%.*]] = alloca i32*, align 8 705 // CHECK1-NEXT: store i32* [[I]], i32** [[I_ADDR]], align 8 706 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[I_ADDR]], align 8 707 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 708 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 709 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM]] 710 // CHECK1-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 711 // CHECK1-NEXT: ret void 712 // 713 // 714 // CHECK2-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 715 // CHECK2-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { 716 // CHECK2-NEXT: entry: 717 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 718 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 719 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 720 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 721 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 722 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 723 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 724 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 725 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 726 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 727 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 728 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 729 // CHECK2-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 730 // CHECK2-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 731 // CHECK2-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 732 // CHECK2-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 733 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 734 // CHECK2-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 735 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 736 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 737 // CHECK2-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 66, i32 0, i32 4571423, i32 1, i32 1) 738 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 739 // CHECK2: omp.dispatch.cond: 740 // CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 741 // CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 742 // CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 743 // CHECK2: omp.dispatch.body: 744 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 745 // CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_IV]], align 4 746 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 747 // CHECK2: omp.inner.for.cond: 748 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 749 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 750 // CHECK2-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP3]], [[TMP4]] 751 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 752 // CHECK2: omp.inner.for.body: 753 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 754 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP5]], 7 755 // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 756 // CHECK2-NEXT: store i32 [[SUB]], i32* [[I]], align 4 757 // CHECK2-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 758 // CHECK2-NEXT: [[TMP6:%.*]] = load float*, float** [[B_ADDR]], align 8 759 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 760 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 761 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP6]], i64 [[IDXPROM]] 762 // CHECK2-NEXT: [[TMP8:%.*]] = load float, float* [[ARRAYIDX]], align 4 763 // CHECK2-NEXT: [[TMP9:%.*]] = load float*, float** [[C_ADDR]], align 8 764 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 765 // CHECK2-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP10]] to i64 766 // CHECK2-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP9]], i64 [[IDXPROM1]] 767 // CHECK2-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX2]], align 4 768 // CHECK2-NEXT: [[MUL3:%.*]] = fmul float [[TMP8]], [[TMP11]] 769 // CHECK2-NEXT: [[TMP12:%.*]] = load float*, float** [[D_ADDR]], align 8 770 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 771 // CHECK2-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP13]] to i64 772 // CHECK2-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM4]] 773 // CHECK2-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX5]], align 4 774 // CHECK2-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP14]] 775 // CHECK2-NEXT: [[TMP15:%.*]] = load float*, float** [[A_ADDR]], align 8 776 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 777 // CHECK2-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP16]] to i64 778 // CHECK2-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM7]] 779 // CHECK2-NEXT: store float [[MUL6]], float* [[ARRAYIDX8]], align 4 780 // CHECK2-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 781 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 782 // CHECK2: omp.body.continue: 783 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 784 // CHECK2: omp.inner.for.inc: 785 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 786 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP17]], 1 787 // CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 788 // CHECK2-NEXT: call void @__kmpc_dispatch_fini_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 789 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 790 // CHECK2: omp.inner.for.end: 791 // CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 792 // CHECK2: omp.dispatch.inc: 793 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND]] 794 // CHECK2: omp.dispatch.end: 795 // CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP0]]) 796 // CHECK2-NEXT: ret void 797 // 798 // 799 // CHECK2-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_ 800 // CHECK2-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 801 // CHECK2-NEXT: entry: 802 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 803 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 804 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 805 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 806 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 807 // CHECK2-NEXT: [[TMP:%.*]] = alloca i64, align 8 808 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 809 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 810 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 811 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 812 // CHECK2-NEXT: [[I:%.*]] = alloca i64, align 8 813 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 814 // CHECK2-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 815 // CHECK2-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 816 // CHECK2-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 817 // CHECK2-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 818 // CHECK2-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 819 // CHECK2-NEXT: store i64 16908287, i64* [[DOTOMP_UB]], align 8 820 // CHECK2-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 821 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 822 // CHECK2-NEXT: call void @__kmpc_dispatch_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1073741891, i64 0, i64 16908287, i64 1, i64 1) 823 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 824 // CHECK2: omp.dispatch.cond: 825 // CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 826 // CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 827 // CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 828 // CHECK2: omp.dispatch.body: 829 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 830 // CHECK2-NEXT: store i64 [[TMP2]], i64* [[DOTOMP_IV]], align 8 831 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 832 // CHECK2: omp.inner.for.cond: 833 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 834 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 835 // CHECK2-NEXT: [[ADD:%.*]] = add i64 [[TMP4]], 1 836 // CHECK2-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP3]], [[ADD]] 837 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 838 // CHECK2: omp.inner.for.body: 839 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 840 // CHECK2-NEXT: [[MUL:%.*]] = mul i64 [[TMP5]], 127 841 // CHECK2-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]] 842 // CHECK2-NEXT: store i64 [[ADD1]], i64* [[I]], align 8 843 // CHECK2-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 844 // CHECK2-NEXT: [[TMP6:%.*]] = load float*, float** [[B_ADDR]], align 8 845 // CHECK2-NEXT: [[TMP7:%.*]] = load i64, i64* [[I]], align 8 846 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP6]], i64 [[TMP7]] 847 // CHECK2-NEXT: [[TMP8:%.*]] = load float, float* [[ARRAYIDX]], align 4 848 // CHECK2-NEXT: [[TMP9:%.*]] = load float*, float** [[C_ADDR]], align 8 849 // CHECK2-NEXT: [[TMP10:%.*]] = load i64, i64* [[I]], align 8 850 // CHECK2-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP9]], i64 [[TMP10]] 851 // CHECK2-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX2]], align 4 852 // CHECK2-NEXT: [[MUL3:%.*]] = fmul float [[TMP8]], [[TMP11]] 853 // CHECK2-NEXT: [[TMP12:%.*]] = load float*, float** [[D_ADDR]], align 8 854 // CHECK2-NEXT: [[TMP13:%.*]] = load i64, i64* [[I]], align 8 855 // CHECK2-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[TMP13]] 856 // CHECK2-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX4]], align 4 857 // CHECK2-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP14]] 858 // CHECK2-NEXT: [[TMP15:%.*]] = load float*, float** [[A_ADDR]], align 8 859 // CHECK2-NEXT: [[TMP16:%.*]] = load i64, i64* [[I]], align 8 860 // CHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[TMP16]] 861 // CHECK2-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4 862 // CHECK2-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 863 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 864 // CHECK2: omp.body.continue: 865 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 866 // CHECK2: omp.inner.for.inc: 867 // CHECK2-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 868 // CHECK2-NEXT: [[ADD7:%.*]] = add i64 [[TMP17]], 1 869 // CHECK2-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 870 // CHECK2-NEXT: call void @__kmpc_dispatch_fini_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 871 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 872 // CHECK2: omp.inner.for.end: 873 // CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 874 // CHECK2: omp.dispatch.inc: 875 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND]] 876 // CHECK2: omp.dispatch.end: 877 // CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 878 // CHECK2-NEXT: ret void 879 // 880 // 881 // CHECK2-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_ 882 // CHECK2-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 883 // CHECK2-NEXT: entry: 884 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 885 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 886 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 887 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 888 // CHECK2-NEXT: [[X:%.*]] = alloca i32, align 4 889 // CHECK2-NEXT: [[Y:%.*]] = alloca i32, align 4 890 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 891 // CHECK2-NEXT: [[TMP:%.*]] = alloca i8, align 1 892 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 893 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 894 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8 895 // CHECK2-NEXT: [[I:%.*]] = alloca i8, align 1 896 // CHECK2-NEXT: [[X6:%.*]] = alloca i32, align 4 897 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 898 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 899 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 900 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 901 // CHECK2-NEXT: [[I8:%.*]] = alloca i8, align 1 902 // CHECK2-NEXT: [[X9:%.*]] = alloca i32, align 4 903 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 904 // CHECK2-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 905 // CHECK2-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 906 // CHECK2-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 907 // CHECK2-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 908 // CHECK2-NEXT: store i32 0, i32* [[X]], align 4 909 // CHECK2-NEXT: store i32 0, i32* [[Y]], align 4 910 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[Y]], align 4 911 // CHECK2-NEXT: [[CONV:%.*]] = trunc i32 [[TMP1]] to i8 912 // CHECK2-NEXT: store i8 [[CONV]], i8* [[DOTCAPTURE_EXPR_]], align 1 913 // CHECK2-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 914 // CHECK2-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 915 // CHECK2-NEXT: [[SUB:%.*]] = sub i32 57, [[CONV3]] 916 // CHECK2-NEXT: [[ADD:%.*]] = add i32 [[SUB]], 1 917 // CHECK2-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 918 // CHECK2-NEXT: [[CONV4:%.*]] = zext i32 [[DIV]] to i64 919 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV4]], 11 920 // CHECK2-NEXT: [[SUB5:%.*]] = sub nsw i64 [[MUL]], 1 921 // CHECK2-NEXT: store i64 [[SUB5]], i64* [[DOTCAPTURE_EXPR_2]], align 8 922 // CHECK2-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 923 // CHECK2-NEXT: store i8 [[TMP3]], i8* [[I]], align 1 924 // CHECK2-NEXT: store i32 11, i32* [[X6]], align 4 925 // CHECK2-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 926 // CHECK2-NEXT: [[CONV7:%.*]] = sext i8 [[TMP4]] to i32 927 // CHECK2-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV7]], 57 928 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 929 // CHECK2: omp.precond.then: 930 // CHECK2-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 931 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 932 // CHECK2-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_UB]], align 8 933 // CHECK2-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 934 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 935 // CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 936 // CHECK2-NEXT: call void @__kmpc_dispatch_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1073741894, i64 0, i64 [[TMP6]], i64 1, i64 1) 937 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 938 // CHECK2: omp.dispatch.cond: 939 // CHECK2-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_dispatch_next_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 940 // CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0 941 // CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 942 // CHECK2: omp.dispatch.body: 943 // CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 944 // CHECK2-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 945 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 946 // CHECK2: omp.inner.for.cond: 947 // CHECK2-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 948 // CHECK2-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 949 // CHECK2-NEXT: [[CMP10:%.*]] = icmp sle i64 [[TMP9]], [[TMP10]] 950 // CHECK2-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 951 // CHECK2: omp.inner.for.body: 952 // CHECK2-NEXT: [[TMP11:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 953 // CHECK2-NEXT: [[CONV11:%.*]] = sext i8 [[TMP11]] to i64 954 // CHECK2-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 955 // CHECK2-NEXT: [[DIV12:%.*]] = sdiv i64 [[TMP12]], 11 956 // CHECK2-NEXT: [[MUL13:%.*]] = mul nsw i64 [[DIV12]], 1 957 // CHECK2-NEXT: [[ADD14:%.*]] = add nsw i64 [[CONV11]], [[MUL13]] 958 // CHECK2-NEXT: [[CONV15:%.*]] = trunc i64 [[ADD14]] to i8 959 // CHECK2-NEXT: store i8 [[CONV15]], i8* [[I8]], align 1 960 // CHECK2-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 961 // CHECK2-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 962 // CHECK2-NEXT: [[DIV16:%.*]] = sdiv i64 [[TMP14]], 11 963 // CHECK2-NEXT: [[MUL17:%.*]] = mul nsw i64 [[DIV16]], 11 964 // CHECK2-NEXT: [[SUB18:%.*]] = sub nsw i64 [[TMP13]], [[MUL17]] 965 // CHECK2-NEXT: [[MUL19:%.*]] = mul nsw i64 [[SUB18]], 1 966 // CHECK2-NEXT: [[SUB20:%.*]] = sub nsw i64 11, [[MUL19]] 967 // CHECK2-NEXT: [[CONV21:%.*]] = trunc i64 [[SUB20]] to i32 968 // CHECK2-NEXT: store i32 [[CONV21]], i32* [[X9]], align 4 969 // CHECK2-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 970 // CHECK2-NEXT: [[TMP15:%.*]] = load float*, float** [[B_ADDR]], align 8 971 // CHECK2-NEXT: [[TMP16:%.*]] = load i8, i8* [[I8]], align 1 972 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP16]] to i64 973 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM]] 974 // CHECK2-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4 975 // CHECK2-NEXT: [[TMP18:%.*]] = load float*, float** [[C_ADDR]], align 8 976 // CHECK2-NEXT: [[TMP19:%.*]] = load i8, i8* [[I8]], align 1 977 // CHECK2-NEXT: [[IDXPROM22:%.*]] = sext i8 [[TMP19]] to i64 978 // CHECK2-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM22]] 979 // CHECK2-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX23]], align 4 980 // CHECK2-NEXT: [[MUL24:%.*]] = fmul float [[TMP17]], [[TMP20]] 981 // CHECK2-NEXT: [[TMP21:%.*]] = load float*, float** [[D_ADDR]], align 8 982 // CHECK2-NEXT: [[TMP22:%.*]] = load i8, i8* [[I8]], align 1 983 // CHECK2-NEXT: [[IDXPROM25:%.*]] = sext i8 [[TMP22]] to i64 984 // CHECK2-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM25]] 985 // CHECK2-NEXT: [[TMP23:%.*]] = load float, float* [[ARRAYIDX26]], align 4 986 // CHECK2-NEXT: [[MUL27:%.*]] = fmul float [[MUL24]], [[TMP23]] 987 // CHECK2-NEXT: [[TMP24:%.*]] = load float*, float** [[A_ADDR]], align 8 988 // CHECK2-NEXT: [[TMP25:%.*]] = load i8, i8* [[I8]], align 1 989 // CHECK2-NEXT: [[IDXPROM28:%.*]] = sext i8 [[TMP25]] to i64 990 // CHECK2-NEXT: [[ARRAYIDX29:%.*]] = getelementptr inbounds float, float* [[TMP24]], i64 [[IDXPROM28]] 991 // CHECK2-NEXT: store float [[MUL27]], float* [[ARRAYIDX29]], align 4 992 // CHECK2-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 993 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 994 // CHECK2: omp.body.continue: 995 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 996 // CHECK2: omp.inner.for.inc: 997 // CHECK2-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 998 // CHECK2-NEXT: [[ADD30:%.*]] = add nsw i64 [[TMP26]], 1 999 // CHECK2-NEXT: store i64 [[ADD30]], i64* [[DOTOMP_IV]], align 8 1000 // CHECK2-NEXT: call void @__kmpc_dispatch_fini_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 1001 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 1002 // CHECK2: omp.inner.for.end: 1003 // CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1004 // CHECK2: omp.dispatch.inc: 1005 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND]] 1006 // CHECK2: omp.dispatch.end: 1007 // CHECK2-NEXT: br label [[OMP_PRECOND_END]] 1008 // CHECK2: omp.precond.end: 1009 // CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 1010 // CHECK2-NEXT: ret void 1011 // 1012 // 1013 // CHECK2-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_ 1014 // CHECK2-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 1015 // CHECK2-NEXT: entry: 1016 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 1017 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 1018 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 1019 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 1020 // CHECK2-NEXT: [[X:%.*]] = alloca i32, align 4 1021 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1022 // CHECK2-NEXT: [[TMP:%.*]] = alloca i8, align 1 1023 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1024 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1025 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1026 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1027 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1028 // CHECK2-NEXT: [[I:%.*]] = alloca i8, align 1 1029 // CHECK2-NEXT: [[X2:%.*]] = alloca i32, align 4 1030 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1031 // CHECK2-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 1032 // CHECK2-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 1033 // CHECK2-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 1034 // CHECK2-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 1035 // CHECK2-NEXT: store i32 0, i32* [[X]], align 4 1036 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1037 // CHECK2-NEXT: store i32 199, i32* [[DOTOMP_UB]], align 4 1038 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1039 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1040 // CHECK2-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1073741893, i32 0, i32 199, i32 1, i32 1) 1041 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 1042 // CHECK2: omp.dispatch.cond: 1043 // CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 1044 // CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 1045 // CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 1046 // CHECK2: omp.dispatch.body: 1047 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1048 // CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_IV]], align 4 1049 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1050 // CHECK2: omp.inner.for.cond: 1051 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1052 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1053 // CHECK2-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP3]], [[TMP4]] 1054 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1055 // CHECK2: omp.inner.for.body: 1056 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1057 // CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 20 1058 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 1059 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 48, [[MUL]] 1060 // CHECK2-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i8 1061 // CHECK2-NEXT: store i8 [[CONV]], i8* [[I]], align 1 1062 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1063 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1064 // CHECK2-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP7]], 20 1065 // CHECK2-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 20 1066 // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP6]], [[MUL4]] 1067 // CHECK2-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 1068 // CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 -10, [[MUL5]] 1069 // CHECK2-NEXT: store i32 [[ADD6]], i32* [[X2]], align 4 1070 // CHECK2-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 1071 // CHECK2-NEXT: [[TMP8:%.*]] = load float*, float** [[B_ADDR]], align 8 1072 // CHECK2-NEXT: [[TMP9:%.*]] = load i8, i8* [[I]], align 1 1073 // CHECK2-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP9]] to i64 1074 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[IDXPROM]] 1075 // CHECK2-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX]], align 4 1076 // CHECK2-NEXT: [[TMP11:%.*]] = load float*, float** [[C_ADDR]], align 8 1077 // CHECK2-NEXT: [[TMP12:%.*]] = load i8, i8* [[I]], align 1 1078 // CHECK2-NEXT: [[IDXPROM7:%.*]] = zext i8 [[TMP12]] to i64 1079 // CHECK2-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[IDXPROM7]] 1080 // CHECK2-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX8]], align 4 1081 // CHECK2-NEXT: [[MUL9:%.*]] = fmul float [[TMP10]], [[TMP13]] 1082 // CHECK2-NEXT: [[TMP14:%.*]] = load float*, float** [[D_ADDR]], align 8 1083 // CHECK2-NEXT: [[TMP15:%.*]] = load i8, i8* [[I]], align 1 1084 // CHECK2-NEXT: [[IDXPROM10:%.*]] = zext i8 [[TMP15]] to i64 1085 // CHECK2-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM10]] 1086 // CHECK2-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX11]], align 4 1087 // CHECK2-NEXT: [[MUL12:%.*]] = fmul float [[MUL9]], [[TMP16]] 1088 // CHECK2-NEXT: [[TMP17:%.*]] = load float*, float** [[A_ADDR]], align 8 1089 // CHECK2-NEXT: [[TMP18:%.*]] = load i8, i8* [[I]], align 1 1090 // CHECK2-NEXT: [[IDXPROM13:%.*]] = zext i8 [[TMP18]] to i64 1091 // CHECK2-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM13]] 1092 // CHECK2-NEXT: store float [[MUL12]], float* [[ARRAYIDX14]], align 4 1093 // CHECK2-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 1094 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1095 // CHECK2: omp.body.continue: 1096 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1097 // CHECK2: omp.inner.for.inc: 1098 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1099 // CHECK2-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP19]], 1 1100 // CHECK2-NEXT: store i32 [[ADD15]], i32* [[DOTOMP_IV]], align 4 1101 // CHECK2-NEXT: call void @__kmpc_dispatch_fini_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 1102 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 1103 // CHECK2: omp.inner.for.end: 1104 // CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1105 // CHECK2: omp.dispatch.inc: 1106 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND]] 1107 // CHECK2: omp.dispatch.end: 1108 // CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 1109 // CHECK2-NEXT: ret void 1110 // 1111 // 1112 // CHECK2-LABEL: define {{[^@]+}}@_Z8foo_simdii 1113 // CHECK2-SAME: (i32 [[LOW:%.*]], i32 [[UP:%.*]]) #[[ATTR0]] { 1114 // CHECK2-NEXT: entry: 1115 // CHECK2-NEXT: [[LOW_ADDR:%.*]] = alloca i32, align 4 1116 // CHECK2-NEXT: [[UP_ADDR:%.*]] = alloca i32, align 4 1117 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 1118 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1119 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 1120 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 1121 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 1122 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1123 // CHECK2-NEXT: [[I5:%.*]] = alloca i32, align 4 1124 // CHECK2-NEXT: [[DOTOMP_IV16:%.*]] = alloca i32, align 4 1125 // CHECK2-NEXT: [[_TMP17:%.*]] = alloca i32, align 4 1126 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_18:%.*]] = alloca i32, align 4 1127 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_19:%.*]] = alloca i32, align 4 1128 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_20:%.*]] = alloca i32, align 4 1129 // CHECK2-NEXT: [[I26:%.*]] = alloca i32, align 4 1130 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1131 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1132 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1133 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1134 // CHECK2-NEXT: [[I28:%.*]] = alloca i32, align 4 1135 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1136 // CHECK2-NEXT: store i32 [[LOW]], i32* [[LOW_ADDR]], align 4 1137 // CHECK2-NEXT: store i32 [[UP]], i32* [[UP_ADDR]], align 4 1138 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[LOW_ADDR]], align 4 1139 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 1140 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[UP_ADDR]], align 4 1141 // CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 1142 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 1143 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1144 // CHECK2-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] 1145 // CHECK2-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1 1146 // CHECK2-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1 1147 // CHECK2-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 1148 // CHECK2-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1 1149 // CHECK2-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4 1150 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1151 // CHECK2-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 1152 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1153 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 1154 // CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] 1155 // CHECK2-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]] 1156 // CHECK2: simd.if.then: 1157 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IV]], align 4 1158 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1159 // CHECK2: omp.inner.for.cond: 1160 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 1161 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !2 1162 // CHECK2-NEXT: [[ADD6:%.*]] = add i32 [[TMP9]], 1 1163 // CHECK2-NEXT: [[CMP7:%.*]] = icmp ult i32 [[TMP8]], [[ADD6]] 1164 // CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1165 // CHECK2: omp.inner.for.body: 1166 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !2 1167 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 1168 // CHECK2-NEXT: [[MUL:%.*]] = mul i32 [[TMP11]], 1 1169 // CHECK2-NEXT: [[ADD8:%.*]] = add i32 [[TMP10]], [[MUL]] 1170 // CHECK2-NEXT: store i32 [[ADD8]], i32* [[I5]], align 4, !llvm.access.group !2 1171 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[I5]], align 4, !llvm.access.group !2 1172 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64 1173 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM]] 1174 // CHECK2-NEXT: store float 0.000000e+00, float* [[ARRAYIDX]], align 4, !llvm.access.group !2 1175 // CHECK2-NEXT: call void @__captured_stmt(i32* [[I5]]), !llvm.access.group !2 1176 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1177 // CHECK2: omp.body.continue: 1178 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1179 // CHECK2: omp.inner.for.inc: 1180 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 1181 // CHECK2-NEXT: [[ADD9:%.*]] = add i32 [[TMP13]], 1 1182 // CHECK2-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 1183 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 1184 // CHECK2: omp.inner.for.end: 1185 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1186 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 1187 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1188 // CHECK2-NEXT: [[SUB10:%.*]] = sub i32 [[TMP15]], [[TMP16]] 1189 // CHECK2-NEXT: [[SUB11:%.*]] = sub i32 [[SUB10]], 1 1190 // CHECK2-NEXT: [[ADD12:%.*]] = add i32 [[SUB11]], 1 1191 // CHECK2-NEXT: [[DIV13:%.*]] = udiv i32 [[ADD12]], 1 1192 // CHECK2-NEXT: [[MUL14:%.*]] = mul i32 [[DIV13]], 1 1193 // CHECK2-NEXT: [[ADD15:%.*]] = add i32 [[TMP14]], [[MUL14]] 1194 // CHECK2-NEXT: store i32 [[ADD15]], i32* [[I5]], align 4 1195 // CHECK2-NEXT: br label [[SIMD_IF_END]] 1196 // CHECK2: simd.if.end: 1197 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[LOW_ADDR]], align 4 1198 // CHECK2-NEXT: store i32 [[TMP17]], i32* [[DOTCAPTURE_EXPR_18]], align 4 1199 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[UP_ADDR]], align 4 1200 // CHECK2-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_19]], align 4 1201 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 1202 // CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 1203 // CHECK2-NEXT: [[SUB21:%.*]] = sub i32 [[TMP19]], [[TMP20]] 1204 // CHECK2-NEXT: [[SUB22:%.*]] = sub i32 [[SUB21]], 1 1205 // CHECK2-NEXT: [[ADD23:%.*]] = add i32 [[SUB22]], 1 1206 // CHECK2-NEXT: [[DIV24:%.*]] = udiv i32 [[ADD23]], 1 1207 // CHECK2-NEXT: [[SUB25:%.*]] = sub i32 [[DIV24]], 1 1208 // CHECK2-NEXT: store i32 [[SUB25]], i32* [[DOTCAPTURE_EXPR_20]], align 4 1209 // CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 1210 // CHECK2-NEXT: store i32 [[TMP21]], i32* [[I26]], align 4 1211 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 1212 // CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 1213 // CHECK2-NEXT: [[CMP27:%.*]] = icmp slt i32 [[TMP22]], [[TMP23]] 1214 // CHECK2-NEXT: br i1 [[CMP27]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 1215 // CHECK2: omp.precond.then: 1216 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1217 // CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_20]], align 4 1218 // CHECK2-NEXT: store i32 [[TMP24]], i32* [[DOTOMP_UB]], align 4 1219 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1220 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1221 // CHECK2-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_20]], align 4 1222 // CHECK2-NEXT: call void @__kmpc_dispatch_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 66, i32 0, i32 [[TMP25]], i32 1, i32 1) 1223 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 1224 // CHECK2: omp.dispatch.cond: 1225 // CHECK2-NEXT: [[TMP26:%.*]] = call i32 @__kmpc_dispatch_next_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 1226 // CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP26]], 0 1227 // CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 1228 // CHECK2: omp.dispatch.body: 1229 // CHECK2-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1230 // CHECK2-NEXT: store i32 [[TMP27]], i32* [[DOTOMP_IV16]], align 4 1231 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND29:%.*]] 1232 // CHECK2: omp.inner.for.cond29: 1233 // CHECK2-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV16]], align 4 1234 // CHECK2-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1235 // CHECK2-NEXT: [[ADD30:%.*]] = add i32 [[TMP29]], 1 1236 // CHECK2-NEXT: [[CMP31:%.*]] = icmp ult i32 [[TMP28]], [[ADD30]] 1237 // CHECK2-NEXT: br i1 [[CMP31]], label [[OMP_INNER_FOR_BODY32:%.*]], label [[OMP_INNER_FOR_END40:%.*]] 1238 // CHECK2: omp.inner.for.body32: 1239 // CHECK2-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 1240 // CHECK2-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV16]], align 4 1241 // CHECK2-NEXT: [[MUL33:%.*]] = mul i32 [[TMP31]], 1 1242 // CHECK2-NEXT: [[ADD34:%.*]] = add i32 [[TMP30]], [[MUL33]] 1243 // CHECK2-NEXT: store i32 [[ADD34]], i32* [[I28]], align 4 1244 // CHECK2-NEXT: [[TMP32:%.*]] = load i32, i32* [[I28]], align 4 1245 // CHECK2-NEXT: [[IDXPROM35:%.*]] = sext i32 [[TMP32]] to i64 1246 // CHECK2-NEXT: [[ARRAYIDX36:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM35]] 1247 // CHECK2-NEXT: store float 0.000000e+00, float* [[ARRAYIDX36]], align 4 1248 // CHECK2-NEXT: call void @__captured_stmt.1(i32* [[I28]]) 1249 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE37:%.*]] 1250 // CHECK2: omp.body.continue37: 1251 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC38:%.*]] 1252 // CHECK2: omp.inner.for.inc38: 1253 // CHECK2-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_IV16]], align 4 1254 // CHECK2-NEXT: [[ADD39:%.*]] = add i32 [[TMP33]], 1 1255 // CHECK2-NEXT: store i32 [[ADD39]], i32* [[DOTOMP_IV16]], align 4 1256 // CHECK2-NEXT: call void @__kmpc_dispatch_fini_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 1257 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND29]], !llvm.loop [[LOOP6:![0-9]+]] 1258 // CHECK2: omp.inner.for.end40: 1259 // CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1260 // CHECK2: omp.dispatch.inc: 1261 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND]] 1262 // CHECK2: omp.dispatch.end: 1263 // CHECK2-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 1264 // CHECK2-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 1265 // CHECK2-NEXT: br i1 [[TMP35]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1266 // CHECK2: .omp.final.then: 1267 // CHECK2-NEXT: [[TMP36:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 1268 // CHECK2-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 1269 // CHECK2-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 1270 // CHECK2-NEXT: [[SUB41:%.*]] = sub i32 [[TMP37]], [[TMP38]] 1271 // CHECK2-NEXT: [[SUB42:%.*]] = sub i32 [[SUB41]], 1 1272 // CHECK2-NEXT: [[ADD43:%.*]] = add i32 [[SUB42]], 1 1273 // CHECK2-NEXT: [[DIV44:%.*]] = udiv i32 [[ADD43]], 1 1274 // CHECK2-NEXT: [[MUL45:%.*]] = mul i32 [[DIV44]], 1 1275 // CHECK2-NEXT: [[ADD46:%.*]] = add i32 [[TMP36]], [[MUL45]] 1276 // CHECK2-NEXT: store i32 [[ADD46]], i32* [[I28]], align 4 1277 // CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]] 1278 // CHECK2: .omp.final.done: 1279 // CHECK2-NEXT: br label [[OMP_PRECOND_END]] 1280 // CHECK2: omp.precond.end: 1281 // CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 1282 // CHECK2-NEXT: ret void 1283 // 1284 // 1285 // CHECK2-LABEL: define {{[^@]+}}@__captured_stmt 1286 // CHECK2-SAME: (i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR3:[0-9]+]] { 1287 // CHECK2-NEXT: entry: 1288 // CHECK2-NEXT: [[I_ADDR:%.*]] = alloca i32*, align 8 1289 // CHECK2-NEXT: store i32* [[I]], i32** [[I_ADDR]], align 8 1290 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[I_ADDR]], align 8 1291 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 1292 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 1293 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM]] 1294 // CHECK2-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 1295 // CHECK2-NEXT: ret void 1296 // 1297 // 1298 // CHECK2-LABEL: define {{[^@]+}}@__captured_stmt.1 1299 // CHECK2-SAME: (i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR3]] { 1300 // CHECK2-NEXT: entry: 1301 // CHECK2-NEXT: [[I_ADDR:%.*]] = alloca i32*, align 8 1302 // CHECK2-NEXT: store i32* [[I]], i32** [[I_ADDR]], align 8 1303 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[I_ADDR]], align 8 1304 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 1305 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 1306 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM]] 1307 // CHECK2-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 1308 // CHECK2-NEXT: ret void 1309 // 1310 // 1311 // CHECK3-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 1312 // CHECK3-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { 1313 // CHECK3-NEXT: entry: 1314 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 1315 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 1316 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 1317 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 1318 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1319 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1320 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1321 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1322 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1323 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1324 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1325 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 1326 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 1327 // CHECK3-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 1328 // CHECK3-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 1329 // CHECK3-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 1330 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1331 // CHECK3-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 1332 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1333 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1334 // CHECK3-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 66, i32 0, i32 4571423, i32 1, i32 1) 1335 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 1336 // CHECK3: omp.dispatch.cond: 1337 // CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 1338 // CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 1339 // CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 1340 // CHECK3: omp.dispatch.body: 1341 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1342 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_IV]], align 4 1343 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1344 // CHECK3: omp.inner.for.cond: 1345 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1346 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1347 // CHECK3-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP3]], [[TMP4]] 1348 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1349 // CHECK3: omp.inner.for.body: 1350 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1351 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP5]], 7 1352 // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 1353 // CHECK3-NEXT: store i32 [[SUB]], i32* [[I]], align 4 1354 // CHECK3-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 1355 // CHECK3-NEXT: [[TMP6:%.*]] = load float*, float** [[B_ADDR]], align 8 1356 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 1357 // CHECK3-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 1358 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP6]], i64 [[IDXPROM]] 1359 // CHECK3-NEXT: [[TMP8:%.*]] = load float, float* [[ARRAYIDX]], align 4 1360 // CHECK3-NEXT: [[TMP9:%.*]] = load float*, float** [[C_ADDR]], align 8 1361 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 1362 // CHECK3-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP10]] to i64 1363 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP9]], i64 [[IDXPROM1]] 1364 // CHECK3-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX2]], align 4 1365 // CHECK3-NEXT: [[MUL3:%.*]] = fmul float [[TMP8]], [[TMP11]] 1366 // CHECK3-NEXT: [[TMP12:%.*]] = load float*, float** [[D_ADDR]], align 8 1367 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 1368 // CHECK3-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP13]] to i64 1369 // CHECK3-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM4]] 1370 // CHECK3-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX5]], align 4 1371 // CHECK3-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP14]] 1372 // CHECK3-NEXT: [[TMP15:%.*]] = load float*, float** [[A_ADDR]], align 8 1373 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 1374 // CHECK3-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP16]] to i64 1375 // CHECK3-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM7]] 1376 // CHECK3-NEXT: store float [[MUL6]], float* [[ARRAYIDX8]], align 4 1377 // CHECK3-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 1378 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1379 // CHECK3: omp.body.continue: 1380 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1381 // CHECK3: omp.inner.for.inc: 1382 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1383 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP17]], 1 1384 // CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 1385 // CHECK3-NEXT: call void @__kmpc_dispatch_fini_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 1386 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 1387 // CHECK3: omp.inner.for.end: 1388 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1389 // CHECK3: omp.dispatch.inc: 1390 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]] 1391 // CHECK3: omp.dispatch.end: 1392 // CHECK3-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP0]]) 1393 // CHECK3-NEXT: ret void 1394 // 1395 // 1396 // CHECK3-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_ 1397 // CHECK3-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 1398 // CHECK3-NEXT: entry: 1399 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 1400 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 1401 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 1402 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 1403 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 1404 // CHECK3-NEXT: [[TMP:%.*]] = alloca i64, align 8 1405 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 1406 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 1407 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 1408 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1409 // CHECK3-NEXT: [[I:%.*]] = alloca i64, align 8 1410 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1411 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 1412 // CHECK3-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 1413 // CHECK3-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 1414 // CHECK3-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 1415 // CHECK3-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 1416 // CHECK3-NEXT: store i64 16908287, i64* [[DOTOMP_UB]], align 8 1417 // CHECK3-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 1418 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1419 // CHECK3-NEXT: call void @__kmpc_dispatch_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 67, i64 0, i64 16908287, i64 1, i64 1) 1420 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 1421 // CHECK3: omp.dispatch.cond: 1422 // CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 1423 // CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 1424 // CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 1425 // CHECK3: omp.dispatch.body: 1426 // CHECK3-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 1427 // CHECK3-NEXT: store i64 [[TMP2]], i64* [[DOTOMP_IV]], align 8 1428 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1429 // CHECK3: omp.inner.for.cond: 1430 // CHECK3-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1431 // CHECK3-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1432 // CHECK3-NEXT: [[ADD:%.*]] = add i64 [[TMP4]], 1 1433 // CHECK3-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP3]], [[ADD]] 1434 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1435 // CHECK3: omp.inner.for.body: 1436 // CHECK3-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1437 // CHECK3-NEXT: [[MUL:%.*]] = mul i64 [[TMP5]], 127 1438 // CHECK3-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]] 1439 // CHECK3-NEXT: store i64 [[ADD1]], i64* [[I]], align 8 1440 // CHECK3-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 1441 // CHECK3-NEXT: [[TMP6:%.*]] = load float*, float** [[B_ADDR]], align 8 1442 // CHECK3-NEXT: [[TMP7:%.*]] = load i64, i64* [[I]], align 8 1443 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP6]], i64 [[TMP7]] 1444 // CHECK3-NEXT: [[TMP8:%.*]] = load float, float* [[ARRAYIDX]], align 4 1445 // CHECK3-NEXT: [[TMP9:%.*]] = load float*, float** [[C_ADDR]], align 8 1446 // CHECK3-NEXT: [[TMP10:%.*]] = load i64, i64* [[I]], align 8 1447 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP9]], i64 [[TMP10]] 1448 // CHECK3-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX2]], align 4 1449 // CHECK3-NEXT: [[MUL3:%.*]] = fmul float [[TMP8]], [[TMP11]] 1450 // CHECK3-NEXT: [[TMP12:%.*]] = load float*, float** [[D_ADDR]], align 8 1451 // CHECK3-NEXT: [[TMP13:%.*]] = load i64, i64* [[I]], align 8 1452 // CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[TMP13]] 1453 // CHECK3-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX4]], align 4 1454 // CHECK3-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP14]] 1455 // CHECK3-NEXT: [[TMP15:%.*]] = load float*, float** [[A_ADDR]], align 8 1456 // CHECK3-NEXT: [[TMP16:%.*]] = load i64, i64* [[I]], align 8 1457 // CHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[TMP16]] 1458 // CHECK3-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4 1459 // CHECK3-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 1460 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1461 // CHECK3: omp.body.continue: 1462 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1463 // CHECK3: omp.inner.for.inc: 1464 // CHECK3-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1465 // CHECK3-NEXT: [[ADD7:%.*]] = add i64 [[TMP17]], 1 1466 // CHECK3-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 1467 // CHECK3-NEXT: call void @__kmpc_dispatch_fini_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 1468 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 1469 // CHECK3: omp.inner.for.end: 1470 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1471 // CHECK3: omp.dispatch.inc: 1472 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]] 1473 // CHECK3: omp.dispatch.end: 1474 // CHECK3-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 1475 // CHECK3-NEXT: ret void 1476 // 1477 // 1478 // CHECK3-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_ 1479 // CHECK3-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 1480 // CHECK3-NEXT: entry: 1481 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 1482 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 1483 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 1484 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 1485 // CHECK3-NEXT: [[X:%.*]] = alloca i32, align 4 1486 // CHECK3-NEXT: [[Y:%.*]] = alloca i32, align 4 1487 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 1488 // CHECK3-NEXT: [[TMP:%.*]] = alloca i8, align 1 1489 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1490 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 1491 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8 1492 // CHECK3-NEXT: [[I:%.*]] = alloca i8, align 1 1493 // CHECK3-NEXT: [[X6:%.*]] = alloca i32, align 4 1494 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 1495 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 1496 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 1497 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1498 // CHECK3-NEXT: [[I8:%.*]] = alloca i8, align 1 1499 // CHECK3-NEXT: [[X9:%.*]] = alloca i32, align 4 1500 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1501 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 1502 // CHECK3-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 1503 // CHECK3-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 1504 // CHECK3-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 1505 // CHECK3-NEXT: store i32 0, i32* [[X]], align 4 1506 // CHECK3-NEXT: store i32 0, i32* [[Y]], align 4 1507 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[Y]], align 4 1508 // CHECK3-NEXT: [[CONV:%.*]] = trunc i32 [[TMP1]] to i8 1509 // CHECK3-NEXT: store i8 [[CONV]], i8* [[DOTCAPTURE_EXPR_]], align 1 1510 // CHECK3-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 1511 // CHECK3-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 1512 // CHECK3-NEXT: [[SUB:%.*]] = sub i32 57, [[CONV3]] 1513 // CHECK3-NEXT: [[ADD:%.*]] = add i32 [[SUB]], 1 1514 // CHECK3-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 1515 // CHECK3-NEXT: [[CONV4:%.*]] = zext i32 [[DIV]] to i64 1516 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV4]], 11 1517 // CHECK3-NEXT: [[SUB5:%.*]] = sub nsw i64 [[MUL]], 1 1518 // CHECK3-NEXT: store i64 [[SUB5]], i64* [[DOTCAPTURE_EXPR_2]], align 8 1519 // CHECK3-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 1520 // CHECK3-NEXT: store i8 [[TMP3]], i8* [[I]], align 1 1521 // CHECK3-NEXT: store i32 11, i32* [[X6]], align 4 1522 // CHECK3-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 1523 // CHECK3-NEXT: [[CONV7:%.*]] = sext i8 [[TMP4]] to i32 1524 // CHECK3-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV7]], 57 1525 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 1526 // CHECK3: omp.precond.then: 1527 // CHECK3-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 1528 // CHECK3-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 1529 // CHECK3-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_UB]], align 8 1530 // CHECK3-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 1531 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1532 // CHECK3-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 1533 // CHECK3-NEXT: call void @__kmpc_dispatch_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 70, i64 0, i64 [[TMP6]], i64 1, i64 1) 1534 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 1535 // CHECK3: omp.dispatch.cond: 1536 // CHECK3-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_dispatch_next_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 1537 // CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0 1538 // CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 1539 // CHECK3: omp.dispatch.body: 1540 // CHECK3-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 1541 // CHECK3-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 1542 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1543 // CHECK3: omp.inner.for.cond: 1544 // CHECK3-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1545 // CHECK3-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1546 // CHECK3-NEXT: [[CMP10:%.*]] = icmp sle i64 [[TMP9]], [[TMP10]] 1547 // CHECK3-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1548 // CHECK3: omp.inner.for.body: 1549 // CHECK3-NEXT: [[TMP11:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 1550 // CHECK3-NEXT: [[CONV11:%.*]] = sext i8 [[TMP11]] to i64 1551 // CHECK3-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1552 // CHECK3-NEXT: [[DIV12:%.*]] = sdiv i64 [[TMP12]], 11 1553 // CHECK3-NEXT: [[MUL13:%.*]] = mul nsw i64 [[DIV12]], 1 1554 // CHECK3-NEXT: [[ADD14:%.*]] = add nsw i64 [[CONV11]], [[MUL13]] 1555 // CHECK3-NEXT: [[CONV15:%.*]] = trunc i64 [[ADD14]] to i8 1556 // CHECK3-NEXT: store i8 [[CONV15]], i8* [[I8]], align 1 1557 // CHECK3-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1558 // CHECK3-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1559 // CHECK3-NEXT: [[DIV16:%.*]] = sdiv i64 [[TMP14]], 11 1560 // CHECK3-NEXT: [[MUL17:%.*]] = mul nsw i64 [[DIV16]], 11 1561 // CHECK3-NEXT: [[SUB18:%.*]] = sub nsw i64 [[TMP13]], [[MUL17]] 1562 // CHECK3-NEXT: [[MUL19:%.*]] = mul nsw i64 [[SUB18]], 1 1563 // CHECK3-NEXT: [[SUB20:%.*]] = sub nsw i64 11, [[MUL19]] 1564 // CHECK3-NEXT: [[CONV21:%.*]] = trunc i64 [[SUB20]] to i32 1565 // CHECK3-NEXT: store i32 [[CONV21]], i32* [[X9]], align 4 1566 // CHECK3-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 1567 // CHECK3-NEXT: [[TMP15:%.*]] = load float*, float** [[B_ADDR]], align 8 1568 // CHECK3-NEXT: [[TMP16:%.*]] = load i8, i8* [[I8]], align 1 1569 // CHECK3-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP16]] to i64 1570 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM]] 1571 // CHECK3-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4 1572 // CHECK3-NEXT: [[TMP18:%.*]] = load float*, float** [[C_ADDR]], align 8 1573 // CHECK3-NEXT: [[TMP19:%.*]] = load i8, i8* [[I8]], align 1 1574 // CHECK3-NEXT: [[IDXPROM22:%.*]] = sext i8 [[TMP19]] to i64 1575 // CHECK3-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM22]] 1576 // CHECK3-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX23]], align 4 1577 // CHECK3-NEXT: [[MUL24:%.*]] = fmul float [[TMP17]], [[TMP20]] 1578 // CHECK3-NEXT: [[TMP21:%.*]] = load float*, float** [[D_ADDR]], align 8 1579 // CHECK3-NEXT: [[TMP22:%.*]] = load i8, i8* [[I8]], align 1 1580 // CHECK3-NEXT: [[IDXPROM25:%.*]] = sext i8 [[TMP22]] to i64 1581 // CHECK3-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM25]] 1582 // CHECK3-NEXT: [[TMP23:%.*]] = load float, float* [[ARRAYIDX26]], align 4 1583 // CHECK3-NEXT: [[MUL27:%.*]] = fmul float [[MUL24]], [[TMP23]] 1584 // CHECK3-NEXT: [[TMP24:%.*]] = load float*, float** [[A_ADDR]], align 8 1585 // CHECK3-NEXT: [[TMP25:%.*]] = load i8, i8* [[I8]], align 1 1586 // CHECK3-NEXT: [[IDXPROM28:%.*]] = sext i8 [[TMP25]] to i64 1587 // CHECK3-NEXT: [[ARRAYIDX29:%.*]] = getelementptr inbounds float, float* [[TMP24]], i64 [[IDXPROM28]] 1588 // CHECK3-NEXT: store float [[MUL27]], float* [[ARRAYIDX29]], align 4 1589 // CHECK3-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 1590 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1591 // CHECK3: omp.body.continue: 1592 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1593 // CHECK3: omp.inner.for.inc: 1594 // CHECK3-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1595 // CHECK3-NEXT: [[ADD30:%.*]] = add nsw i64 [[TMP26]], 1 1596 // CHECK3-NEXT: store i64 [[ADD30]], i64* [[DOTOMP_IV]], align 8 1597 // CHECK3-NEXT: call void @__kmpc_dispatch_fini_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 1598 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 1599 // CHECK3: omp.inner.for.end: 1600 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1601 // CHECK3: omp.dispatch.inc: 1602 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]] 1603 // CHECK3: omp.dispatch.end: 1604 // CHECK3-NEXT: br label [[OMP_PRECOND_END]] 1605 // CHECK3: omp.precond.end: 1606 // CHECK3-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 1607 // CHECK3-NEXT: ret void 1608 // 1609 // 1610 // CHECK3-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_ 1611 // CHECK3-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 1612 // CHECK3-NEXT: entry: 1613 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 1614 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 1615 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 1616 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 1617 // CHECK3-NEXT: [[X:%.*]] = alloca i32, align 4 1618 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1619 // CHECK3-NEXT: [[TMP:%.*]] = alloca i8, align 1 1620 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1621 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1622 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1623 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1624 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1625 // CHECK3-NEXT: [[I:%.*]] = alloca i8, align 1 1626 // CHECK3-NEXT: [[X2:%.*]] = alloca i32, align 4 1627 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1628 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 1629 // CHECK3-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 1630 // CHECK3-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 1631 // CHECK3-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 1632 // CHECK3-NEXT: store i32 0, i32* [[X]], align 4 1633 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1634 // CHECK3-NEXT: store i32 199, i32* [[DOTOMP_UB]], align 4 1635 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1636 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1637 // CHECK3-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 69, i32 0, i32 199, i32 1, i32 1) 1638 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 1639 // CHECK3: omp.dispatch.cond: 1640 // CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 1641 // CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 1642 // CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 1643 // CHECK3: omp.dispatch.body: 1644 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1645 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_IV]], align 4 1646 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1647 // CHECK3: omp.inner.for.cond: 1648 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1649 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1650 // CHECK3-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP3]], [[TMP4]] 1651 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1652 // CHECK3: omp.inner.for.body: 1653 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1654 // CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 20 1655 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 1656 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 48, [[MUL]] 1657 // CHECK3-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i8 1658 // CHECK3-NEXT: store i8 [[CONV]], i8* [[I]], align 1 1659 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1660 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1661 // CHECK3-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP7]], 20 1662 // CHECK3-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 20 1663 // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP6]], [[MUL4]] 1664 // CHECK3-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 1665 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 -10, [[MUL5]] 1666 // CHECK3-NEXT: store i32 [[ADD6]], i32* [[X2]], align 4 1667 // CHECK3-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 1668 // CHECK3-NEXT: [[TMP8:%.*]] = load float*, float** [[B_ADDR]], align 8 1669 // CHECK3-NEXT: [[TMP9:%.*]] = load i8, i8* [[I]], align 1 1670 // CHECK3-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP9]] to i64 1671 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[IDXPROM]] 1672 // CHECK3-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX]], align 4 1673 // CHECK3-NEXT: [[TMP11:%.*]] = load float*, float** [[C_ADDR]], align 8 1674 // CHECK3-NEXT: [[TMP12:%.*]] = load i8, i8* [[I]], align 1 1675 // CHECK3-NEXT: [[IDXPROM7:%.*]] = zext i8 [[TMP12]] to i64 1676 // CHECK3-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[IDXPROM7]] 1677 // CHECK3-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX8]], align 4 1678 // CHECK3-NEXT: [[MUL9:%.*]] = fmul float [[TMP10]], [[TMP13]] 1679 // CHECK3-NEXT: [[TMP14:%.*]] = load float*, float** [[D_ADDR]], align 8 1680 // CHECK3-NEXT: [[TMP15:%.*]] = load i8, i8* [[I]], align 1 1681 // CHECK3-NEXT: [[IDXPROM10:%.*]] = zext i8 [[TMP15]] to i64 1682 // CHECK3-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM10]] 1683 // CHECK3-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX11]], align 4 1684 // CHECK3-NEXT: [[MUL12:%.*]] = fmul float [[MUL9]], [[TMP16]] 1685 // CHECK3-NEXT: [[TMP17:%.*]] = load float*, float** [[A_ADDR]], align 8 1686 // CHECK3-NEXT: [[TMP18:%.*]] = load i8, i8* [[I]], align 1 1687 // CHECK3-NEXT: [[IDXPROM13:%.*]] = zext i8 [[TMP18]] to i64 1688 // CHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM13]] 1689 // CHECK3-NEXT: store float [[MUL12]], float* [[ARRAYIDX14]], align 4 1690 // CHECK3-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 1691 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1692 // CHECK3: omp.body.continue: 1693 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1694 // CHECK3: omp.inner.for.inc: 1695 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1696 // CHECK3-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP19]], 1 1697 // CHECK3-NEXT: store i32 [[ADD15]], i32* [[DOTOMP_IV]], align 4 1698 // CHECK3-NEXT: call void @__kmpc_dispatch_fini_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 1699 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 1700 // CHECK3: omp.inner.for.end: 1701 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1702 // CHECK3: omp.dispatch.inc: 1703 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]] 1704 // CHECK3: omp.dispatch.end: 1705 // CHECK3-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 1706 // CHECK3-NEXT: ret void 1707 // 1708 // 1709 // CHECK3-LABEL: define {{[^@]+}}@_Z8foo_simdii 1710 // CHECK3-SAME: (i32 [[LOW:%.*]], i32 [[UP:%.*]]) #[[ATTR0]] { 1711 // CHECK3-NEXT: entry: 1712 // CHECK3-NEXT: [[LOW_ADDR:%.*]] = alloca i32, align 4 1713 // CHECK3-NEXT: [[UP_ADDR:%.*]] = alloca i32, align 4 1714 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1715 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1716 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 1717 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 1718 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1719 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1720 // CHECK3-NEXT: [[I5:%.*]] = alloca i32, align 4 1721 // CHECK3-NEXT: [[DOTOMP_IV16:%.*]] = alloca i32, align 4 1722 // CHECK3-NEXT: [[_TMP17:%.*]] = alloca i32, align 4 1723 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_18:%.*]] = alloca i32, align 4 1724 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_19:%.*]] = alloca i32, align 4 1725 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_20:%.*]] = alloca i32, align 4 1726 // CHECK3-NEXT: [[I26:%.*]] = alloca i32, align 4 1727 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1728 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1729 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1730 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1731 // CHECK3-NEXT: [[I28:%.*]] = alloca i32, align 4 1732 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1733 // CHECK3-NEXT: store i32 [[LOW]], i32* [[LOW_ADDR]], align 4 1734 // CHECK3-NEXT: store i32 [[UP]], i32* [[UP_ADDR]], align 4 1735 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[LOW_ADDR]], align 4 1736 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 1737 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[UP_ADDR]], align 4 1738 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 1739 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 1740 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1741 // CHECK3-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] 1742 // CHECK3-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1 1743 // CHECK3-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1 1744 // CHECK3-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 1745 // CHECK3-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1 1746 // CHECK3-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4 1747 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1748 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 1749 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1750 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 1751 // CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] 1752 // CHECK3-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]] 1753 // CHECK3: simd.if.then: 1754 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IV]], align 4 1755 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1756 // CHECK3: omp.inner.for.cond: 1757 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 1758 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !2 1759 // CHECK3-NEXT: [[ADD6:%.*]] = add i32 [[TMP9]], 1 1760 // CHECK3-NEXT: [[CMP7:%.*]] = icmp ult i32 [[TMP8]], [[ADD6]] 1761 // CHECK3-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1762 // CHECK3: omp.inner.for.body: 1763 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !2 1764 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 1765 // CHECK3-NEXT: [[MUL:%.*]] = mul i32 [[TMP11]], 1 1766 // CHECK3-NEXT: [[ADD8:%.*]] = add i32 [[TMP10]], [[MUL]] 1767 // CHECK3-NEXT: store i32 [[ADD8]], i32* [[I5]], align 4, !llvm.access.group !2 1768 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[I5]], align 4, !llvm.access.group !2 1769 // CHECK3-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64 1770 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM]] 1771 // CHECK3-NEXT: store float 0.000000e+00, float* [[ARRAYIDX]], align 4, !llvm.access.group !2 1772 // CHECK3-NEXT: call void @__captured_stmt(i32* [[I5]]), !llvm.access.group !2 1773 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1774 // CHECK3: omp.body.continue: 1775 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1776 // CHECK3: omp.inner.for.inc: 1777 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 1778 // CHECK3-NEXT: [[ADD9:%.*]] = add i32 [[TMP13]], 1 1779 // CHECK3-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 1780 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 1781 // CHECK3: omp.inner.for.end: 1782 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1783 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 1784 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1785 // CHECK3-NEXT: [[SUB10:%.*]] = sub i32 [[TMP15]], [[TMP16]] 1786 // CHECK3-NEXT: [[SUB11:%.*]] = sub i32 [[SUB10]], 1 1787 // CHECK3-NEXT: [[ADD12:%.*]] = add i32 [[SUB11]], 1 1788 // CHECK3-NEXT: [[DIV13:%.*]] = udiv i32 [[ADD12]], 1 1789 // CHECK3-NEXT: [[MUL14:%.*]] = mul i32 [[DIV13]], 1 1790 // CHECK3-NEXT: [[ADD15:%.*]] = add i32 [[TMP14]], [[MUL14]] 1791 // CHECK3-NEXT: store i32 [[ADD15]], i32* [[I5]], align 4 1792 // CHECK3-NEXT: br label [[SIMD_IF_END]] 1793 // CHECK3: simd.if.end: 1794 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[LOW_ADDR]], align 4 1795 // CHECK3-NEXT: store i32 [[TMP17]], i32* [[DOTCAPTURE_EXPR_18]], align 4 1796 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[UP_ADDR]], align 4 1797 // CHECK3-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_19]], align 4 1798 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 1799 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 1800 // CHECK3-NEXT: [[SUB21:%.*]] = sub i32 [[TMP19]], [[TMP20]] 1801 // CHECK3-NEXT: [[SUB22:%.*]] = sub i32 [[SUB21]], 1 1802 // CHECK3-NEXT: [[ADD23:%.*]] = add i32 [[SUB22]], 1 1803 // CHECK3-NEXT: [[DIV24:%.*]] = udiv i32 [[ADD23]], 1 1804 // CHECK3-NEXT: [[SUB25:%.*]] = sub i32 [[DIV24]], 1 1805 // CHECK3-NEXT: store i32 [[SUB25]], i32* [[DOTCAPTURE_EXPR_20]], align 4 1806 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 1807 // CHECK3-NEXT: store i32 [[TMP21]], i32* [[I26]], align 4 1808 // CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 1809 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 1810 // CHECK3-NEXT: [[CMP27:%.*]] = icmp slt i32 [[TMP22]], [[TMP23]] 1811 // CHECK3-NEXT: br i1 [[CMP27]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 1812 // CHECK3: omp.precond.then: 1813 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1814 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_20]], align 4 1815 // CHECK3-NEXT: store i32 [[TMP24]], i32* [[DOTOMP_UB]], align 4 1816 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1817 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1818 // CHECK3-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_20]], align 4 1819 // CHECK3-NEXT: call void @__kmpc_dispatch_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 66, i32 0, i32 [[TMP25]], i32 1, i32 1) 1820 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 1821 // CHECK3: omp.dispatch.cond: 1822 // CHECK3-NEXT: [[TMP26:%.*]] = call i32 @__kmpc_dispatch_next_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 1823 // CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP26]], 0 1824 // CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 1825 // CHECK3: omp.dispatch.body: 1826 // CHECK3-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1827 // CHECK3-NEXT: store i32 [[TMP27]], i32* [[DOTOMP_IV16]], align 4 1828 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND29:%.*]] 1829 // CHECK3: omp.inner.for.cond29: 1830 // CHECK3-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV16]], align 4 1831 // CHECK3-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1832 // CHECK3-NEXT: [[ADD30:%.*]] = add i32 [[TMP29]], 1 1833 // CHECK3-NEXT: [[CMP31:%.*]] = icmp ult i32 [[TMP28]], [[ADD30]] 1834 // CHECK3-NEXT: br i1 [[CMP31]], label [[OMP_INNER_FOR_BODY32:%.*]], label [[OMP_INNER_FOR_END40:%.*]] 1835 // CHECK3: omp.inner.for.body32: 1836 // CHECK3-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 1837 // CHECK3-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV16]], align 4 1838 // CHECK3-NEXT: [[MUL33:%.*]] = mul i32 [[TMP31]], 1 1839 // CHECK3-NEXT: [[ADD34:%.*]] = add i32 [[TMP30]], [[MUL33]] 1840 // CHECK3-NEXT: store i32 [[ADD34]], i32* [[I28]], align 4 1841 // CHECK3-NEXT: [[TMP32:%.*]] = load i32, i32* [[I28]], align 4 1842 // CHECK3-NEXT: [[IDXPROM35:%.*]] = sext i32 [[TMP32]] to i64 1843 // CHECK3-NEXT: [[ARRAYIDX36:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM35]] 1844 // CHECK3-NEXT: store float 0.000000e+00, float* [[ARRAYIDX36]], align 4 1845 // CHECK3-NEXT: call void @__captured_stmt.1(i32* [[I28]]) 1846 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE37:%.*]] 1847 // CHECK3: omp.body.continue37: 1848 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC38:%.*]] 1849 // CHECK3: omp.inner.for.inc38: 1850 // CHECK3-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_IV16]], align 4 1851 // CHECK3-NEXT: [[ADD39:%.*]] = add i32 [[TMP33]], 1 1852 // CHECK3-NEXT: store i32 [[ADD39]], i32* [[DOTOMP_IV16]], align 4 1853 // CHECK3-NEXT: call void @__kmpc_dispatch_fini_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 1854 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND29]], !llvm.loop [[LOOP6:![0-9]+]] 1855 // CHECK3: omp.inner.for.end40: 1856 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1857 // CHECK3: omp.dispatch.inc: 1858 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]] 1859 // CHECK3: omp.dispatch.end: 1860 // CHECK3-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 1861 // CHECK3-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 1862 // CHECK3-NEXT: br i1 [[TMP35]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1863 // CHECK3: .omp.final.then: 1864 // CHECK3-NEXT: [[TMP36:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 1865 // CHECK3-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 1866 // CHECK3-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 1867 // CHECK3-NEXT: [[SUB41:%.*]] = sub i32 [[TMP37]], [[TMP38]] 1868 // CHECK3-NEXT: [[SUB42:%.*]] = sub i32 [[SUB41]], 1 1869 // CHECK3-NEXT: [[ADD43:%.*]] = add i32 [[SUB42]], 1 1870 // CHECK3-NEXT: [[DIV44:%.*]] = udiv i32 [[ADD43]], 1 1871 // CHECK3-NEXT: [[MUL45:%.*]] = mul i32 [[DIV44]], 1 1872 // CHECK3-NEXT: [[ADD46:%.*]] = add i32 [[TMP36]], [[MUL45]] 1873 // CHECK3-NEXT: store i32 [[ADD46]], i32* [[I28]], align 4 1874 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 1875 // CHECK3: .omp.final.done: 1876 // CHECK3-NEXT: br label [[OMP_PRECOND_END]] 1877 // CHECK3: omp.precond.end: 1878 // CHECK3-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 1879 // CHECK3-NEXT: ret void 1880 // 1881 // 1882 // CHECK3-LABEL: define {{[^@]+}}@__captured_stmt 1883 // CHECK3-SAME: (i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR3:[0-9]+]] { 1884 // CHECK3-NEXT: entry: 1885 // CHECK3-NEXT: [[I_ADDR:%.*]] = alloca i32*, align 8 1886 // CHECK3-NEXT: store i32* [[I]], i32** [[I_ADDR]], align 8 1887 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[I_ADDR]], align 8 1888 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 1889 // CHECK3-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 1890 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM]] 1891 // CHECK3-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 1892 // CHECK3-NEXT: ret void 1893 // 1894 // 1895 // CHECK3-LABEL: define {{[^@]+}}@__captured_stmt.1 1896 // CHECK3-SAME: (i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR3]] { 1897 // CHECK3-NEXT: entry: 1898 // CHECK3-NEXT: [[I_ADDR:%.*]] = alloca i32*, align 8 1899 // CHECK3-NEXT: store i32* [[I]], i32** [[I_ADDR]], align 8 1900 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[I_ADDR]], align 8 1901 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 1902 // CHECK3-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 1903 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM]] 1904 // CHECK3-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 1905 // CHECK3-NEXT: ret void 1906 // 1907 // 1908 // CHECK4-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 1909 // CHECK4-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { 1910 // CHECK4-NEXT: entry: 1911 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 1912 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 1913 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 1914 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 1915 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1916 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 1917 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1918 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1919 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1920 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1921 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 1922 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 1923 // CHECK4-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 1924 // CHECK4-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 1925 // CHECK4-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 1926 // CHECK4-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 1927 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1928 // CHECK4-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 1929 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1930 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1931 // CHECK4-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 66, i32 0, i32 4571423, i32 1, i32 1) 1932 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 1933 // CHECK4: omp.dispatch.cond: 1934 // CHECK4-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 1935 // CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 1936 // CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 1937 // CHECK4: omp.dispatch.body: 1938 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1939 // CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_IV]], align 4 1940 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1941 // CHECK4: omp.inner.for.cond: 1942 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1943 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1944 // CHECK4-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP3]], [[TMP4]] 1945 // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1946 // CHECK4: omp.inner.for.body: 1947 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1948 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP5]], 7 1949 // CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 1950 // CHECK4-NEXT: store i32 [[SUB]], i32* [[I]], align 4 1951 // CHECK4-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 1952 // CHECK4-NEXT: [[TMP6:%.*]] = load float*, float** [[B_ADDR]], align 8 1953 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 1954 // CHECK4-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 1955 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP6]], i64 [[IDXPROM]] 1956 // CHECK4-NEXT: [[TMP8:%.*]] = load float, float* [[ARRAYIDX]], align 4 1957 // CHECK4-NEXT: [[TMP9:%.*]] = load float*, float** [[C_ADDR]], align 8 1958 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 1959 // CHECK4-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP10]] to i64 1960 // CHECK4-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP9]], i64 [[IDXPROM1]] 1961 // CHECK4-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX2]], align 4 1962 // CHECK4-NEXT: [[MUL3:%.*]] = fmul float [[TMP8]], [[TMP11]] 1963 // CHECK4-NEXT: [[TMP12:%.*]] = load float*, float** [[D_ADDR]], align 8 1964 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 1965 // CHECK4-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP13]] to i64 1966 // CHECK4-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM4]] 1967 // CHECK4-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX5]], align 4 1968 // CHECK4-NEXT: [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP14]] 1969 // CHECK4-NEXT: [[TMP15:%.*]] = load float*, float** [[A_ADDR]], align 8 1970 // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 1971 // CHECK4-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP16]] to i64 1972 // CHECK4-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM7]] 1973 // CHECK4-NEXT: store float [[MUL6]], float* [[ARRAYIDX8]], align 4 1974 // CHECK4-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 1975 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1976 // CHECK4: omp.body.continue: 1977 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1978 // CHECK4: omp.inner.for.inc: 1979 // CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1980 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP17]], 1 1981 // CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 1982 // CHECK4-NEXT: call void @__kmpc_dispatch_fini_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 1983 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] 1984 // CHECK4: omp.inner.for.end: 1985 // CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1986 // CHECK4: omp.dispatch.inc: 1987 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND]] 1988 // CHECK4: omp.dispatch.end: 1989 // CHECK4-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP0]]) 1990 // CHECK4-NEXT: ret void 1991 // 1992 // 1993 // CHECK4-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_ 1994 // CHECK4-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 1995 // CHECK4-NEXT: entry: 1996 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 1997 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 1998 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 1999 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 2000 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 2001 // CHECK4-NEXT: [[TMP:%.*]] = alloca i64, align 8 2002 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 2003 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 2004 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 2005 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2006 // CHECK4-NEXT: [[I:%.*]] = alloca i64, align 8 2007 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2008 // CHECK4-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 2009 // CHECK4-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 2010 // CHECK4-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 2011 // CHECK4-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 2012 // CHECK4-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 2013 // CHECK4-NEXT: store i64 16908287, i64* [[DOTOMP_UB]], align 8 2014 // CHECK4-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 2015 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2016 // CHECK4-NEXT: call void @__kmpc_dispatch_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 67, i64 0, i64 16908287, i64 1, i64 1) 2017 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 2018 // CHECK4: omp.dispatch.cond: 2019 // CHECK4-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 2020 // CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 2021 // CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 2022 // CHECK4: omp.dispatch.body: 2023 // CHECK4-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 2024 // CHECK4-NEXT: store i64 [[TMP2]], i64* [[DOTOMP_IV]], align 8 2025 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2026 // CHECK4: omp.inner.for.cond: 2027 // CHECK4-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2028 // CHECK4-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 2029 // CHECK4-NEXT: [[ADD:%.*]] = add i64 [[TMP4]], 1 2030 // CHECK4-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP3]], [[ADD]] 2031 // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2032 // CHECK4: omp.inner.for.body: 2033 // CHECK4-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2034 // CHECK4-NEXT: [[MUL:%.*]] = mul i64 [[TMP5]], 127 2035 // CHECK4-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]] 2036 // CHECK4-NEXT: store i64 [[ADD1]], i64* [[I]], align 8 2037 // CHECK4-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 2038 // CHECK4-NEXT: [[TMP6:%.*]] = load float*, float** [[B_ADDR]], align 8 2039 // CHECK4-NEXT: [[TMP7:%.*]] = load i64, i64* [[I]], align 8 2040 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP6]], i64 [[TMP7]] 2041 // CHECK4-NEXT: [[TMP8:%.*]] = load float, float* [[ARRAYIDX]], align 4 2042 // CHECK4-NEXT: [[TMP9:%.*]] = load float*, float** [[C_ADDR]], align 8 2043 // CHECK4-NEXT: [[TMP10:%.*]] = load i64, i64* [[I]], align 8 2044 // CHECK4-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP9]], i64 [[TMP10]] 2045 // CHECK4-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX2]], align 4 2046 // CHECK4-NEXT: [[MUL3:%.*]] = fmul float [[TMP8]], [[TMP11]] 2047 // CHECK4-NEXT: [[TMP12:%.*]] = load float*, float** [[D_ADDR]], align 8 2048 // CHECK4-NEXT: [[TMP13:%.*]] = load i64, i64* [[I]], align 8 2049 // CHECK4-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[TMP13]] 2050 // CHECK4-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX4]], align 4 2051 // CHECK4-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP14]] 2052 // CHECK4-NEXT: [[TMP15:%.*]] = load float*, float** [[A_ADDR]], align 8 2053 // CHECK4-NEXT: [[TMP16:%.*]] = load i64, i64* [[I]], align 8 2054 // CHECK4-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[TMP16]] 2055 // CHECK4-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4 2056 // CHECK4-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 2057 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2058 // CHECK4: omp.body.continue: 2059 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2060 // CHECK4: omp.inner.for.inc: 2061 // CHECK4-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2062 // CHECK4-NEXT: [[ADD7:%.*]] = add i64 [[TMP17]], 1 2063 // CHECK4-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8 2064 // CHECK4-NEXT: call void @__kmpc_dispatch_fini_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 2065 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] 2066 // CHECK4: omp.inner.for.end: 2067 // CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2068 // CHECK4: omp.dispatch.inc: 2069 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND]] 2070 // CHECK4: omp.dispatch.end: 2071 // CHECK4-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 2072 // CHECK4-NEXT: ret void 2073 // 2074 // 2075 // CHECK4-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_ 2076 // CHECK4-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 2077 // CHECK4-NEXT: entry: 2078 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 2079 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 2080 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 2081 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 2082 // CHECK4-NEXT: [[X:%.*]] = alloca i32, align 4 2083 // CHECK4-NEXT: [[Y:%.*]] = alloca i32, align 4 2084 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 2085 // CHECK4-NEXT: [[TMP:%.*]] = alloca i8, align 1 2086 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2087 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 2088 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8 2089 // CHECK4-NEXT: [[I:%.*]] = alloca i8, align 1 2090 // CHECK4-NEXT: [[X6:%.*]] = alloca i32, align 4 2091 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 2092 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 2093 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 2094 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2095 // CHECK4-NEXT: [[I8:%.*]] = alloca i8, align 1 2096 // CHECK4-NEXT: [[X9:%.*]] = alloca i32, align 4 2097 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2098 // CHECK4-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 2099 // CHECK4-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 2100 // CHECK4-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 2101 // CHECK4-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 2102 // CHECK4-NEXT: store i32 0, i32* [[X]], align 4 2103 // CHECK4-NEXT: store i32 0, i32* [[Y]], align 4 2104 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[Y]], align 4 2105 // CHECK4-NEXT: [[CONV:%.*]] = trunc i32 [[TMP1]] to i8 2106 // CHECK4-NEXT: store i8 [[CONV]], i8* [[DOTCAPTURE_EXPR_]], align 1 2107 // CHECK4-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 2108 // CHECK4-NEXT: [[CONV3:%.*]] = sext i8 [[TMP2]] to i32 2109 // CHECK4-NEXT: [[SUB:%.*]] = sub i32 57, [[CONV3]] 2110 // CHECK4-NEXT: [[ADD:%.*]] = add i32 [[SUB]], 1 2111 // CHECK4-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 2112 // CHECK4-NEXT: [[CONV4:%.*]] = zext i32 [[DIV]] to i64 2113 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV4]], 11 2114 // CHECK4-NEXT: [[SUB5:%.*]] = sub nsw i64 [[MUL]], 1 2115 // CHECK4-NEXT: store i64 [[SUB5]], i64* [[DOTCAPTURE_EXPR_2]], align 8 2116 // CHECK4-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 2117 // CHECK4-NEXT: store i8 [[TMP3]], i8* [[I]], align 1 2118 // CHECK4-NEXT: store i32 11, i32* [[X6]], align 4 2119 // CHECK4-NEXT: [[TMP4:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 2120 // CHECK4-NEXT: [[CONV7:%.*]] = sext i8 [[TMP4]] to i32 2121 // CHECK4-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV7]], 57 2122 // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 2123 // CHECK4: omp.precond.then: 2124 // CHECK4-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 2125 // CHECK4-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 2126 // CHECK4-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_UB]], align 8 2127 // CHECK4-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 2128 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2129 // CHECK4-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 2130 // CHECK4-NEXT: call void @__kmpc_dispatch_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 70, i64 0, i64 [[TMP6]], i64 1, i64 1) 2131 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 2132 // CHECK4: omp.dispatch.cond: 2133 // CHECK4-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_dispatch_next_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 2134 // CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0 2135 // CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 2136 // CHECK4: omp.dispatch.body: 2137 // CHECK4-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 2138 // CHECK4-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 2139 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2140 // CHECK4: omp.inner.for.cond: 2141 // CHECK4-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2142 // CHECK4-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 2143 // CHECK4-NEXT: [[CMP10:%.*]] = icmp sle i64 [[TMP9]], [[TMP10]] 2144 // CHECK4-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2145 // CHECK4: omp.inner.for.body: 2146 // CHECK4-NEXT: [[TMP11:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 2147 // CHECK4-NEXT: [[CONV11:%.*]] = sext i8 [[TMP11]] to i64 2148 // CHECK4-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2149 // CHECK4-NEXT: [[DIV12:%.*]] = sdiv i64 [[TMP12]], 11 2150 // CHECK4-NEXT: [[MUL13:%.*]] = mul nsw i64 [[DIV12]], 1 2151 // CHECK4-NEXT: [[ADD14:%.*]] = add nsw i64 [[CONV11]], [[MUL13]] 2152 // CHECK4-NEXT: [[CONV15:%.*]] = trunc i64 [[ADD14]] to i8 2153 // CHECK4-NEXT: store i8 [[CONV15]], i8* [[I8]], align 1 2154 // CHECK4-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2155 // CHECK4-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2156 // CHECK4-NEXT: [[DIV16:%.*]] = sdiv i64 [[TMP14]], 11 2157 // CHECK4-NEXT: [[MUL17:%.*]] = mul nsw i64 [[DIV16]], 11 2158 // CHECK4-NEXT: [[SUB18:%.*]] = sub nsw i64 [[TMP13]], [[MUL17]] 2159 // CHECK4-NEXT: [[MUL19:%.*]] = mul nsw i64 [[SUB18]], 1 2160 // CHECK4-NEXT: [[SUB20:%.*]] = sub nsw i64 11, [[MUL19]] 2161 // CHECK4-NEXT: [[CONV21:%.*]] = trunc i64 [[SUB20]] to i32 2162 // CHECK4-NEXT: store i32 [[CONV21]], i32* [[X9]], align 4 2163 // CHECK4-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 2164 // CHECK4-NEXT: [[TMP15:%.*]] = load float*, float** [[B_ADDR]], align 8 2165 // CHECK4-NEXT: [[TMP16:%.*]] = load i8, i8* [[I8]], align 1 2166 // CHECK4-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP16]] to i64 2167 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM]] 2168 // CHECK4-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX]], align 4 2169 // CHECK4-NEXT: [[TMP18:%.*]] = load float*, float** [[C_ADDR]], align 8 2170 // CHECK4-NEXT: [[TMP19:%.*]] = load i8, i8* [[I8]], align 1 2171 // CHECK4-NEXT: [[IDXPROM22:%.*]] = sext i8 [[TMP19]] to i64 2172 // CHECK4-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM22]] 2173 // CHECK4-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX23]], align 4 2174 // CHECK4-NEXT: [[MUL24:%.*]] = fmul float [[TMP17]], [[TMP20]] 2175 // CHECK4-NEXT: [[TMP21:%.*]] = load float*, float** [[D_ADDR]], align 8 2176 // CHECK4-NEXT: [[TMP22:%.*]] = load i8, i8* [[I8]], align 1 2177 // CHECK4-NEXT: [[IDXPROM25:%.*]] = sext i8 [[TMP22]] to i64 2178 // CHECK4-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM25]] 2179 // CHECK4-NEXT: [[TMP23:%.*]] = load float, float* [[ARRAYIDX26]], align 4 2180 // CHECK4-NEXT: [[MUL27:%.*]] = fmul float [[MUL24]], [[TMP23]] 2181 // CHECK4-NEXT: [[TMP24:%.*]] = load float*, float** [[A_ADDR]], align 8 2182 // CHECK4-NEXT: [[TMP25:%.*]] = load i8, i8* [[I8]], align 1 2183 // CHECK4-NEXT: [[IDXPROM28:%.*]] = sext i8 [[TMP25]] to i64 2184 // CHECK4-NEXT: [[ARRAYIDX29:%.*]] = getelementptr inbounds float, float* [[TMP24]], i64 [[IDXPROM28]] 2185 // CHECK4-NEXT: store float [[MUL27]], float* [[ARRAYIDX29]], align 4 2186 // CHECK4-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 2187 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2188 // CHECK4: omp.body.continue: 2189 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2190 // CHECK4: omp.inner.for.inc: 2191 // CHECK4-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2192 // CHECK4-NEXT: [[ADD30:%.*]] = add nsw i64 [[TMP26]], 1 2193 // CHECK4-NEXT: store i64 [[ADD30]], i64* [[DOTOMP_IV]], align 8 2194 // CHECK4-NEXT: call void @__kmpc_dispatch_fini_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 2195 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] 2196 // CHECK4: omp.inner.for.end: 2197 // CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2198 // CHECK4: omp.dispatch.inc: 2199 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND]] 2200 // CHECK4: omp.dispatch.end: 2201 // CHECK4-NEXT: br label [[OMP_PRECOND_END]] 2202 // CHECK4: omp.precond.end: 2203 // CHECK4-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 2204 // CHECK4-NEXT: ret void 2205 // 2206 // 2207 // CHECK4-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_ 2208 // CHECK4-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 2209 // CHECK4-NEXT: entry: 2210 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 2211 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 2212 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 2213 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 2214 // CHECK4-NEXT: [[X:%.*]] = alloca i32, align 4 2215 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2216 // CHECK4-NEXT: [[TMP:%.*]] = alloca i8, align 1 2217 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2218 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2219 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2220 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2221 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2222 // CHECK4-NEXT: [[I:%.*]] = alloca i8, align 1 2223 // CHECK4-NEXT: [[X2:%.*]] = alloca i32, align 4 2224 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2225 // CHECK4-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 2226 // CHECK4-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 2227 // CHECK4-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 2228 // CHECK4-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 2229 // CHECK4-NEXT: store i32 0, i32* [[X]], align 4 2230 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2231 // CHECK4-NEXT: store i32 199, i32* [[DOTOMP_UB]], align 4 2232 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2233 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2234 // CHECK4-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 69, i32 0, i32 199, i32 1, i32 1) 2235 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 2236 // CHECK4: omp.dispatch.cond: 2237 // CHECK4-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 2238 // CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 2239 // CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 2240 // CHECK4: omp.dispatch.body: 2241 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2242 // CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTOMP_IV]], align 4 2243 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2244 // CHECK4: omp.inner.for.cond: 2245 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2246 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2247 // CHECK4-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP3]], [[TMP4]] 2248 // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2249 // CHECK4: omp.inner.for.body: 2250 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2251 // CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 20 2252 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 2253 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 48, [[MUL]] 2254 // CHECK4-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i8 2255 // CHECK4-NEXT: store i8 [[CONV]], i8* [[I]], align 1 2256 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2257 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2258 // CHECK4-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP7]], 20 2259 // CHECK4-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 20 2260 // CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP6]], [[MUL4]] 2261 // CHECK4-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 2262 // CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 -10, [[MUL5]] 2263 // CHECK4-NEXT: store i32 [[ADD6]], i32* [[X2]], align 4 2264 // CHECK4-NEXT: call void @__kmpc_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 2265 // CHECK4-NEXT: [[TMP8:%.*]] = load float*, float** [[B_ADDR]], align 8 2266 // CHECK4-NEXT: [[TMP9:%.*]] = load i8, i8* [[I]], align 1 2267 // CHECK4-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP9]] to i64 2268 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[IDXPROM]] 2269 // CHECK4-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX]], align 4 2270 // CHECK4-NEXT: [[TMP11:%.*]] = load float*, float** [[C_ADDR]], align 8 2271 // CHECK4-NEXT: [[TMP12:%.*]] = load i8, i8* [[I]], align 1 2272 // CHECK4-NEXT: [[IDXPROM7:%.*]] = zext i8 [[TMP12]] to i64 2273 // CHECK4-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[IDXPROM7]] 2274 // CHECK4-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX8]], align 4 2275 // CHECK4-NEXT: [[MUL9:%.*]] = fmul float [[TMP10]], [[TMP13]] 2276 // CHECK4-NEXT: [[TMP14:%.*]] = load float*, float** [[D_ADDR]], align 8 2277 // CHECK4-NEXT: [[TMP15:%.*]] = load i8, i8* [[I]], align 1 2278 // CHECK4-NEXT: [[IDXPROM10:%.*]] = zext i8 [[TMP15]] to i64 2279 // CHECK4-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM10]] 2280 // CHECK4-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX11]], align 4 2281 // CHECK4-NEXT: [[MUL12:%.*]] = fmul float [[MUL9]], [[TMP16]] 2282 // CHECK4-NEXT: [[TMP17:%.*]] = load float*, float** [[A_ADDR]], align 8 2283 // CHECK4-NEXT: [[TMP18:%.*]] = load i8, i8* [[I]], align 1 2284 // CHECK4-NEXT: [[IDXPROM13:%.*]] = zext i8 [[TMP18]] to i64 2285 // CHECK4-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM13]] 2286 // CHECK4-NEXT: store float [[MUL12]], float* [[ARRAYIDX14]], align 4 2287 // CHECK4-NEXT: call void @__kmpc_end_ordered(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 2288 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2289 // CHECK4: omp.body.continue: 2290 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2291 // CHECK4: omp.inner.for.inc: 2292 // CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2293 // CHECK4-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP19]], 1 2294 // CHECK4-NEXT: store i32 [[ADD15]], i32* [[DOTOMP_IV]], align 4 2295 // CHECK4-NEXT: call void @__kmpc_dispatch_fini_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 2296 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] 2297 // CHECK4: omp.inner.for.end: 2298 // CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2299 // CHECK4: omp.dispatch.inc: 2300 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND]] 2301 // CHECK4: omp.dispatch.end: 2302 // CHECK4-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 2303 // CHECK4-NEXT: ret void 2304 // 2305 // 2306 // CHECK4-LABEL: define {{[^@]+}}@_Z8foo_simdii 2307 // CHECK4-SAME: (i32 [[LOW:%.*]], i32 [[UP:%.*]]) #[[ATTR0]] { 2308 // CHECK4-NEXT: entry: 2309 // CHECK4-NEXT: [[LOW_ADDR:%.*]] = alloca i32, align 4 2310 // CHECK4-NEXT: [[UP_ADDR:%.*]] = alloca i32, align 4 2311 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 2312 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 2313 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 2314 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 2315 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 2316 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2317 // CHECK4-NEXT: [[I5:%.*]] = alloca i32, align 4 2318 // CHECK4-NEXT: [[DOTOMP_IV16:%.*]] = alloca i32, align 4 2319 // CHECK4-NEXT: [[_TMP17:%.*]] = alloca i32, align 4 2320 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_18:%.*]] = alloca i32, align 4 2321 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_19:%.*]] = alloca i32, align 4 2322 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_20:%.*]] = alloca i32, align 4 2323 // CHECK4-NEXT: [[I26:%.*]] = alloca i32, align 4 2324 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2325 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2326 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2327 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2328 // CHECK4-NEXT: [[I28:%.*]] = alloca i32, align 4 2329 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2330 // CHECK4-NEXT: store i32 [[LOW]], i32* [[LOW_ADDR]], align 4 2331 // CHECK4-NEXT: store i32 [[UP]], i32* [[UP_ADDR]], align 4 2332 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[LOW_ADDR]], align 4 2333 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 2334 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[UP_ADDR]], align 4 2335 // CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 2336 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 2337 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 2338 // CHECK4-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] 2339 // CHECK4-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1 2340 // CHECK4-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1 2341 // CHECK4-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 2342 // CHECK4-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1 2343 // CHECK4-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4 2344 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 2345 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[I]], align 4 2346 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 2347 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 2348 // CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] 2349 // CHECK4-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]] 2350 // CHECK4: simd.if.then: 2351 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IV]], align 4 2352 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2353 // CHECK4: omp.inner.for.cond: 2354 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 2355 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !2 2356 // CHECK4-NEXT: [[ADD6:%.*]] = add i32 [[TMP9]], 1 2357 // CHECK4-NEXT: [[CMP7:%.*]] = icmp ult i32 [[TMP8]], [[ADD6]] 2358 // CHECK4-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2359 // CHECK4: omp.inner.for.body: 2360 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !2 2361 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 2362 // CHECK4-NEXT: [[MUL:%.*]] = mul i32 [[TMP11]], 1 2363 // CHECK4-NEXT: [[ADD8:%.*]] = add i32 [[TMP10]], [[MUL]] 2364 // CHECK4-NEXT: store i32 [[ADD8]], i32* [[I5]], align 4, !llvm.access.group !2 2365 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[I5]], align 4, !llvm.access.group !2 2366 // CHECK4-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64 2367 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM]] 2368 // CHECK4-NEXT: store float 0.000000e+00, float* [[ARRAYIDX]], align 4, !llvm.access.group !2 2369 // CHECK4-NEXT: call void @__captured_stmt(i32* [[I5]]), !llvm.access.group !2 2370 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2371 // CHECK4: omp.body.continue: 2372 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2373 // CHECK4: omp.inner.for.inc: 2374 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 2375 // CHECK4-NEXT: [[ADD9:%.*]] = add i32 [[TMP13]], 1 2376 // CHECK4-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 2377 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 2378 // CHECK4: omp.inner.for.end: 2379 // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 2380 // CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 2381 // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 2382 // CHECK4-NEXT: [[SUB10:%.*]] = sub i32 [[TMP15]], [[TMP16]] 2383 // CHECK4-NEXT: [[SUB11:%.*]] = sub i32 [[SUB10]], 1 2384 // CHECK4-NEXT: [[ADD12:%.*]] = add i32 [[SUB11]], 1 2385 // CHECK4-NEXT: [[DIV13:%.*]] = udiv i32 [[ADD12]], 1 2386 // CHECK4-NEXT: [[MUL14:%.*]] = mul i32 [[DIV13]], 1 2387 // CHECK4-NEXT: [[ADD15:%.*]] = add i32 [[TMP14]], [[MUL14]] 2388 // CHECK4-NEXT: store i32 [[ADD15]], i32* [[I5]], align 4 2389 // CHECK4-NEXT: br label [[SIMD_IF_END]] 2390 // CHECK4: simd.if.end: 2391 // CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[LOW_ADDR]], align 4 2392 // CHECK4-NEXT: store i32 [[TMP17]], i32* [[DOTCAPTURE_EXPR_18]], align 4 2393 // CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[UP_ADDR]], align 4 2394 // CHECK4-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_19]], align 4 2395 // CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 2396 // CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 2397 // CHECK4-NEXT: [[SUB21:%.*]] = sub i32 [[TMP19]], [[TMP20]] 2398 // CHECK4-NEXT: [[SUB22:%.*]] = sub i32 [[SUB21]], 1 2399 // CHECK4-NEXT: [[ADD23:%.*]] = add i32 [[SUB22]], 1 2400 // CHECK4-NEXT: [[DIV24:%.*]] = udiv i32 [[ADD23]], 1 2401 // CHECK4-NEXT: [[SUB25:%.*]] = sub i32 [[DIV24]], 1 2402 // CHECK4-NEXT: store i32 [[SUB25]], i32* [[DOTCAPTURE_EXPR_20]], align 4 2403 // CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 2404 // CHECK4-NEXT: store i32 [[TMP21]], i32* [[I26]], align 4 2405 // CHECK4-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 2406 // CHECK4-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 2407 // CHECK4-NEXT: [[CMP27:%.*]] = icmp slt i32 [[TMP22]], [[TMP23]] 2408 // CHECK4-NEXT: br i1 [[CMP27]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 2409 // CHECK4: omp.precond.then: 2410 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2411 // CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_20]], align 4 2412 // CHECK4-NEXT: store i32 [[TMP24]], i32* [[DOTOMP_UB]], align 4 2413 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2414 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2415 // CHECK4-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_20]], align 4 2416 // CHECK4-NEXT: call void @__kmpc_dispatch_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 66, i32 0, i32 [[TMP25]], i32 1, i32 1) 2417 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 2418 // CHECK4: omp.dispatch.cond: 2419 // CHECK4-NEXT: [[TMP26:%.*]] = call i32 @__kmpc_dispatch_next_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 2420 // CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP26]], 0 2421 // CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 2422 // CHECK4: omp.dispatch.body: 2423 // CHECK4-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2424 // CHECK4-NEXT: store i32 [[TMP27]], i32* [[DOTOMP_IV16]], align 4 2425 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND29:%.*]] 2426 // CHECK4: omp.inner.for.cond29: 2427 // CHECK4-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV16]], align 4 2428 // CHECK4-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2429 // CHECK4-NEXT: [[ADD30:%.*]] = add i32 [[TMP29]], 1 2430 // CHECK4-NEXT: [[CMP31:%.*]] = icmp ult i32 [[TMP28]], [[ADD30]] 2431 // CHECK4-NEXT: br i1 [[CMP31]], label [[OMP_INNER_FOR_BODY32:%.*]], label [[OMP_INNER_FOR_END40:%.*]] 2432 // CHECK4: omp.inner.for.body32: 2433 // CHECK4-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 2434 // CHECK4-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV16]], align 4 2435 // CHECK4-NEXT: [[MUL33:%.*]] = mul i32 [[TMP31]], 1 2436 // CHECK4-NEXT: [[ADD34:%.*]] = add i32 [[TMP30]], [[MUL33]] 2437 // CHECK4-NEXT: store i32 [[ADD34]], i32* [[I28]], align 4 2438 // CHECK4-NEXT: [[TMP32:%.*]] = load i32, i32* [[I28]], align 4 2439 // CHECK4-NEXT: [[IDXPROM35:%.*]] = sext i32 [[TMP32]] to i64 2440 // CHECK4-NEXT: [[ARRAYIDX36:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM35]] 2441 // CHECK4-NEXT: store float 0.000000e+00, float* [[ARRAYIDX36]], align 4 2442 // CHECK4-NEXT: call void @__captured_stmt.1(i32* [[I28]]) 2443 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE37:%.*]] 2444 // CHECK4: omp.body.continue37: 2445 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC38:%.*]] 2446 // CHECK4: omp.inner.for.inc38: 2447 // CHECK4-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_IV16]], align 4 2448 // CHECK4-NEXT: [[ADD39:%.*]] = add i32 [[TMP33]], 1 2449 // CHECK4-NEXT: store i32 [[ADD39]], i32* [[DOTOMP_IV16]], align 4 2450 // CHECK4-NEXT: call void @__kmpc_dispatch_fini_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 2451 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND29]], !llvm.loop [[LOOP6:![0-9]+]] 2452 // CHECK4: omp.inner.for.end40: 2453 // CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2454 // CHECK4: omp.dispatch.inc: 2455 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND]] 2456 // CHECK4: omp.dispatch.end: 2457 // CHECK4-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 2458 // CHECK4-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 2459 // CHECK4-NEXT: br i1 [[TMP35]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2460 // CHECK4: .omp.final.then: 2461 // CHECK4-NEXT: [[TMP36:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 2462 // CHECK4-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 2463 // CHECK4-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_18]], align 4 2464 // CHECK4-NEXT: [[SUB41:%.*]] = sub i32 [[TMP37]], [[TMP38]] 2465 // CHECK4-NEXT: [[SUB42:%.*]] = sub i32 [[SUB41]], 1 2466 // CHECK4-NEXT: [[ADD43:%.*]] = add i32 [[SUB42]], 1 2467 // CHECK4-NEXT: [[DIV44:%.*]] = udiv i32 [[ADD43]], 1 2468 // CHECK4-NEXT: [[MUL45:%.*]] = mul i32 [[DIV44]], 1 2469 // CHECK4-NEXT: [[ADD46:%.*]] = add i32 [[TMP36]], [[MUL45]] 2470 // CHECK4-NEXT: store i32 [[ADD46]], i32* [[I28]], align 4 2471 // CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]] 2472 // CHECK4: .omp.final.done: 2473 // CHECK4-NEXT: br label [[OMP_PRECOND_END]] 2474 // CHECK4: omp.precond.end: 2475 // CHECK4-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 2476 // CHECK4-NEXT: ret void 2477 // 2478 // 2479 // CHECK4-LABEL: define {{[^@]+}}@__captured_stmt 2480 // CHECK4-SAME: (i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR3:[0-9]+]] { 2481 // CHECK4-NEXT: entry: 2482 // CHECK4-NEXT: [[I_ADDR:%.*]] = alloca i32*, align 8 2483 // CHECK4-NEXT: store i32* [[I]], i32** [[I_ADDR]], align 8 2484 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[I_ADDR]], align 8 2485 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 2486 // CHECK4-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 2487 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM]] 2488 // CHECK4-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 2489 // CHECK4-NEXT: ret void 2490 // 2491 // 2492 // CHECK4-LABEL: define {{[^@]+}}@__captured_stmt.1 2493 // CHECK4-SAME: (i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR3]] { 2494 // CHECK4-NEXT: entry: 2495 // CHECK4-NEXT: [[I_ADDR:%.*]] = alloca i32*, align 8 2496 // CHECK4-NEXT: store i32* [[I]], i32** [[I_ADDR]], align 8 2497 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[I_ADDR]], align 8 2498 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 2499 // CHECK4-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 2500 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM]] 2501 // CHECK4-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 2502 // CHECK4-NEXT: ret void 2503 // 2504 // 2505 // CHECK5-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 2506 // CHECK5-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { 2507 // CHECK5-NEXT: entry: 2508 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 2509 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 2510 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 2511 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 2512 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 2513 // CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 2514 // CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 2515 // CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 2516 // CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 2517 // CHECK5-NEXT: store i32 32000000, i32* [[I]], align 4 2518 // CHECK5-NEXT: br label [[FOR_COND:%.*]] 2519 // CHECK5: for.cond: 2520 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 2521 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 33 2522 // CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 2523 // CHECK5: for.body: 2524 // CHECK5-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 2525 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 2526 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 2527 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] 2528 // CHECK5-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 2529 // CHECK5-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 2530 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 2531 // CHECK5-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64 2532 // CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] 2533 // CHECK5-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 2534 // CHECK5-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] 2535 // CHECK5-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 2536 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 2537 // CHECK5-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64 2538 // CHECK5-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] 2539 // CHECK5-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 2540 // CHECK5-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] 2541 // CHECK5-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 2542 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 2543 // CHECK5-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64 2544 // CHECK5-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] 2545 // CHECK5-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 2546 // CHECK5-NEXT: br label [[FOR_INC:%.*]] 2547 // CHECK5: for.inc: 2548 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 2549 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], -7 2550 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4 2551 // CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] 2552 // CHECK5: for.end: 2553 // CHECK5-NEXT: ret void 2554 // 2555 // 2556 // CHECK5-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_ 2557 // CHECK5-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 2558 // CHECK5-NEXT: entry: 2559 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 2560 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 2561 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 2562 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 2563 // CHECK5-NEXT: [[I:%.*]] = alloca i64, align 8 2564 // CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 2565 // CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 2566 // CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 2567 // CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 2568 // CHECK5-NEXT: store i64 131071, i64* [[I]], align 8 2569 // CHECK5-NEXT: br label [[FOR_COND:%.*]] 2570 // CHECK5: for.cond: 2571 // CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 2572 // CHECK5-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP0]], 2147483647 2573 // CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 2574 // CHECK5: for.body: 2575 // CHECK5-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 2576 // CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[I]], align 8 2577 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[TMP2]] 2578 // CHECK5-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 2579 // CHECK5-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 2580 // CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[I]], align 8 2581 // CHECK5-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[TMP5]] 2582 // CHECK5-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 2583 // CHECK5-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] 2584 // CHECK5-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 2585 // CHECK5-NEXT: [[TMP8:%.*]] = load i64, i64* [[I]], align 8 2586 // CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[TMP8]] 2587 // CHECK5-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 2588 // CHECK5-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] 2589 // CHECK5-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 2590 // CHECK5-NEXT: [[TMP11:%.*]] = load i64, i64* [[I]], align 8 2591 // CHECK5-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[TMP11]] 2592 // CHECK5-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 2593 // CHECK5-NEXT: br label [[FOR_INC:%.*]] 2594 // CHECK5: for.inc: 2595 // CHECK5-NEXT: [[TMP12:%.*]] = load i64, i64* [[I]], align 8 2596 // CHECK5-NEXT: [[ADD:%.*]] = add i64 [[TMP12]], 127 2597 // CHECK5-NEXT: store i64 [[ADD]], i64* [[I]], align 8 2598 // CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 2599 // CHECK5: for.end: 2600 // CHECK5-NEXT: ret void 2601 // 2602 // 2603 // CHECK5-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_ 2604 // CHECK5-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 2605 // CHECK5-NEXT: entry: 2606 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 2607 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 2608 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 2609 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 2610 // CHECK5-NEXT: [[X:%.*]] = alloca i32, align 4 2611 // CHECK5-NEXT: [[Y:%.*]] = alloca i32, align 4 2612 // CHECK5-NEXT: [[I:%.*]] = alloca i8, align 1 2613 // CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 2614 // CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 2615 // CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 2616 // CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 2617 // CHECK5-NEXT: store i32 0, i32* [[X]], align 4 2618 // CHECK5-NEXT: store i32 0, i32* [[Y]], align 4 2619 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[Y]], align 4 2620 // CHECK5-NEXT: [[CONV:%.*]] = trunc i32 [[TMP0]] to i8 2621 // CHECK5-NEXT: store i8 [[CONV]], i8* [[I]], align 1 2622 // CHECK5-NEXT: br label [[FOR_COND:%.*]] 2623 // CHECK5: for.cond: 2624 // CHECK5-NEXT: [[TMP1:%.*]] = load i8, i8* [[I]], align 1 2625 // CHECK5-NEXT: [[CONV1:%.*]] = sext i8 [[TMP1]] to i32 2626 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV1]], 57 2627 // CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END13:%.*]] 2628 // CHECK5: for.body: 2629 // CHECK5-NEXT: store i32 11, i32* [[X]], align 4 2630 // CHECK5-NEXT: br label [[FOR_COND2:%.*]] 2631 // CHECK5: for.cond2: 2632 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[X]], align 4 2633 // CHECK5-NEXT: [[CMP3:%.*]] = icmp ugt i32 [[TMP2]], 0 2634 // CHECK5-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END:%.*]] 2635 // CHECK5: for.body4: 2636 // CHECK5-NEXT: [[TMP3:%.*]] = load float*, float** [[B_ADDR]], align 8 2637 // CHECK5-NEXT: [[TMP4:%.*]] = load i8, i8* [[I]], align 1 2638 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP4]] to i64 2639 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP3]], i64 [[IDXPROM]] 2640 // CHECK5-NEXT: [[TMP5:%.*]] = load float, float* [[ARRAYIDX]], align 4 2641 // CHECK5-NEXT: [[TMP6:%.*]] = load float*, float** [[C_ADDR]], align 8 2642 // CHECK5-NEXT: [[TMP7:%.*]] = load i8, i8* [[I]], align 1 2643 // CHECK5-NEXT: [[IDXPROM5:%.*]] = sext i8 [[TMP7]] to i64 2644 // CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP6]], i64 [[IDXPROM5]] 2645 // CHECK5-NEXT: [[TMP8:%.*]] = load float, float* [[ARRAYIDX6]], align 4 2646 // CHECK5-NEXT: [[MUL:%.*]] = fmul float [[TMP5]], [[TMP8]] 2647 // CHECK5-NEXT: [[TMP9:%.*]] = load float*, float** [[D_ADDR]], align 8 2648 // CHECK5-NEXT: [[TMP10:%.*]] = load i8, i8* [[I]], align 1 2649 // CHECK5-NEXT: [[IDXPROM7:%.*]] = sext i8 [[TMP10]] to i64 2650 // CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP9]], i64 [[IDXPROM7]] 2651 // CHECK5-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX8]], align 4 2652 // CHECK5-NEXT: [[MUL9:%.*]] = fmul float [[MUL]], [[TMP11]] 2653 // CHECK5-NEXT: [[TMP12:%.*]] = load float*, float** [[A_ADDR]], align 8 2654 // CHECK5-NEXT: [[TMP13:%.*]] = load i8, i8* [[I]], align 1 2655 // CHECK5-NEXT: [[IDXPROM10:%.*]] = sext i8 [[TMP13]] to i64 2656 // CHECK5-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM10]] 2657 // CHECK5-NEXT: store float [[MUL9]], float* [[ARRAYIDX11]], align 4 2658 // CHECK5-NEXT: br label [[FOR_INC:%.*]] 2659 // CHECK5: for.inc: 2660 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[X]], align 4 2661 // CHECK5-NEXT: [[DEC:%.*]] = add i32 [[TMP14]], -1 2662 // CHECK5-NEXT: store i32 [[DEC]], i32* [[X]], align 4 2663 // CHECK5-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP5:![0-9]+]] 2664 // CHECK5: for.end: 2665 // CHECK5-NEXT: br label [[FOR_INC12:%.*]] 2666 // CHECK5: for.inc12: 2667 // CHECK5-NEXT: [[TMP15:%.*]] = load i8, i8* [[I]], align 1 2668 // CHECK5-NEXT: [[INC:%.*]] = add i8 [[TMP15]], 1 2669 // CHECK5-NEXT: store i8 [[INC]], i8* [[I]], align 1 2670 // CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 2671 // CHECK5: for.end13: 2672 // CHECK5-NEXT: ret void 2673 // 2674 // 2675 // CHECK5-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_ 2676 // CHECK5-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 2677 // CHECK5-NEXT: entry: 2678 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 2679 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 2680 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 2681 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 2682 // CHECK5-NEXT: [[X:%.*]] = alloca i32, align 4 2683 // CHECK5-NEXT: [[I:%.*]] = alloca i8, align 1 2684 // CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 2685 // CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 2686 // CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 2687 // CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 2688 // CHECK5-NEXT: store i32 0, i32* [[X]], align 4 2689 // CHECK5-NEXT: store i8 48, i8* [[I]], align 1 2690 // CHECK5-NEXT: br label [[FOR_COND:%.*]] 2691 // CHECK5: for.cond: 2692 // CHECK5-NEXT: [[TMP0:%.*]] = load i8, i8* [[I]], align 1 2693 // CHECK5-NEXT: [[CONV:%.*]] = zext i8 [[TMP0]] to i32 2694 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV]], 57 2695 // CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END13:%.*]] 2696 // CHECK5: for.body: 2697 // CHECK5-NEXT: store i32 -10, i32* [[X]], align 4 2698 // CHECK5-NEXT: br label [[FOR_COND1:%.*]] 2699 // CHECK5: for.cond1: 2700 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[X]], align 4 2701 // CHECK5-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP1]], 10 2702 // CHECK5-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] 2703 // CHECK5: for.body3: 2704 // CHECK5-NEXT: [[TMP2:%.*]] = load float*, float** [[B_ADDR]], align 8 2705 // CHECK5-NEXT: [[TMP3:%.*]] = load i8, i8* [[I]], align 1 2706 // CHECK5-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP3]] to i64 2707 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 [[IDXPROM]] 2708 // CHECK5-NEXT: [[TMP4:%.*]] = load float, float* [[ARRAYIDX]], align 4 2709 // CHECK5-NEXT: [[TMP5:%.*]] = load float*, float** [[C_ADDR]], align 8 2710 // CHECK5-NEXT: [[TMP6:%.*]] = load i8, i8* [[I]], align 1 2711 // CHECK5-NEXT: [[IDXPROM4:%.*]] = zext i8 [[TMP6]] to i64 2712 // CHECK5-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP5]], i64 [[IDXPROM4]] 2713 // CHECK5-NEXT: [[TMP7:%.*]] = load float, float* [[ARRAYIDX5]], align 4 2714 // CHECK5-NEXT: [[MUL:%.*]] = fmul float [[TMP4]], [[TMP7]] 2715 // CHECK5-NEXT: [[TMP8:%.*]] = load float*, float** [[D_ADDR]], align 8 2716 // CHECK5-NEXT: [[TMP9:%.*]] = load i8, i8* [[I]], align 1 2717 // CHECK5-NEXT: [[IDXPROM6:%.*]] = zext i8 [[TMP9]] to i64 2718 // CHECK5-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[IDXPROM6]] 2719 // CHECK5-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 2720 // CHECK5-NEXT: [[MUL8:%.*]] = fmul float [[MUL]], [[TMP10]] 2721 // CHECK5-NEXT: [[TMP11:%.*]] = load float*, float** [[A_ADDR]], align 8 2722 // CHECK5-NEXT: [[TMP12:%.*]] = load i8, i8* [[I]], align 1 2723 // CHECK5-NEXT: [[IDXPROM9:%.*]] = zext i8 [[TMP12]] to i64 2724 // CHECK5-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[IDXPROM9]] 2725 // CHECK5-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4 2726 // CHECK5-NEXT: br label [[FOR_INC:%.*]] 2727 // CHECK5: for.inc: 2728 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[X]], align 4 2729 // CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP13]], 1 2730 // CHECK5-NEXT: store i32 [[INC]], i32* [[X]], align 4 2731 // CHECK5-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP7:![0-9]+]] 2732 // CHECK5: for.end: 2733 // CHECK5-NEXT: br label [[FOR_INC11:%.*]] 2734 // CHECK5: for.inc11: 2735 // CHECK5-NEXT: [[TMP14:%.*]] = load i8, i8* [[I]], align 1 2736 // CHECK5-NEXT: [[INC12:%.*]] = add i8 [[TMP14]], 1 2737 // CHECK5-NEXT: store i8 [[INC12]], i8* [[I]], align 1 2738 // CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] 2739 // CHECK5: for.end13: 2740 // CHECK5-NEXT: ret void 2741 // 2742 // 2743 // CHECK5-LABEL: define {{[^@]+}}@_Z8foo_simdii 2744 // CHECK5-SAME: (i32 [[LOW:%.*]], i32 [[UP:%.*]]) #[[ATTR0]] { 2745 // CHECK5-NEXT: entry: 2746 // CHECK5-NEXT: [[LOW_ADDR:%.*]] = alloca i32, align 4 2747 // CHECK5-NEXT: [[UP_ADDR:%.*]] = alloca i32, align 4 2748 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 2749 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 2750 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 2751 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 2752 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 2753 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2754 // CHECK5-NEXT: [[I5:%.*]] = alloca i32, align 4 2755 // CHECK5-NEXT: [[_TMP18:%.*]] = alloca i32, align 4 2756 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_19:%.*]] = alloca i32, align 4 2757 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_20:%.*]] = alloca i32, align 4 2758 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_21:%.*]] = alloca i32, align 4 2759 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2760 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2761 // CHECK5-NEXT: [[I27:%.*]] = alloca i32, align 4 2762 // CHECK5-NEXT: [[DOTOMP_IV30:%.*]] = alloca i32, align 4 2763 // CHECK5-NEXT: [[I31:%.*]] = alloca i32, align 4 2764 // CHECK5-NEXT: store i32 [[LOW]], i32* [[LOW_ADDR]], align 4 2765 // CHECK5-NEXT: store i32 [[UP]], i32* [[UP_ADDR]], align 4 2766 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[LOW_ADDR]], align 4 2767 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 2768 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[UP_ADDR]], align 4 2769 // CHECK5-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_1]], align 4 2770 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 2771 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 2772 // CHECK5-NEXT: [[SUB:%.*]] = sub i32 [[TMP2]], [[TMP3]] 2773 // CHECK5-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1 2774 // CHECK5-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1 2775 // CHECK5-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 2776 // CHECK5-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1 2777 // CHECK5-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4 2778 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 2779 // CHECK5-NEXT: store i32 [[TMP4]], i32* [[I]], align 4 2780 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 2781 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 2782 // CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], [[TMP6]] 2783 // CHECK5-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]] 2784 // CHECK5: simd.if.then: 2785 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IV]], align 4 2786 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2787 // CHECK5: omp.inner.for.cond: 2788 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 2789 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !9 2790 // CHECK5-NEXT: [[ADD6:%.*]] = add i32 [[TMP8]], 1 2791 // CHECK5-NEXT: [[CMP7:%.*]] = icmp ult i32 [[TMP7]], [[ADD6]] 2792 // CHECK5-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2793 // CHECK5: omp.inner.for.body: 2794 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !9 2795 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 2796 // CHECK5-NEXT: [[MUL:%.*]] = mul i32 [[TMP10]], 1 2797 // CHECK5-NEXT: [[ADD8:%.*]] = add i32 [[TMP9]], [[MUL]] 2798 // CHECK5-NEXT: store i32 [[ADD8]], i32* [[I5]], align 4, !llvm.access.group !9 2799 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[I5]], align 4, !llvm.access.group !9 2800 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 2801 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM]] 2802 // CHECK5-NEXT: store float 0.000000e+00, float* [[ARRAYIDX]], align 4, !llvm.access.group !9 2803 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[I5]], align 4, !llvm.access.group !9 2804 // CHECK5-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP12]] to i64 2805 // CHECK5-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM9]] 2806 // CHECK5-NEXT: store float 1.000000e+00, float* [[ARRAYIDX10]], align 4, !llvm.access.group !9 2807 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2808 // CHECK5: omp.body.continue: 2809 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2810 // CHECK5: omp.inner.for.inc: 2811 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 2812 // CHECK5-NEXT: [[ADD11:%.*]] = add i32 [[TMP13]], 1 2813 // CHECK5-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 2814 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] 2815 // CHECK5: omp.inner.for.end: 2816 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 2817 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 2818 // CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 2819 // CHECK5-NEXT: [[SUB12:%.*]] = sub i32 [[TMP15]], [[TMP16]] 2820 // CHECK5-NEXT: [[SUB13:%.*]] = sub i32 [[SUB12]], 1 2821 // CHECK5-NEXT: [[ADD14:%.*]] = add i32 [[SUB13]], 1 2822 // CHECK5-NEXT: [[DIV15:%.*]] = udiv i32 [[ADD14]], 1 2823 // CHECK5-NEXT: [[MUL16:%.*]] = mul i32 [[DIV15]], 1 2824 // CHECK5-NEXT: [[ADD17:%.*]] = add i32 [[TMP14]], [[MUL16]] 2825 // CHECK5-NEXT: store i32 [[ADD17]], i32* [[I5]], align 4 2826 // CHECK5-NEXT: br label [[SIMD_IF_END]] 2827 // CHECK5: simd.if.end: 2828 // CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[LOW_ADDR]], align 4 2829 // CHECK5-NEXT: store i32 [[TMP17]], i32* [[DOTCAPTURE_EXPR_19]], align 4 2830 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[UP_ADDR]], align 4 2831 // CHECK5-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_20]], align 4 2832 // CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_20]], align 4 2833 // CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 2834 // CHECK5-NEXT: [[SUB22:%.*]] = sub i32 [[TMP19]], [[TMP20]] 2835 // CHECK5-NEXT: [[SUB23:%.*]] = sub i32 [[SUB22]], 1 2836 // CHECK5-NEXT: [[ADD24:%.*]] = add i32 [[SUB23]], 1 2837 // CHECK5-NEXT: [[DIV25:%.*]] = udiv i32 [[ADD24]], 1 2838 // CHECK5-NEXT: [[SUB26:%.*]] = sub i32 [[DIV25]], 1 2839 // CHECK5-NEXT: store i32 [[SUB26]], i32* [[DOTCAPTURE_EXPR_21]], align 4 2840 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2841 // CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_21]], align 4 2842 // CHECK5-NEXT: store i32 [[TMP21]], i32* [[DOTOMP_UB]], align 4 2843 // CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 2844 // CHECK5-NEXT: store i32 [[TMP22]], i32* [[I27]], align 4 2845 // CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 2846 // CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_20]], align 4 2847 // CHECK5-NEXT: [[CMP28:%.*]] = icmp slt i32 [[TMP23]], [[TMP24]] 2848 // CHECK5-NEXT: br i1 [[CMP28]], label [[SIMD_IF_THEN29:%.*]], label [[SIMD_IF_END52:%.*]] 2849 // CHECK5: simd.if.then29: 2850 // CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2851 // CHECK5-NEXT: store i32 [[TMP25]], i32* [[DOTOMP_IV30]], align 4 2852 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND32:%.*]] 2853 // CHECK5: omp.inner.for.cond32: 2854 // CHECK5-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_IV30]], align 4, !llvm.access.group !13 2855 // CHECK5-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 2856 // CHECK5-NEXT: [[ADD33:%.*]] = add i32 [[TMP27]], 1 2857 // CHECK5-NEXT: [[CMP34:%.*]] = icmp ult i32 [[TMP26]], [[ADD33]] 2858 // CHECK5-NEXT: br i1 [[CMP34]], label [[OMP_INNER_FOR_BODY35:%.*]], label [[OMP_INNER_FOR_END45:%.*]] 2859 // CHECK5: omp.inner.for.body35: 2860 // CHECK5-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4, !llvm.access.group !13 2861 // CHECK5-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV30]], align 4, !llvm.access.group !13 2862 // CHECK5-NEXT: [[MUL36:%.*]] = mul i32 [[TMP29]], 1 2863 // CHECK5-NEXT: [[ADD37:%.*]] = add i32 [[TMP28]], [[MUL36]] 2864 // CHECK5-NEXT: store i32 [[ADD37]], i32* [[I31]], align 4, !llvm.access.group !13 2865 // CHECK5-NEXT: [[TMP30:%.*]] = load i32, i32* [[I31]], align 4, !llvm.access.group !13 2866 // CHECK5-NEXT: [[IDXPROM38:%.*]] = sext i32 [[TMP30]] to i64 2867 // CHECK5-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM38]] 2868 // CHECK5-NEXT: store float 0.000000e+00, float* [[ARRAYIDX39]], align 4, !llvm.access.group !13 2869 // CHECK5-NEXT: [[TMP31:%.*]] = load i32, i32* [[I31]], align 4, !llvm.access.group !13 2870 // CHECK5-NEXT: [[IDXPROM40:%.*]] = sext i32 [[TMP31]] to i64 2871 // CHECK5-NEXT: [[ARRAYIDX41:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM40]] 2872 // CHECK5-NEXT: store float 1.000000e+00, float* [[ARRAYIDX41]], align 4, !llvm.access.group !13 2873 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE42:%.*]] 2874 // CHECK5: omp.body.continue42: 2875 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC43:%.*]] 2876 // CHECK5: omp.inner.for.inc43: 2877 // CHECK5-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IV30]], align 4, !llvm.access.group !13 2878 // CHECK5-NEXT: [[ADD44:%.*]] = add i32 [[TMP32]], 1 2879 // CHECK5-NEXT: store i32 [[ADD44]], i32* [[DOTOMP_IV30]], align 4, !llvm.access.group !13 2880 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND32]], !llvm.loop [[LOOP14:![0-9]+]] 2881 // CHECK5: omp.inner.for.end45: 2882 // CHECK5-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 2883 // CHECK5-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_20]], align 4 2884 // CHECK5-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 2885 // CHECK5-NEXT: [[SUB46:%.*]] = sub i32 [[TMP34]], [[TMP35]] 2886 // CHECK5-NEXT: [[SUB47:%.*]] = sub i32 [[SUB46]], 1 2887 // CHECK5-NEXT: [[ADD48:%.*]] = add i32 [[SUB47]], 1 2888 // CHECK5-NEXT: [[DIV49:%.*]] = udiv i32 [[ADD48]], 1 2889 // CHECK5-NEXT: [[MUL50:%.*]] = mul i32 [[DIV49]], 1 2890 // CHECK5-NEXT: [[ADD51:%.*]] = add i32 [[TMP33]], [[MUL50]] 2891 // CHECK5-NEXT: store i32 [[ADD51]], i32* [[I31]], align 4 2892 // CHECK5-NEXT: br label [[SIMD_IF_END52]] 2893 // CHECK5: simd.if.end52: 2894 // CHECK5-NEXT: ret void 2895 // 2896 // 2897 // CHECK6-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 2898 // CHECK6-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0:[0-9]+]] { 2899 // CHECK6-NEXT: entry: 2900 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 2901 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 2902 // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 2903 // CHECK6-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 2904 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 2905 // CHECK6-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 2906 // CHECK6-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 2907 // CHECK6-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 2908 // CHECK6-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 2909 // CHECK6-NEXT: store i32 32000000, i32* [[I]], align 4 2910 // CHECK6-NEXT: br label [[FOR_COND:%.*]] 2911 // CHECK6: for.cond: 2912 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 2913 // CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 33 2914 // CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 2915 // CHECK6: for.body: 2916 // CHECK6-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 2917 // CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 2918 // CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 2919 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] 2920 // CHECK6-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 2921 // CHECK6-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 2922 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 2923 // CHECK6-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64 2924 // CHECK6-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] 2925 // CHECK6-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 2926 // CHECK6-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] 2927 // CHECK6-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 2928 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 2929 // CHECK6-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64 2930 // CHECK6-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] 2931 // CHECK6-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 2932 // CHECK6-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] 2933 // CHECK6-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 2934 // CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 2935 // CHECK6-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64 2936 // CHECK6-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] 2937 // CHECK6-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 2938 // CHECK6-NEXT: br label [[FOR_INC:%.*]] 2939 // CHECK6: for.inc: 2940 // CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 2941 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], -7 2942 // CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 2943 // CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] 2944 // CHECK6: for.end: 2945 // CHECK6-NEXT: ret void 2946 // 2947 // 2948 // CHECK6-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_ 2949 // CHECK6-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 2950 // CHECK6-NEXT: entry: 2951 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 2952 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 2953 // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 2954 // CHECK6-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 2955 // CHECK6-NEXT: [[I:%.*]] = alloca i64, align 8 2956 // CHECK6-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 2957 // CHECK6-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 2958 // CHECK6-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 2959 // CHECK6-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 2960 // CHECK6-NEXT: store i64 131071, i64* [[I]], align 8 2961 // CHECK6-NEXT: br label [[FOR_COND:%.*]] 2962 // CHECK6: for.cond: 2963 // CHECK6-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 2964 // CHECK6-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP0]], 2147483647 2965 // CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 2966 // CHECK6: for.body: 2967 // CHECK6-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 2968 // CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[I]], align 8 2969 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[TMP2]] 2970 // CHECK6-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 2971 // CHECK6-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 2972 // CHECK6-NEXT: [[TMP5:%.*]] = load i64, i64* [[I]], align 8 2973 // CHECK6-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[TMP5]] 2974 // CHECK6-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 2975 // CHECK6-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] 2976 // CHECK6-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 2977 // CHECK6-NEXT: [[TMP8:%.*]] = load i64, i64* [[I]], align 8 2978 // CHECK6-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[TMP8]] 2979 // CHECK6-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 2980 // CHECK6-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] 2981 // CHECK6-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 2982 // CHECK6-NEXT: [[TMP11:%.*]] = load i64, i64* [[I]], align 8 2983 // CHECK6-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[TMP11]] 2984 // CHECK6-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 2985 // CHECK6-NEXT: br label [[FOR_INC:%.*]] 2986 // CHECK6: for.inc: 2987 // CHECK6-NEXT: [[TMP12:%.*]] = load i64, i64* [[I]], align 8 2988 // CHECK6-NEXT: [[ADD:%.*]] = add i64 [[TMP12]], 127 2989 // CHECK6-NEXT: store i64 [[ADD]], i64* [[I]], align 8 2990 // CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 2991 // CHECK6: for.end: 2992 // CHECK6-NEXT: ret void 2993 // 2994 // 2995 // CHECK6-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_ 2996 // CHECK6-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 2997 // CHECK6-NEXT: entry: 2998 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 2999 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 3000 // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 3001 // CHECK6-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 3002 // CHECK6-NEXT: [[X:%.*]] = alloca i32, align 4 3003 // CHECK6-NEXT: [[Y:%.*]] = alloca i32, align 4 3004 // CHECK6-NEXT: [[I:%.*]] = alloca i8, align 1 3005 // CHECK6-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 3006 // CHECK6-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 3007 // CHECK6-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 3008 // CHECK6-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 3009 // CHECK6-NEXT: store i32 0, i32* [[X]], align 4 3010 // CHECK6-NEXT: store i32 0, i32* [[Y]], align 4 3011 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[Y]], align 4 3012 // CHECK6-NEXT: [[CONV:%.*]] = trunc i32 [[TMP0]] to i8 3013 // CHECK6-NEXT: store i8 [[CONV]], i8* [[I]], align 1 3014 // CHECK6-NEXT: br label [[FOR_COND:%.*]] 3015 // CHECK6: for.cond: 3016 // CHECK6-NEXT: [[TMP1:%.*]] = load i8, i8* [[I]], align 1 3017 // CHECK6-NEXT: [[CONV1:%.*]] = sext i8 [[TMP1]] to i32 3018 // CHECK6-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV1]], 57 3019 // CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END13:%.*]] 3020 // CHECK6: for.body: 3021 // CHECK6-NEXT: store i32 11, i32* [[X]], align 4 3022 // CHECK6-NEXT: br label [[FOR_COND2:%.*]] 3023 // CHECK6: for.cond2: 3024 // CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[X]], align 4 3025 // CHECK6-NEXT: [[CMP3:%.*]] = icmp ugt i32 [[TMP2]], 0 3026 // CHECK6-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END:%.*]] 3027 // CHECK6: for.body4: 3028 // CHECK6-NEXT: [[TMP3:%.*]] = load float*, float** [[B_ADDR]], align 8 3029 // CHECK6-NEXT: [[TMP4:%.*]] = load i8, i8* [[I]], align 1 3030 // CHECK6-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP4]] to i64 3031 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP3]], i64 [[IDXPROM]] 3032 // CHECK6-NEXT: [[TMP5:%.*]] = load float, float* [[ARRAYIDX]], align 4 3033 // CHECK6-NEXT: [[TMP6:%.*]] = load float*, float** [[C_ADDR]], align 8 3034 // CHECK6-NEXT: [[TMP7:%.*]] = load i8, i8* [[I]], align 1 3035 // CHECK6-NEXT: [[IDXPROM5:%.*]] = sext i8 [[TMP7]] to i64 3036 // CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP6]], i64 [[IDXPROM5]] 3037 // CHECK6-NEXT: [[TMP8:%.*]] = load float, float* [[ARRAYIDX6]], align 4 3038 // CHECK6-NEXT: [[MUL:%.*]] = fmul float [[TMP5]], [[TMP8]] 3039 // CHECK6-NEXT: [[TMP9:%.*]] = load float*, float** [[D_ADDR]], align 8 3040 // CHECK6-NEXT: [[TMP10:%.*]] = load i8, i8* [[I]], align 1 3041 // CHECK6-NEXT: [[IDXPROM7:%.*]] = sext i8 [[TMP10]] to i64 3042 // CHECK6-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP9]], i64 [[IDXPROM7]] 3043 // CHECK6-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX8]], align 4 3044 // CHECK6-NEXT: [[MUL9:%.*]] = fmul float [[MUL]], [[TMP11]] 3045 // CHECK6-NEXT: [[TMP12:%.*]] = load float*, float** [[A_ADDR]], align 8 3046 // CHECK6-NEXT: [[TMP13:%.*]] = load i8, i8* [[I]], align 1 3047 // CHECK6-NEXT: [[IDXPROM10:%.*]] = sext i8 [[TMP13]] to i64 3048 // CHECK6-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM10]] 3049 // CHECK6-NEXT: store float [[MUL9]], float* [[ARRAYIDX11]], align 4 3050 // CHECK6-NEXT: br label [[FOR_INC:%.*]] 3051 // CHECK6: for.inc: 3052 // CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[X]], align 4 3053 // CHECK6-NEXT: [[DEC:%.*]] = add i32 [[TMP14]], -1 3054 // CHECK6-NEXT: store i32 [[DEC]], i32* [[X]], align 4 3055 // CHECK6-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP5:![0-9]+]] 3056 // CHECK6: for.end: 3057 // CHECK6-NEXT: br label [[FOR_INC12:%.*]] 3058 // CHECK6: for.inc12: 3059 // CHECK6-NEXT: [[TMP15:%.*]] = load i8, i8* [[I]], align 1 3060 // CHECK6-NEXT: [[INC:%.*]] = add i8 [[TMP15]], 1 3061 // CHECK6-NEXT: store i8 [[INC]], i8* [[I]], align 1 3062 // CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 3063 // CHECK6: for.end13: 3064 // CHECK6-NEXT: ret void 3065 // 3066 // 3067 // CHECK6-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_ 3068 // CHECK6-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 3069 // CHECK6-NEXT: entry: 3070 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 3071 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 3072 // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 3073 // CHECK6-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 3074 // CHECK6-NEXT: [[X:%.*]] = alloca i32, align 4 3075 // CHECK6-NEXT: [[I:%.*]] = alloca i8, align 1 3076 // CHECK6-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 3077 // CHECK6-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 3078 // CHECK6-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 3079 // CHECK6-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 3080 // CHECK6-NEXT: store i32 0, i32* [[X]], align 4 3081 // CHECK6-NEXT: store i8 48, i8* [[I]], align 1 3082 // CHECK6-NEXT: br label [[FOR_COND:%.*]] 3083 // CHECK6: for.cond: 3084 // CHECK6-NEXT: [[TMP0:%.*]] = load i8, i8* [[I]], align 1 3085 // CHECK6-NEXT: [[CONV:%.*]] = zext i8 [[TMP0]] to i32 3086 // CHECK6-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV]], 57 3087 // CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END13:%.*]] 3088 // CHECK6: for.body: 3089 // CHECK6-NEXT: store i32 -10, i32* [[X]], align 4 3090 // CHECK6-NEXT: br label [[FOR_COND1:%.*]] 3091 // CHECK6: for.cond1: 3092 // CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[X]], align 4 3093 // CHECK6-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP1]], 10 3094 // CHECK6-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] 3095 // CHECK6: for.body3: 3096 // CHECK6-NEXT: [[TMP2:%.*]] = load float*, float** [[B_ADDR]], align 8 3097 // CHECK6-NEXT: [[TMP3:%.*]] = load i8, i8* [[I]], align 1 3098 // CHECK6-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP3]] to i64 3099 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 [[IDXPROM]] 3100 // CHECK6-NEXT: [[TMP4:%.*]] = load float, float* [[ARRAYIDX]], align 4 3101 // CHECK6-NEXT: [[TMP5:%.*]] = load float*, float** [[C_ADDR]], align 8 3102 // CHECK6-NEXT: [[TMP6:%.*]] = load i8, i8* [[I]], align 1 3103 // CHECK6-NEXT: [[IDXPROM4:%.*]] = zext i8 [[TMP6]] to i64 3104 // CHECK6-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP5]], i64 [[IDXPROM4]] 3105 // CHECK6-NEXT: [[TMP7:%.*]] = load float, float* [[ARRAYIDX5]], align 4 3106 // CHECK6-NEXT: [[MUL:%.*]] = fmul float [[TMP4]], [[TMP7]] 3107 // CHECK6-NEXT: [[TMP8:%.*]] = load float*, float** [[D_ADDR]], align 8 3108 // CHECK6-NEXT: [[TMP9:%.*]] = load i8, i8* [[I]], align 1 3109 // CHECK6-NEXT: [[IDXPROM6:%.*]] = zext i8 [[TMP9]] to i64 3110 // CHECK6-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[IDXPROM6]] 3111 // CHECK6-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 3112 // CHECK6-NEXT: [[MUL8:%.*]] = fmul float [[MUL]], [[TMP10]] 3113 // CHECK6-NEXT: [[TMP11:%.*]] = load float*, float** [[A_ADDR]], align 8 3114 // CHECK6-NEXT: [[TMP12:%.*]] = load i8, i8* [[I]], align 1 3115 // CHECK6-NEXT: [[IDXPROM9:%.*]] = zext i8 [[TMP12]] to i64 3116 // CHECK6-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[IDXPROM9]] 3117 // CHECK6-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4 3118 // CHECK6-NEXT: br label [[FOR_INC:%.*]] 3119 // CHECK6: for.inc: 3120 // CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[X]], align 4 3121 // CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP13]], 1 3122 // CHECK6-NEXT: store i32 [[INC]], i32* [[X]], align 4 3123 // CHECK6-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP7:![0-9]+]] 3124 // CHECK6: for.end: 3125 // CHECK6-NEXT: br label [[FOR_INC11:%.*]] 3126 // CHECK6: for.inc11: 3127 // CHECK6-NEXT: [[TMP14:%.*]] = load i8, i8* [[I]], align 1 3128 // CHECK6-NEXT: [[INC12:%.*]] = add i8 [[TMP14]], 1 3129 // CHECK6-NEXT: store i8 [[INC12]], i8* [[I]], align 1 3130 // CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] 3131 // CHECK6: for.end13: 3132 // CHECK6-NEXT: ret void 3133 // 3134 // 3135 // CHECK6-LABEL: define {{[^@]+}}@_Z8foo_simdii 3136 // CHECK6-SAME: (i32 [[LOW:%.*]], i32 [[UP:%.*]]) #[[ATTR0]] { 3137 // CHECK6-NEXT: entry: 3138 // CHECK6-NEXT: [[LOW_ADDR:%.*]] = alloca i32, align 4 3139 // CHECK6-NEXT: [[UP_ADDR:%.*]] = alloca i32, align 4 3140 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 3141 // CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 3142 // CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 3143 // CHECK6-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 3144 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 3145 // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3146 // CHECK6-NEXT: [[I5:%.*]] = alloca i32, align 4 3147 // CHECK6-NEXT: [[_TMP18:%.*]] = alloca i32, align 4 3148 // CHECK6-NEXT: [[DOTCAPTURE_EXPR_19:%.*]] = alloca i32, align 4 3149 // CHECK6-NEXT: [[DOTCAPTURE_EXPR_20:%.*]] = alloca i32, align 4 3150 // CHECK6-NEXT: [[DOTCAPTURE_EXPR_21:%.*]] = alloca i32, align 4 3151 // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3152 // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3153 // CHECK6-NEXT: [[I27:%.*]] = alloca i32, align 4 3154 // CHECK6-NEXT: [[DOTOMP_IV30:%.*]] = alloca i32, align 4 3155 // CHECK6-NEXT: [[I31:%.*]] = alloca i32, align 4 3156 // CHECK6-NEXT: store i32 [[LOW]], i32* [[LOW_ADDR]], align 4 3157 // CHECK6-NEXT: store i32 [[UP]], i32* [[UP_ADDR]], align 4 3158 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[LOW_ADDR]], align 4 3159 // CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 3160 // CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[UP_ADDR]], align 4 3161 // CHECK6-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_1]], align 4 3162 // CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 3163 // CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3164 // CHECK6-NEXT: [[SUB:%.*]] = sub i32 [[TMP2]], [[TMP3]] 3165 // CHECK6-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1 3166 // CHECK6-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1 3167 // CHECK6-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 3168 // CHECK6-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1 3169 // CHECK6-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4 3170 // CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3171 // CHECK6-NEXT: store i32 [[TMP4]], i32* [[I]], align 4 3172 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3173 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 3174 // CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP5]], [[TMP6]] 3175 // CHECK6-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]] 3176 // CHECK6: simd.if.then: 3177 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IV]], align 4 3178 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3179 // CHECK6: omp.inner.for.cond: 3180 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 3181 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !9 3182 // CHECK6-NEXT: [[ADD6:%.*]] = add i32 [[TMP8]], 1 3183 // CHECK6-NEXT: [[CMP7:%.*]] = icmp ult i32 [[TMP7]], [[ADD6]] 3184 // CHECK6-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3185 // CHECK6: omp.inner.for.body: 3186 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !9 3187 // CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 3188 // CHECK6-NEXT: [[MUL:%.*]] = mul i32 [[TMP10]], 1 3189 // CHECK6-NEXT: [[ADD8:%.*]] = add i32 [[TMP9]], [[MUL]] 3190 // CHECK6-NEXT: store i32 [[ADD8]], i32* [[I5]], align 4, !llvm.access.group !9 3191 // CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[I5]], align 4, !llvm.access.group !9 3192 // CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 3193 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM]] 3194 // CHECK6-NEXT: store float 0.000000e+00, float* [[ARRAYIDX]], align 4, !llvm.access.group !9 3195 // CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[I5]], align 4, !llvm.access.group !9 3196 // CHECK6-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP12]] to i64 3197 // CHECK6-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM9]] 3198 // CHECK6-NEXT: store float 1.000000e+00, float* [[ARRAYIDX10]], align 4, !llvm.access.group !9 3199 // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3200 // CHECK6: omp.body.continue: 3201 // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3202 // CHECK6: omp.inner.for.inc: 3203 // CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 3204 // CHECK6-NEXT: [[ADD11:%.*]] = add i32 [[TMP13]], 1 3205 // CHECK6-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9 3206 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] 3207 // CHECK6: omp.inner.for.end: 3208 // CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3209 // CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 3210 // CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3211 // CHECK6-NEXT: [[SUB12:%.*]] = sub i32 [[TMP15]], [[TMP16]] 3212 // CHECK6-NEXT: [[SUB13:%.*]] = sub i32 [[SUB12]], 1 3213 // CHECK6-NEXT: [[ADD14:%.*]] = add i32 [[SUB13]], 1 3214 // CHECK6-NEXT: [[DIV15:%.*]] = udiv i32 [[ADD14]], 1 3215 // CHECK6-NEXT: [[MUL16:%.*]] = mul i32 [[DIV15]], 1 3216 // CHECK6-NEXT: [[ADD17:%.*]] = add i32 [[TMP14]], [[MUL16]] 3217 // CHECK6-NEXT: store i32 [[ADD17]], i32* [[I5]], align 4 3218 // CHECK6-NEXT: br label [[SIMD_IF_END]] 3219 // CHECK6: simd.if.end: 3220 // CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[LOW_ADDR]], align 4 3221 // CHECK6-NEXT: store i32 [[TMP17]], i32* [[DOTCAPTURE_EXPR_19]], align 4 3222 // CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[UP_ADDR]], align 4 3223 // CHECK6-NEXT: store i32 [[TMP18]], i32* [[DOTCAPTURE_EXPR_20]], align 4 3224 // CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_20]], align 4 3225 // CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 3226 // CHECK6-NEXT: [[SUB22:%.*]] = sub i32 [[TMP19]], [[TMP20]] 3227 // CHECK6-NEXT: [[SUB23:%.*]] = sub i32 [[SUB22]], 1 3228 // CHECK6-NEXT: [[ADD24:%.*]] = add i32 [[SUB23]], 1 3229 // CHECK6-NEXT: [[DIV25:%.*]] = udiv i32 [[ADD24]], 1 3230 // CHECK6-NEXT: [[SUB26:%.*]] = sub i32 [[DIV25]], 1 3231 // CHECK6-NEXT: store i32 [[SUB26]], i32* [[DOTCAPTURE_EXPR_21]], align 4 3232 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3233 // CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_21]], align 4 3234 // CHECK6-NEXT: store i32 [[TMP21]], i32* [[DOTOMP_UB]], align 4 3235 // CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 3236 // CHECK6-NEXT: store i32 [[TMP22]], i32* [[I27]], align 4 3237 // CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 3238 // CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_20]], align 4 3239 // CHECK6-NEXT: [[CMP28:%.*]] = icmp slt i32 [[TMP23]], [[TMP24]] 3240 // CHECK6-NEXT: br i1 [[CMP28]], label [[SIMD_IF_THEN29:%.*]], label [[SIMD_IF_END52:%.*]] 3241 // CHECK6: simd.if.then29: 3242 // CHECK6-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3243 // CHECK6-NEXT: store i32 [[TMP25]], i32* [[DOTOMP_IV30]], align 4 3244 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND32:%.*]] 3245 // CHECK6: omp.inner.for.cond32: 3246 // CHECK6-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_IV30]], align 4, !llvm.access.group !13 3247 // CHECK6-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 3248 // CHECK6-NEXT: [[ADD33:%.*]] = add i32 [[TMP27]], 1 3249 // CHECK6-NEXT: [[CMP34:%.*]] = icmp ult i32 [[TMP26]], [[ADD33]] 3250 // CHECK6-NEXT: br i1 [[CMP34]], label [[OMP_INNER_FOR_BODY35:%.*]], label [[OMP_INNER_FOR_END45:%.*]] 3251 // CHECK6: omp.inner.for.body35: 3252 // CHECK6-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4, !llvm.access.group !13 3253 // CHECK6-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV30]], align 4, !llvm.access.group !13 3254 // CHECK6-NEXT: [[MUL36:%.*]] = mul i32 [[TMP29]], 1 3255 // CHECK6-NEXT: [[ADD37:%.*]] = add i32 [[TMP28]], [[MUL36]] 3256 // CHECK6-NEXT: store i32 [[ADD37]], i32* [[I31]], align 4, !llvm.access.group !13 3257 // CHECK6-NEXT: [[TMP30:%.*]] = load i32, i32* [[I31]], align 4, !llvm.access.group !13 3258 // CHECK6-NEXT: [[IDXPROM38:%.*]] = sext i32 [[TMP30]] to i64 3259 // CHECK6-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM38]] 3260 // CHECK6-NEXT: store float 0.000000e+00, float* [[ARRAYIDX39]], align 4, !llvm.access.group !13 3261 // CHECK6-NEXT: [[TMP31:%.*]] = load i32, i32* [[I31]], align 4, !llvm.access.group !13 3262 // CHECK6-NEXT: [[IDXPROM40:%.*]] = sext i32 [[TMP31]] to i64 3263 // CHECK6-NEXT: [[ARRAYIDX41:%.*]] = getelementptr inbounds [10 x float], [10 x float]* @f, i64 0, i64 [[IDXPROM40]] 3264 // CHECK6-NEXT: store float 1.000000e+00, float* [[ARRAYIDX41]], align 4, !llvm.access.group !13 3265 // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE42:%.*]] 3266 // CHECK6: omp.body.continue42: 3267 // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC43:%.*]] 3268 // CHECK6: omp.inner.for.inc43: 3269 // CHECK6-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IV30]], align 4, !llvm.access.group !13 3270 // CHECK6-NEXT: [[ADD44:%.*]] = add i32 [[TMP32]], 1 3271 // CHECK6-NEXT: store i32 [[ADD44]], i32* [[DOTOMP_IV30]], align 4, !llvm.access.group !13 3272 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND32]], !llvm.loop [[LOOP14:![0-9]+]] 3273 // CHECK6: omp.inner.for.end45: 3274 // CHECK6-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 3275 // CHECK6-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_20]], align 4 3276 // CHECK6-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_19]], align 4 3277 // CHECK6-NEXT: [[SUB46:%.*]] = sub i32 [[TMP34]], [[TMP35]] 3278 // CHECK6-NEXT: [[SUB47:%.*]] = sub i32 [[SUB46]], 1 3279 // CHECK6-NEXT: [[ADD48:%.*]] = add i32 [[SUB47]], 1 3280 // CHECK6-NEXT: [[DIV49:%.*]] = udiv i32 [[ADD48]], 1 3281 // CHECK6-NEXT: [[MUL50:%.*]] = mul i32 [[DIV49]], 1 3282 // CHECK6-NEXT: [[ADD51:%.*]] = add i32 [[TMP33]], [[MUL50]] 3283 // CHECK6-NEXT: store i32 [[ADD51]], i32* [[I31]], align 4 3284 // CHECK6-NEXT: br label [[SIMD_IF_END52]] 3285 // CHECK6: simd.if.end52: 3286 // CHECK6-NEXT: ret void 3287 // 3288