xref: /llvm-project/clang/test/OpenMP/nvptx_target_parallel_num_threads_codegen.cpp (revision c1c8cbbf5f29257d084a23a2f6c4236c40b7afb9) 
1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
2 // Test target codegen - host bc file has to be created first.
3 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc
4 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK1
5 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc
6 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK2
7 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -fexceptions -fcxx-exceptions -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK2
8 
9 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc
10 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK1
11 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc
12 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK2
13 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -fexceptions -fcxx-exceptions -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK2
14 
15 // expected-no-diagnostics
16 #ifndef HEADER
17 #define HEADER
18 
19 template<typename tx>
20 tx ftemplate(int n) {
21   tx a = 0;
22   short aa = 0;
23   tx b[10];
24 
25   #pragma omp target parallel map(tofrom: aa) num_threads(1024)
26   {
27     aa += 1;
28   }
29 
30   #pragma omp target parallel map(tofrom:a, aa, b) if(target: n>40) num_threads(n)
31   {
32     a += 1;
33     aa += 1;
34     b[2] += 1;
35   }
36 
37   return a;
38 }
39 
40 int bar(int n){
41   int a = 0;
42 
43   a += ftemplate<int>(n);
44 
45   return a;
46 }
47 
48 #endif
49 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25
50 // CHECK1-SAME: (ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {
51 // CHECK1-NEXT:  entry:
52 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca ptr, align 8
53 // CHECK1-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x ptr], align 8
54 // CHECK1-NEXT:    store ptr [[AA]], ptr [[AA_ADDR]], align 8
55 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8
56 // CHECK1-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @[[GLOB1:[0-9]+]], i8 2, i1 false)
57 // CHECK1-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
58 // CHECK1-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
59 // CHECK1:       user_code.entry:
60 // CHECK1-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
61 // CHECK1-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
62 // CHECK1-NEXT:    store ptr [[TMP0]], ptr [[TMP3]], align 8
63 // CHECK1-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP2]], i32 1, i32 1024, i32 -1, ptr @__omp_outlined__, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 1)
64 // CHECK1-NEXT:    call void @__kmpc_target_deinit(ptr @[[GLOB1]], i8 2)
65 // CHECK1-NEXT:    ret void
66 // CHECK1:       worker.exit:
67 // CHECK1-NEXT:    ret void
68 //
69 //
70 // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__
71 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] {
72 // CHECK1-NEXT:  entry:
73 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
74 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
75 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca ptr, align 8
76 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
77 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
78 // CHECK1-NEXT:    store ptr [[AA]], ptr [[AA_ADDR]], align 8
79 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8
80 // CHECK1-NEXT:    [[TMP1:%.*]] = load i16, ptr [[TMP0]], align 2
81 // CHECK1-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
82 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV]], 1
83 // CHECK1-NEXT:    [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
84 // CHECK1-NEXT:    store i16 [[CONV1]], ptr [[TMP0]], align 2
85 // CHECK1-NEXT:    ret void
86 //
87 //
88 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30
89 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
90 // CHECK1-NEXT:  entry:
91 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
92 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca ptr, align 8
93 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
94 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
95 // CHECK1-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x ptr], align 8
96 // CHECK1-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
97 // CHECK1-NEXT:    store ptr [[AA]], ptr [[AA_ADDR]], align 8
98 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
99 // CHECK1-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
100 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
101 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[AA_ADDR]], align 8
102 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8
103 // CHECK1-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_target_init(ptr @[[GLOB1]], i8 2, i1 false)
104 // CHECK1-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP3]], -1
105 // CHECK1-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
106 // CHECK1:       user_code.entry:
107 // CHECK1-NEXT:    [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
108 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
109 // CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
110 // CHECK1-NEXT:    store ptr [[TMP0]], ptr [[TMP6]], align 8
111 // CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
112 // CHECK1-NEXT:    store ptr [[TMP1]], ptr [[TMP7]], align 8
113 // CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
114 // CHECK1-NEXT:    store ptr [[TMP2]], ptr [[TMP8]], align 8
115 // CHECK1-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP4]], i32 1, i32 [[TMP5]], i32 -1, ptr @__omp_outlined__1, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 3)
116 // CHECK1-NEXT:    call void @__kmpc_target_deinit(ptr @[[GLOB1]], i8 2)
117 // CHECK1-NEXT:    ret void
118 // CHECK1:       worker.exit:
119 // CHECK1-NEXT:    ret void
120 //
121 //
122 // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1
123 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
124 // CHECK1-NEXT:  entry:
125 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
126 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
127 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
128 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca ptr, align 8
129 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
130 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
131 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
132 // CHECK1-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
133 // CHECK1-NEXT:    store ptr [[AA]], ptr [[AA_ADDR]], align 8
134 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
135 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
136 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[AA_ADDR]], align 8
137 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8
138 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP0]], align 4
139 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
140 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[TMP0]], align 4
141 // CHECK1-NEXT:    [[TMP4:%.*]] = load i16, ptr [[TMP1]], align 2
142 // CHECK1-NEXT:    [[CONV:%.*]] = sext i16 [[TMP4]] to i32
143 // CHECK1-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
144 // CHECK1-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
145 // CHECK1-NEXT:    store i16 [[CONV2]], ptr [[TMP1]], align 2
146 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP2]], i64 0, i64 2
147 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
148 // CHECK1-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP5]], 1
149 // CHECK1-NEXT:    store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4
150 // CHECK1-NEXT:    ret void
151 //
152 //
153 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25
154 // CHECK2-SAME: (ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {
155 // CHECK2-NEXT:  entry:
156 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca ptr, align 4
157 // CHECK2-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x ptr], align 4
158 // CHECK2-NEXT:    store ptr [[AA]], ptr [[AA_ADDR]], align 4
159 // CHECK2-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 4
160 // CHECK2-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @[[GLOB1:[0-9]+]], i8 2, i1 false)
161 // CHECK2-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
162 // CHECK2-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
163 // CHECK2:       user_code.entry:
164 // CHECK2-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
165 // CHECK2-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
166 // CHECK2-NEXT:    store ptr [[TMP0]], ptr [[TMP3]], align 4
167 // CHECK2-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP2]], i32 1, i32 1024, i32 -1, ptr @__omp_outlined__, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 1)
168 // CHECK2-NEXT:    call void @__kmpc_target_deinit(ptr @[[GLOB1]], i8 2)
169 // CHECK2-NEXT:    ret void
170 // CHECK2:       worker.exit:
171 // CHECK2-NEXT:    ret void
172 //
173 //
174 // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__
175 // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] {
176 // CHECK2-NEXT:  entry:
177 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
178 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
179 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca ptr, align 4
180 // CHECK2-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
181 // CHECK2-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
182 // CHECK2-NEXT:    store ptr [[AA]], ptr [[AA_ADDR]], align 4
183 // CHECK2-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 4
184 // CHECK2-NEXT:    [[TMP1:%.*]] = load i16, ptr [[TMP0]], align 2
185 // CHECK2-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
186 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV]], 1
187 // CHECK2-NEXT:    [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
188 // CHECK2-NEXT:    store i16 [[CONV1]], ptr [[TMP0]], align 2
189 // CHECK2-NEXT:    ret void
190 //
191 //
192 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30
193 // CHECK2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
194 // CHECK2-NEXT:  entry:
195 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 4
196 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca ptr, align 4
197 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
198 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
199 // CHECK2-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x ptr], align 4
200 // CHECK2-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 4
201 // CHECK2-NEXT:    store ptr [[AA]], ptr [[AA_ADDR]], align 4
202 // CHECK2-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
203 // CHECK2-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
204 // CHECK2-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4
205 // CHECK2-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[AA_ADDR]], align 4
206 // CHECK2-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 4
207 // CHECK2-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_target_init(ptr @[[GLOB1]], i8 2, i1 false)
208 // CHECK2-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP3]], -1
209 // CHECK2-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
210 // CHECK2:       user_code.entry:
211 // CHECK2-NEXT:    [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
212 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
213 // CHECK2-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
214 // CHECK2-NEXT:    store ptr [[TMP0]], ptr [[TMP6]], align 4
215 // CHECK2-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
216 // CHECK2-NEXT:    store ptr [[TMP1]], ptr [[TMP7]], align 4
217 // CHECK2-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
218 // CHECK2-NEXT:    store ptr [[TMP2]], ptr [[TMP8]], align 4
219 // CHECK2-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP4]], i32 1, i32 [[TMP5]], i32 -1, ptr @__omp_outlined__1, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 3)
220 // CHECK2-NEXT:    call void @__kmpc_target_deinit(ptr @[[GLOB1]], i8 2)
221 // CHECK2-NEXT:    ret void
222 // CHECK2:       worker.exit:
223 // CHECK2-NEXT:    ret void
224 //
225 //
226 // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1
227 // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
228 // CHECK2-NEXT:  entry:
229 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
230 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
231 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 4
232 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca ptr, align 4
233 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
234 // CHECK2-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
235 // CHECK2-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
236 // CHECK2-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 4
237 // CHECK2-NEXT:    store ptr [[AA]], ptr [[AA_ADDR]], align 4
238 // CHECK2-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
239 // CHECK2-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4
240 // CHECK2-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[AA_ADDR]], align 4
241 // CHECK2-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 4
242 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP0]], align 4
243 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
244 // CHECK2-NEXT:    store i32 [[ADD]], ptr [[TMP0]], align 4
245 // CHECK2-NEXT:    [[TMP4:%.*]] = load i16, ptr [[TMP1]], align 2
246 // CHECK2-NEXT:    [[CONV:%.*]] = sext i16 [[TMP4]] to i32
247 // CHECK2-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
248 // CHECK2-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
249 // CHECK2-NEXT:    store i16 [[CONV2]], ptr [[TMP1]], align 2
250 // CHECK2-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP2]], i32 0, i32 2
251 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
252 // CHECK2-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP5]], 1
253 // CHECK2-NEXT:    store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4
254 // CHECK2-NEXT:    ret void
255 //
256