1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // Test target codegen - host bc file has to be created first. 3 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc 4 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK1 5 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc 6 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK2 7 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -fexceptions -fcxx-exceptions -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK2 8 9 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc 10 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK1 11 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc 12 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK2 13 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-cuda-mode -fexceptions -fcxx-exceptions -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK2 14 15 // expected-no-diagnostics 16 #ifndef HEADER 17 #define HEADER 18 19 template<typename tx> 20 tx ftemplate(int n) { 21 tx a = 0; 22 short aa = 0; 23 tx b[10]; 24 25 #pragma omp target parallel map(tofrom: aa) num_threads(1024) 26 { 27 aa += 1; 28 } 29 30 #pragma omp target parallel map(tofrom:a, aa, b) if(target: n>40) num_threads(n) 31 { 32 a += 1; 33 aa += 1; 34 b[2] += 1; 35 } 36 37 return a; 38 } 39 40 int bar(int n){ 41 int a = 0; 42 43 a += ftemplate<int>(n); 44 45 return a; 46 } 47 48 #endif 49 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25 50 // CHECK1-SAME: (i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] { 51 // CHECK1-NEXT: entry: 52 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8 53 // CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 8 54 // CHECK1-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8 55 // CHECK1-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 8 56 // CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 true) 57 // CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 58 // CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] 59 // CHECK1: user_code.entry: 60 // CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 61 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0 62 // CHECK1-NEXT: [[TMP4:%.*]] = bitcast i16* [[TMP0]] to i8* 63 // CHECK1-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 8 64 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** 65 // CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 1024, i32 -1, i8* bitcast (void (i32*, i32*, i16*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP5]], i64 1) 66 // CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true) 67 // CHECK1-NEXT: ret void 68 // CHECK1: worker.exit: 69 // CHECK1-NEXT: ret void 70 // 71 // 72 // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__ 73 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] { 74 // CHECK1-NEXT: entry: 75 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 76 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 77 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8 78 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 79 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 80 // CHECK1-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8 81 // CHECK1-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 8 82 // CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2 83 // CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 84 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 85 // CHECK1-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16 86 // CHECK1-NEXT: store i16 [[CONV1]], i16* [[TMP0]], align 2 87 // CHECK1-NEXT: ret void 88 // 89 // 90 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30 91 // CHECK1-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 92 // CHECK1-NEXT: entry: 93 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 94 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8 95 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 96 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 97 // CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x i8*], align 8 98 // CHECK1-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 99 // CHECK1-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8 100 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 101 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 102 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8 103 // CHECK1-NEXT: [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 8 104 // CHECK1-NEXT: [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 105 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 106 // CHECK1-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 2, i1 false, i1 true) 107 // CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP3]], -1 108 // CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] 109 // CHECK1: user_code.entry: 110 // CHECK1-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) 111 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV]], align 4 112 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0 113 // CHECK1-NEXT: [[TMP7:%.*]] = bitcast i32* [[TMP0]] to i8* 114 // CHECK1-NEXT: store i8* [[TMP7]], i8** [[TMP6]], align 8 115 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 1 116 // CHECK1-NEXT: [[TMP9:%.*]] = bitcast i16* [[TMP1]] to i8* 117 // CHECK1-NEXT: store i8* [[TMP9]], i8** [[TMP8]], align 8 118 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 2 119 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast [10 x i32]* [[TMP2]] to i8* 120 // CHECK1-NEXT: store i8* [[TMP11]], i8** [[TMP10]], align 8 121 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast [3 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** 122 // CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 1, i32 [[TMP5]], i32 -1, i8* bitcast (void (i32*, i32*, i32*, i16*, [10 x i32]*)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP12]], i64 3) 123 // CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true) 124 // CHECK1-NEXT: ret void 125 // CHECK1: worker.exit: 126 // CHECK1-NEXT: ret void 127 // 128 // 129 // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1 130 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 131 // CHECK1-NEXT: entry: 132 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 133 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 134 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 135 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 8 136 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 137 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 138 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 139 // CHECK1-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 140 // CHECK1-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 8 141 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 142 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 8 143 // CHECK1-NEXT: [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 8 144 // CHECK1-NEXT: [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 145 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 146 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 147 // CHECK1-NEXT: store i32 [[ADD]], i32* [[TMP0]], align 4 148 // CHECK1-NEXT: [[TMP4:%.*]] = load i16, i16* [[TMP1]], align 2 149 // CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32 150 // CHECK1-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 151 // CHECK1-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 152 // CHECK1-NEXT: store i16 [[CONV2]], i16* [[TMP1]], align 2 153 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP2]], i64 0, i64 2 154 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 155 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP5]], 1 156 // CHECK1-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 157 // CHECK1-NEXT: ret void 158 // 159 // 160 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l25 161 // CHECK2-SAME: (i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR0:[0-9]+]] { 162 // CHECK2-NEXT: entry: 163 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 164 // CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 4 165 // CHECK2-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4 166 // CHECK2-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4 167 // CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i8 2, i1 false, i1 true) 168 // CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 169 // CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] 170 // CHECK2: user_code.entry: 171 // CHECK2-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 172 // CHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0 173 // CHECK2-NEXT: [[TMP4:%.*]] = bitcast i16* [[TMP0]] to i8* 174 // CHECK2-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 4 175 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** 176 // CHECK2-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 1024, i32 -1, i8* bitcast (void (i32*, i32*, i16*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP5]], i32 1) 177 // CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true) 178 // CHECK2-NEXT: ret void 179 // CHECK2: worker.exit: 180 // CHECK2-NEXT: ret void 181 // 182 // 183 // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__ 184 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]]) #[[ATTR1:[0-9]+]] { 185 // CHECK2-NEXT: entry: 186 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 187 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 188 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 189 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 190 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 191 // CHECK2-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4 192 // CHECK2-NEXT: [[TMP0:%.*]] = load i16*, i16** [[AA_ADDR]], align 4 193 // CHECK2-NEXT: [[TMP1:%.*]] = load i16, i16* [[TMP0]], align 2 194 // CHECK2-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 195 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 196 // CHECK2-NEXT: [[CONV1:%.*]] = trunc i32 [[ADD]] to i16 197 // CHECK2-NEXT: store i16 [[CONV1]], i16* [[TMP0]], align 2 198 // CHECK2-NEXT: ret void 199 // 200 // 201 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l30 202 // CHECK2-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 203 // CHECK2-NEXT: entry: 204 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 205 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 206 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 207 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 208 // CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x i8*], align 4 209 // CHECK2-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 210 // CHECK2-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4 211 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 212 // CHECK2-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 213 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4 214 // CHECK2-NEXT: [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 4 215 // CHECK2-NEXT: [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 216 // CHECK2-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 2, i1 false, i1 true) 217 // CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP3]], -1 218 // CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] 219 // CHECK2: user_code.entry: 220 // CHECK2-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) 221 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 222 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0 223 // CHECK2-NEXT: [[TMP7:%.*]] = bitcast i32* [[TMP0]] to i8* 224 // CHECK2-NEXT: store i8* [[TMP7]], i8** [[TMP6]], align 4 225 // CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 1 226 // CHECK2-NEXT: [[TMP9:%.*]] = bitcast i16* [[TMP1]] to i8* 227 // CHECK2-NEXT: store i8* [[TMP9]], i8** [[TMP8]], align 4 228 // CHECK2-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 2 229 // CHECK2-NEXT: [[TMP11:%.*]] = bitcast [10 x i32]* [[TMP2]] to i8* 230 // CHECK2-NEXT: store i8* [[TMP11]], i8** [[TMP10]], align 4 231 // CHECK2-NEXT: [[TMP12:%.*]] = bitcast [3 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8** 232 // CHECK2-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP4]], i32 1, i32 [[TMP5]], i32 -1, i8* bitcast (void (i32*, i32*, i32*, i16*, [10 x i32]*)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP12]], i32 3) 233 // CHECK2-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 2, i1 true) 234 // CHECK2-NEXT: ret void 235 // CHECK2: worker.exit: 236 // CHECK2-NEXT: ret void 237 // 238 // 239 // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1 240 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 241 // CHECK2-NEXT: entry: 242 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 243 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 244 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 245 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i16*, align 4 246 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 247 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 248 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 249 // CHECK2-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 250 // CHECK2-NEXT: store i16* [[AA]], i16** [[AA_ADDR]], align 4 251 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 252 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A_ADDR]], align 4 253 // CHECK2-NEXT: [[TMP1:%.*]] = load i16*, i16** [[AA_ADDR]], align 4 254 // CHECK2-NEXT: [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 255 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 256 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 257 // CHECK2-NEXT: store i32 [[ADD]], i32* [[TMP0]], align 4 258 // CHECK2-NEXT: [[TMP4:%.*]] = load i16, i16* [[TMP1]], align 2 259 // CHECK2-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32 260 // CHECK2-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 261 // CHECK2-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 262 // CHECK2-NEXT: store i16 [[CONV2]], i16* [[TMP1]], align 2 263 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP2]], i32 0, i32 2 264 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 265 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP5]], 1 266 // CHECK2-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 267 // CHECK2-NEXT: ret void 268 // 269