1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
2 // RUN: %clang_cc1 -triple riscv32 -target-feature +xtheadbb -emit-llvm %s -o - \
3 // RUN: -disable-O0-optnone | opt -S -passes=mem2reg \
4 // RUN: | FileCheck %s -check-prefix=RV32XTHEADBB
5
6 // RV32XTHEADBB-LABEL: @clz_32(
7 // RV32XTHEADBB-NEXT: entry:
8 // RV32XTHEADBB-NEXT: [[TMP0:%.*]] = call i32 @llvm.ctlz.i32(i32 [[A:%.*]], i1 false)
9 // RV32XTHEADBB-NEXT: ret i32 [[TMP0]]
10 //
clz_32(unsigned int a)11 unsigned int clz_32(unsigned int a) {
12 return __builtin_riscv_clz_32(a);
13 }
14
15 // RV32XTHEADBB-LABEL: @clo_32(
16 // RV32XTHEADBB-NEXT: entry:
17 // RV32XTHEADBB-NEXT: [[NOT:%.*]] = xor i32 [[A:%.*]], -1
18 // RV32XTHEADBB-NEXT: [[TMP0:%.*]] = call i32 @llvm.ctlz.i32(i32 [[NOT]], i1 false)
19 // RV32XTHEADBB-NEXT: ret i32 [[TMP0]]
20 //
clo_32(unsigned int a)21 unsigned int clo_32(unsigned int a) {
22 return __builtin_riscv_clz_32(~a);
23 }
24