1 //===--- RISCV.h - Declare RISC-V target feature support --------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file declares RISC-V TargetInfo objects. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_CLANG_LIB_BASIC_TARGETS_RISCV_H 14 #define LLVM_CLANG_LIB_BASIC_TARGETS_RISCV_H 15 16 #include "clang/Basic/TargetInfo.h" 17 #include "clang/Basic/TargetOptions.h" 18 #include "llvm/Support/Compiler.h" 19 #include "llvm/TargetParser/RISCVISAInfo.h" 20 #include "llvm/TargetParser/Triple.h" 21 #include <optional> 22 23 namespace clang { 24 namespace targets { 25 26 // RISC-V Target 27 class RISCVTargetInfo : public TargetInfo { 28 protected: 29 std::string ABI, CPU; 30 std::unique_ptr<llvm::RISCVISAInfo> ISAInfo; 31 32 private: 33 bool FastScalarUnalignedAccess; 34 bool HasExperimental = false; 35 36 public: 37 RISCVTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 38 : TargetInfo(Triple) { 39 BFloat16Width = 16; 40 BFloat16Align = 16; 41 BFloat16Format = &llvm::APFloat::BFloat(); 42 LongDoubleWidth = 128; 43 LongDoubleAlign = 128; 44 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 45 SuitableAlign = 128; 46 WCharType = SignedInt; 47 WIntType = UnsignedInt; 48 HasRISCVVTypes = true; 49 MCountName = "_mcount"; 50 HasFloat16 = true; 51 HasStrictFP = true; 52 } 53 54 bool setCPU(const std::string &Name) override { 55 if (!isValidCPUName(Name)) 56 return false; 57 CPU = Name; 58 return true; 59 } 60 61 StringRef getABI() const override { return ABI; } 62 void getTargetDefines(const LangOptions &Opts, 63 MacroBuilder &Builder) const override; 64 65 ArrayRef<Builtin::Info> getTargetBuiltins() const override; 66 67 BuiltinVaListKind getBuiltinVaListKind() const override { 68 return TargetInfo::VoidPtrBuiltinVaList; 69 } 70 71 std::string_view getClobbers() const override { return ""; } 72 73 StringRef getConstraintRegister(StringRef Constraint, 74 StringRef Expression) const override { 75 return Expression; 76 } 77 78 ArrayRef<const char *> getGCCRegNames() const override; 79 80 int getEHDataRegisterNumber(unsigned RegNo) const override { 81 if (RegNo == 0) 82 return 10; 83 else if (RegNo == 1) 84 return 11; 85 else 86 return -1; 87 } 88 89 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 90 91 bool validateAsmConstraint(const char *&Name, 92 TargetInfo::ConstraintInfo &Info) const override; 93 94 std::string convertConstraint(const char *&Constraint) const override; 95 96 bool 97 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 98 StringRef CPU, 99 const std::vector<std::string> &FeaturesVec) const override; 100 101 std::optional<std::pair<unsigned, unsigned>> 102 getVScaleRange(const LangOptions &LangOpts) const override; 103 104 bool hasFeature(StringRef Feature) const override; 105 106 bool handleTargetFeatures(std::vector<std::string> &Features, 107 DiagnosticsEngine &Diags) override; 108 109 bool hasBitIntType() const override { return true; } 110 111 bool hasBFloat16Type() const override { return true; } 112 113 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override; 114 115 bool useFP16ConversionIntrinsics() const override { 116 return false; 117 } 118 119 bool isValidCPUName(StringRef Name) const override; 120 void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override; 121 bool isValidTuneCPUName(StringRef Name) const override; 122 void fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const override; 123 bool supportsTargetAttributeTune() const override { return true; } 124 ParsedTargetAttr parseTargetAttr(StringRef Str) const override; 125 126 std::pair<unsigned, unsigned> hardwareInterferenceSizes() const override { 127 return std::make_pair(32, 32); 128 } 129 130 bool supportsCpuSupports() const override { return getTriple().isOSLinux(); } 131 bool supportsCpuIs() const override { return getTriple().isOSLinux(); } 132 bool supportsCpuInit() const override { return getTriple().isOSLinux(); } 133 bool validateCpuSupports(StringRef Feature) const override; 134 bool validateCpuIs(StringRef CPUName) const override; 135 bool isValidFeatureName(StringRef Name) const override; 136 137 bool validateGlobalRegisterVariable(StringRef RegName, unsigned RegSize, 138 bool &HasSizeMismatch) const override; 139 140 bool checkCFProtectionBranchSupported(DiagnosticsEngine &) const override { 141 // Always generate Zicfilp lpad insns 142 // Non-zicfilp CPUs would read them as NOP 143 return true; 144 } 145 146 bool 147 checkCFProtectionReturnSupported(DiagnosticsEngine &Diags) const override { 148 if (ISAInfo->hasExtension("zicfiss")) 149 return true; 150 return TargetInfo::checkCFProtectionReturnSupported(Diags); 151 } 152 153 CFBranchLabelSchemeKind getDefaultCFBranchLabelScheme() const override { 154 return CFBranchLabelSchemeKind::FuncSig; 155 } 156 157 bool 158 checkCFBranchLabelSchemeSupported(const CFBranchLabelSchemeKind Scheme, 159 DiagnosticsEngine &Diags) const override { 160 switch (Scheme) { 161 case CFBranchLabelSchemeKind::Default: 162 case CFBranchLabelSchemeKind::Unlabeled: 163 case CFBranchLabelSchemeKind::FuncSig: 164 return true; 165 } 166 return TargetInfo::checkCFBranchLabelSchemeSupported(Scheme, Diags); 167 } 168 }; 169 class LLVM_LIBRARY_VISIBILITY RISCV32TargetInfo : public RISCVTargetInfo { 170 public: 171 RISCV32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 172 : RISCVTargetInfo(Triple, Opts) { 173 IntPtrType = SignedInt; 174 PtrDiffType = SignedInt; 175 SizeType = UnsignedInt; 176 resetDataLayout("e-m:e-p:32:32-i64:64-n32-S128"); 177 } 178 179 bool setABI(const std::string &Name) override { 180 if (Name == "ilp32e") { 181 ABI = Name; 182 resetDataLayout("e-m:e-p:32:32-i64:64-n32-S32"); 183 return true; 184 } 185 186 if (Name == "ilp32" || Name == "ilp32f" || Name == "ilp32d") { 187 ABI = Name; 188 return true; 189 } 190 return false; 191 } 192 193 void setMaxAtomicWidth() override { 194 MaxAtomicPromoteWidth = 128; 195 196 if (ISAInfo->hasExtension("a")) 197 MaxAtomicInlineWidth = 32; 198 } 199 }; 200 class LLVM_LIBRARY_VISIBILITY RISCV64TargetInfo : public RISCVTargetInfo { 201 public: 202 RISCV64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 203 : RISCVTargetInfo(Triple, Opts) { 204 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 205 IntMaxType = Int64Type = SignedLong; 206 resetDataLayout("e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"); 207 } 208 209 bool setABI(const std::string &Name) override { 210 if (Name == "lp64e") { 211 ABI = Name; 212 resetDataLayout("e-m:e-p:64:64-i64:64-i128:128-n32:64-S64"); 213 return true; 214 } 215 216 if (Name == "lp64" || Name == "lp64f" || Name == "lp64d") { 217 ABI = Name; 218 return true; 219 } 220 return false; 221 } 222 223 void setMaxAtomicWidth() override { 224 MaxAtomicPromoteWidth = 128; 225 226 if (ISAInfo->hasExtension("a")) 227 MaxAtomicInlineWidth = 64; 228 } 229 }; 230 } // namespace targets 231 } // namespace clang 232 233 #endif // LLVM_CLANG_LIB_BASIC_TARGETS_RISCV_H 234