1 //===- bolt/Target/X86/X86MCPlusBuilder.cpp -------------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file provides X86-specific MCPlus builder. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "MCTargetDesc/X86BaseInfo.h" 14 #include "MCTargetDesc/X86MCTargetDesc.h" 15 #include "bolt/Core/MCPlusBuilder.h" 16 #include "llvm/MC/MCContext.h" 17 #include "llvm/MC/MCFixupKindInfo.h" 18 #include "llvm/MC/MCInstBuilder.h" 19 #include "llvm/MC/MCInstrInfo.h" 20 #include "llvm/MC/MCRegisterInfo.h" 21 #include "llvm/Support/DataExtractor.h" 22 #include "llvm/Support/Debug.h" 23 #include "llvm/Support/Errc.h" 24 #include "llvm/Support/ErrorHandling.h" 25 #include "llvm/Support/ErrorOr.h" 26 #include <set> 27 28 #define DEBUG_TYPE "bolt-x86" 29 30 using namespace llvm; 31 using namespace bolt; 32 33 namespace { 34 35 unsigned getShortBranchOpcode(unsigned Opcode) { 36 switch (Opcode) { 37 default: 38 return Opcode; 39 case X86::JMP_2: return X86::JMP_1; 40 case X86::JMP_4: return X86::JMP_1; 41 case X86::JCC_2: return X86::JCC_1; 42 case X86::JCC_4: return X86::JCC_1; 43 } 44 } 45 46 unsigned getShortArithOpcode(unsigned Opcode) { 47 switch (Opcode) { 48 default: 49 return Opcode; 50 51 // IMUL 52 case X86::IMUL16rri: return X86::IMUL16rri8; 53 case X86::IMUL16rmi: return X86::IMUL16rmi8; 54 case X86::IMUL32rri: return X86::IMUL32rri8; 55 case X86::IMUL32rmi: return X86::IMUL32rmi8; 56 case X86::IMUL64rri32: return X86::IMUL64rri8; 57 case X86::IMUL64rmi32: return X86::IMUL64rmi8; 58 59 // OR 60 case X86::OR16ri: return X86::OR16ri8; 61 case X86::OR16mi: return X86::OR16mi8; 62 case X86::OR32ri: return X86::OR32ri8; 63 case X86::OR32mi: return X86::OR32mi8; 64 case X86::OR64ri32: return X86::OR64ri8; 65 case X86::OR64mi32: return X86::OR64mi8; 66 67 // AND 68 case X86::AND16ri: return X86::AND16ri8; 69 case X86::AND16mi: return X86::AND16mi8; 70 case X86::AND32ri: return X86::AND32ri8; 71 case X86::AND32mi: return X86::AND32mi8; 72 case X86::AND64ri32: return X86::AND64ri8; 73 case X86::AND64mi32: return X86::AND64mi8; 74 75 // XOR 76 case X86::XOR16ri: return X86::XOR16ri8; 77 case X86::XOR16mi: return X86::XOR16mi8; 78 case X86::XOR32ri: return X86::XOR32ri8; 79 case X86::XOR32mi: return X86::XOR32mi8; 80 case X86::XOR64ri32: return X86::XOR64ri8; 81 case X86::XOR64mi32: return X86::XOR64mi8; 82 83 // ADD 84 case X86::ADD16ri: return X86::ADD16ri8; 85 case X86::ADD16mi: return X86::ADD16mi8; 86 case X86::ADD32ri: return X86::ADD32ri8; 87 case X86::ADD32mi: return X86::ADD32mi8; 88 case X86::ADD64ri32: return X86::ADD64ri8; 89 case X86::ADD64mi32: return X86::ADD64mi8; 90 91 // SUB 92 case X86::SUB16ri: return X86::SUB16ri8; 93 case X86::SUB16mi: return X86::SUB16mi8; 94 case X86::SUB32ri: return X86::SUB32ri8; 95 case X86::SUB32mi: return X86::SUB32mi8; 96 case X86::SUB64ri32: return X86::SUB64ri8; 97 case X86::SUB64mi32: return X86::SUB64mi8; 98 99 // CMP 100 case X86::CMP16ri: return X86::CMP16ri8; 101 case X86::CMP16mi: return X86::CMP16mi8; 102 case X86::CMP32ri: return X86::CMP32ri8; 103 case X86::CMP32mi: return X86::CMP32mi8; 104 case X86::CMP64ri32: return X86::CMP64ri8; 105 case X86::CMP64mi32: return X86::CMP64mi8; 106 107 // PUSH 108 case X86::PUSHi32: return X86::PUSH32i8; 109 case X86::PUSHi16: return X86::PUSH16i8; 110 case X86::PUSH64i32: return X86::PUSH64i8; 111 } 112 } 113 114 bool isADD(unsigned Opcode) { 115 switch (Opcode) { 116 default: 117 return false; 118 case X86::ADD16i16: 119 case X86::ADD16mi: 120 case X86::ADD16mi8: 121 case X86::ADD16mr: 122 case X86::ADD16ri: 123 case X86::ADD16ri8: 124 case X86::ADD16ri8_DB: 125 case X86::ADD16ri_DB: 126 case X86::ADD16rm: 127 case X86::ADD16rr: 128 case X86::ADD16rr_DB: 129 case X86::ADD16rr_REV: 130 case X86::ADD32i32: 131 case X86::ADD32mi: 132 case X86::ADD32mi8: 133 case X86::ADD32mr: 134 case X86::ADD32ri: 135 case X86::ADD32ri8: 136 case X86::ADD32ri8_DB: 137 case X86::ADD32ri_DB: 138 case X86::ADD32rm: 139 case X86::ADD32rr: 140 case X86::ADD32rr_DB: 141 case X86::ADD32rr_REV: 142 case X86::ADD64i32: 143 case X86::ADD64mi32: 144 case X86::ADD64mi8: 145 case X86::ADD64mr: 146 case X86::ADD64ri32: 147 case X86::ADD64ri32_DB: 148 case X86::ADD64ri8: 149 case X86::ADD64ri8_DB: 150 case X86::ADD64rm: 151 case X86::ADD64rr: 152 case X86::ADD64rr_DB: 153 case X86::ADD64rr_REV: 154 case X86::ADD8i8: 155 case X86::ADD8mi: 156 case X86::ADD8mi8: 157 case X86::ADD8mr: 158 case X86::ADD8ri: 159 case X86::ADD8ri8: 160 case X86::ADD8rm: 161 case X86::ADD8rr: 162 case X86::ADD8rr_REV: 163 return true; 164 } 165 } 166 167 bool isAND(unsigned Opcode) { 168 switch (Opcode) { 169 default: 170 return false; 171 case X86::AND16i16: 172 case X86::AND16mi: 173 case X86::AND16mi8: 174 case X86::AND16mr: 175 case X86::AND16ri: 176 case X86::AND16ri8: 177 case X86::AND16rm: 178 case X86::AND16rr: 179 case X86::AND16rr_REV: 180 case X86::AND32i32: 181 case X86::AND32mi: 182 case X86::AND32mi8: 183 case X86::AND32mr: 184 case X86::AND32ri: 185 case X86::AND32ri8: 186 case X86::AND32rm: 187 case X86::AND32rr: 188 case X86::AND32rr_REV: 189 case X86::AND64i32: 190 case X86::AND64mi32: 191 case X86::AND64mi8: 192 case X86::AND64mr: 193 case X86::AND64ri32: 194 case X86::AND64ri8: 195 case X86::AND64rm: 196 case X86::AND64rr: 197 case X86::AND64rr_REV: 198 case X86::AND8i8: 199 case X86::AND8mi: 200 case X86::AND8mi8: 201 case X86::AND8mr: 202 case X86::AND8ri: 203 case X86::AND8ri8: 204 case X86::AND8rm: 205 case X86::AND8rr: 206 case X86::AND8rr_REV: 207 return true; 208 } 209 } 210 211 bool isCMP(unsigned Opcode) { 212 switch (Opcode) { 213 default: 214 return false; 215 case X86::CMP16i16: 216 case X86::CMP16mi: 217 case X86::CMP16mi8: 218 case X86::CMP16mr: 219 case X86::CMP16ri: 220 case X86::CMP16ri8: 221 case X86::CMP16rm: 222 case X86::CMP16rr: 223 case X86::CMP16rr_REV: 224 case X86::CMP32i32: 225 case X86::CMP32mi: 226 case X86::CMP32mi8: 227 case X86::CMP32mr: 228 case X86::CMP32ri: 229 case X86::CMP32ri8: 230 case X86::CMP32rm: 231 case X86::CMP32rr: 232 case X86::CMP32rr_REV: 233 case X86::CMP64i32: 234 case X86::CMP64mi32: 235 case X86::CMP64mi8: 236 case X86::CMP64mr: 237 case X86::CMP64ri32: 238 case X86::CMP64ri8: 239 case X86::CMP64rm: 240 case X86::CMP64rr: 241 case X86::CMP64rr_REV: 242 case X86::CMP8i8: 243 case X86::CMP8mi: 244 case X86::CMP8mi8: 245 case X86::CMP8mr: 246 case X86::CMP8ri: 247 case X86::CMP8ri8: 248 case X86::CMP8rm: 249 case X86::CMP8rr: 250 case X86::CMP8rr_REV: 251 return true; 252 } 253 } 254 255 bool isDEC(unsigned Opcode) { 256 switch (Opcode) { 257 default: 258 return false; 259 case X86::DEC16m: 260 case X86::DEC16r: 261 case X86::DEC16r_alt: 262 case X86::DEC32m: 263 case X86::DEC32r: 264 case X86::DEC32r_alt: 265 case X86::DEC64r: 266 case X86::DEC64m: 267 case X86::DEC8m: 268 case X86::DEC8r: 269 return true; 270 } 271 } 272 273 bool isINC(unsigned Opcode) { 274 switch (Opcode) { 275 default: 276 return false; 277 case X86::INC16m: 278 case X86::INC16r: 279 case X86::INC16r_alt: 280 case X86::INC32m: 281 case X86::INC32r: 282 case X86::INC32r_alt: 283 case X86::INC64r: 284 case X86::INC64m: 285 case X86::INC8m: 286 case X86::INC8r: 287 return true; 288 } 289 } 290 291 bool isSUB(unsigned Opcode) { 292 switch (Opcode) { 293 default: 294 return false; 295 case X86::SUB16i16: 296 case X86::SUB16mi: 297 case X86::SUB16mi8: 298 case X86::SUB16mr: 299 case X86::SUB16ri: 300 case X86::SUB16ri8: 301 case X86::SUB16rm: 302 case X86::SUB16rr: 303 case X86::SUB16rr_REV: 304 case X86::SUB32i32: 305 case X86::SUB32mi: 306 case X86::SUB32mi8: 307 case X86::SUB32mr: 308 case X86::SUB32ri: 309 case X86::SUB32ri8: 310 case X86::SUB32rm: 311 case X86::SUB32rr: 312 case X86::SUB32rr_REV: 313 case X86::SUB64i32: 314 case X86::SUB64mi32: 315 case X86::SUB64mi8: 316 case X86::SUB64mr: 317 case X86::SUB64ri32: 318 case X86::SUB64ri8: 319 case X86::SUB64rm: 320 case X86::SUB64rr: 321 case X86::SUB64rr_REV: 322 case X86::SUB8i8: 323 case X86::SUB8mi: 324 case X86::SUB8mi8: 325 case X86::SUB8mr: 326 case X86::SUB8ri: 327 case X86::SUB8ri8: 328 case X86::SUB8rm: 329 case X86::SUB8rr: 330 case X86::SUB8rr_REV: 331 return true; 332 } 333 } 334 335 bool isTEST(unsigned Opcode) { 336 switch (Opcode) { 337 default: 338 return false; 339 case X86::TEST16i16: 340 case X86::TEST16mi: 341 case X86::TEST16mr: 342 case X86::TEST16ri: 343 case X86::TEST16rr: 344 case X86::TEST32i32: 345 case X86::TEST32mi: 346 case X86::TEST32mr: 347 case X86::TEST32ri: 348 case X86::TEST32rr: 349 case X86::TEST64i32: 350 case X86::TEST64mi32: 351 case X86::TEST64mr: 352 case X86::TEST64ri32: 353 case X86::TEST64rr: 354 case X86::TEST8i8: 355 case X86::TEST8mi: 356 case X86::TEST8mr: 357 case X86::TEST8ri: 358 case X86::TEST8rr: 359 return true; 360 } 361 } 362 363 class X86MCPlusBuilder : public MCPlusBuilder { 364 public: 365 X86MCPlusBuilder(const MCInstrAnalysis *Analysis, const MCInstrInfo *Info, 366 const MCRegisterInfo *RegInfo) 367 : MCPlusBuilder(Analysis, Info, RegInfo) {} 368 369 bool isBranch(const MCInst &Inst) const override { 370 return Analysis->isBranch(Inst) && !isTailCall(Inst); 371 } 372 373 bool isUnconditionalBranch(const MCInst &Inst) const override { 374 return Analysis->isUnconditionalBranch(Inst) && !isTailCall(Inst); 375 } 376 377 bool isNoop(const MCInst &Inst) const override { 378 switch (Inst.getOpcode()) { 379 case X86::NOOP: 380 case X86::NOOPL: 381 case X86::NOOPLr: 382 case X86::NOOPQ: 383 case X86::NOOPQr: 384 case X86::NOOPW: 385 case X86::NOOPWr: 386 return true; 387 } 388 return false; 389 } 390 391 unsigned getCondCode(const MCInst &Inst) const override { 392 switch (Inst.getOpcode()) { 393 default: 394 return X86::COND_INVALID; 395 case X86::JCC_1: 396 case X86::JCC_2: 397 case X86::JCC_4: 398 return Inst.getOperand(Info->get(Inst.getOpcode()).NumOperands - 1) 399 .getImm(); 400 } 401 } 402 403 unsigned getInvertedCondCode(unsigned CC) const override { 404 switch (CC) { 405 default: return X86::COND_INVALID; 406 case X86::COND_E: return X86::COND_NE; 407 case X86::COND_NE: return X86::COND_E; 408 case X86::COND_L: return X86::COND_GE; 409 case X86::COND_LE: return X86::COND_G; 410 case X86::COND_G: return X86::COND_LE; 411 case X86::COND_GE: return X86::COND_L; 412 case X86::COND_B: return X86::COND_AE; 413 case X86::COND_BE: return X86::COND_A; 414 case X86::COND_A: return X86::COND_BE; 415 case X86::COND_AE: return X86::COND_B; 416 case X86::COND_S: return X86::COND_NS; 417 case X86::COND_NS: return X86::COND_S; 418 case X86::COND_P: return X86::COND_NP; 419 case X86::COND_NP: return X86::COND_P; 420 case X86::COND_O: return X86::COND_NO; 421 case X86::COND_NO: return X86::COND_O; 422 } 423 } 424 425 unsigned getCondCodesLogicalOr(unsigned CC1, unsigned CC2) const override { 426 enum DecodedCondCode : uint8_t { 427 DCC_EQUAL = 0x1, 428 DCC_GREATER = 0x2, 429 DCC_LESSER = 0x4, 430 DCC_GREATER_OR_LESSER = 0x6, 431 DCC_UNSIGNED = 0x8, 432 DCC_SIGNED = 0x10, 433 DCC_INVALID = 0x20, 434 }; 435 436 auto decodeCondCode = [&](unsigned CC) -> uint8_t { 437 switch (CC) { 438 default: return DCC_INVALID; 439 case X86::COND_E: return DCC_EQUAL; 440 case X86::COND_NE: return DCC_GREATER | DCC_LESSER; 441 case X86::COND_L: return DCC_LESSER | DCC_SIGNED; 442 case X86::COND_LE: return DCC_EQUAL | DCC_LESSER | DCC_SIGNED; 443 case X86::COND_G: return DCC_GREATER | DCC_SIGNED; 444 case X86::COND_GE: return DCC_GREATER | DCC_EQUAL | DCC_SIGNED; 445 case X86::COND_B: return DCC_LESSER | DCC_UNSIGNED; 446 case X86::COND_BE: return DCC_EQUAL | DCC_LESSER | DCC_UNSIGNED; 447 case X86::COND_A: return DCC_GREATER | DCC_UNSIGNED; 448 case X86::COND_AE: return DCC_GREATER | DCC_EQUAL | DCC_UNSIGNED; 449 } 450 }; 451 452 uint8_t DCC = decodeCondCode(CC1) | decodeCondCode(CC2); 453 454 if (DCC & DCC_INVALID) 455 return X86::COND_INVALID; 456 457 if (DCC & DCC_SIGNED && DCC & DCC_UNSIGNED) 458 return X86::COND_INVALID; 459 460 switch (DCC) { 461 default: return X86::COND_INVALID; 462 case DCC_EQUAL | DCC_LESSER | DCC_SIGNED: return X86::COND_LE; 463 case DCC_EQUAL | DCC_LESSER | DCC_UNSIGNED: return X86::COND_BE; 464 case DCC_EQUAL | DCC_GREATER | DCC_SIGNED: return X86::COND_GE; 465 case DCC_EQUAL | DCC_GREATER | DCC_UNSIGNED: return X86::COND_AE; 466 case DCC_GREATER | DCC_LESSER | DCC_SIGNED: return X86::COND_NE; 467 case DCC_GREATER | DCC_LESSER | DCC_UNSIGNED: return X86::COND_NE; 468 case DCC_GREATER | DCC_LESSER: return X86::COND_NE; 469 case DCC_EQUAL | DCC_SIGNED: return X86::COND_E; 470 case DCC_EQUAL | DCC_UNSIGNED: return X86::COND_E; 471 case DCC_EQUAL: return X86::COND_E; 472 case DCC_LESSER | DCC_SIGNED: return X86::COND_L; 473 case DCC_LESSER | DCC_UNSIGNED: return X86::COND_B; 474 case DCC_GREATER | DCC_SIGNED: return X86::COND_G; 475 case DCC_GREATER | DCC_UNSIGNED: return X86::COND_A; 476 } 477 } 478 479 bool isValidCondCode(unsigned CC) const override { 480 return (CC != X86::COND_INVALID); 481 } 482 483 bool isBreakpoint(const MCInst &Inst) const override { 484 return Inst.getOpcode() == X86::INT3; 485 } 486 487 bool isPrefix(const MCInst &Inst) const override { 488 switch (Inst.getOpcode()) { 489 case X86::LOCK_PREFIX: 490 case X86::REPNE_PREFIX: 491 case X86::REP_PREFIX: 492 return true; 493 } 494 return false; 495 } 496 497 bool isRep(const MCInst &Inst) const override { 498 return Inst.getFlags() == X86::IP_HAS_REPEAT; 499 } 500 501 bool deleteREPPrefix(MCInst &Inst) const override { 502 if (Inst.getFlags() == X86::IP_HAS_REPEAT) { 503 Inst.setFlags(0); 504 return true; 505 } 506 return false; 507 } 508 509 // FIXME: For compatibility with old LLVM only! 510 bool isTerminator(const MCInst &Inst) const override { 511 if (Info->get(Inst.getOpcode()).isTerminator()) 512 return true; 513 switch (Inst.getOpcode()) { 514 default: 515 return false; 516 case X86::TRAP: 517 // Opcodes previously known as X86::UD2B 518 case X86::UD1Wm: 519 case X86::UD1Lm: 520 case X86::UD1Qm: 521 case X86::UD1Wr: 522 case X86::UD1Lr: 523 case X86::UD1Qr: 524 return true; 525 } 526 } 527 528 bool isIndirectCall(const MCInst &Inst) const override { 529 return isCall(Inst) && 530 ((getMemoryOperandNo(Inst) != -1) || Inst.getOperand(0).isReg()); 531 } 532 533 bool isPop(const MCInst &Inst) const override { 534 return getPopSize(Inst) == 0 ? false : true; 535 } 536 537 bool isTerminateBranch(const MCInst &Inst) const override { 538 return Inst.getOpcode() == X86::ENDBR32 || Inst.getOpcode() == X86::ENDBR64; 539 } 540 541 int getPopSize(const MCInst &Inst) const override { 542 switch (Inst.getOpcode()) { 543 case X86::POP16r: 544 case X86::POP16rmm: 545 case X86::POP16rmr: 546 case X86::POPF16: 547 case X86::POPA16: 548 case X86::POPDS16: 549 case X86::POPES16: 550 case X86::POPFS16: 551 case X86::POPGS16: 552 case X86::POPSS16: 553 return 2; 554 case X86::POP32r: 555 case X86::POP32rmm: 556 case X86::POP32rmr: 557 case X86::POPA32: 558 case X86::POPDS32: 559 case X86::POPES32: 560 case X86::POPF32: 561 case X86::POPFS32: 562 case X86::POPGS32: 563 case X86::POPSS32: 564 return 4; 565 case X86::POP64r: 566 case X86::POP64rmm: 567 case X86::POP64rmr: 568 case X86::POPF64: 569 case X86::POPFS64: 570 case X86::POPGS64: 571 return 8; 572 } 573 return 0; 574 } 575 576 bool isPush(const MCInst &Inst) const override { 577 return getPushSize(Inst) == 0 ? false : true; 578 } 579 580 int getPushSize(const MCInst &Inst) const override { 581 switch (Inst.getOpcode()) { 582 case X86::PUSH16i8: 583 case X86::PUSH16r: 584 case X86::PUSH16rmm: 585 case X86::PUSH16rmr: 586 case X86::PUSHA16: 587 case X86::PUSHCS16: 588 case X86::PUSHDS16: 589 case X86::PUSHES16: 590 case X86::PUSHF16: 591 case X86::PUSHFS16: 592 case X86::PUSHGS16: 593 case X86::PUSHSS16: 594 case X86::PUSHi16: 595 return 2; 596 case X86::PUSH32i8: 597 case X86::PUSH32r: 598 case X86::PUSH32rmm: 599 case X86::PUSH32rmr: 600 case X86::PUSHA32: 601 case X86::PUSHCS32: 602 case X86::PUSHDS32: 603 case X86::PUSHES32: 604 case X86::PUSHF32: 605 case X86::PUSHFS32: 606 case X86::PUSHGS32: 607 case X86::PUSHSS32: 608 case X86::PUSHi32: 609 return 4; 610 case X86::PUSH64i32: 611 case X86::PUSH64i8: 612 case X86::PUSH64r: 613 case X86::PUSH64rmm: 614 case X86::PUSH64rmr: 615 case X86::PUSHF64: 616 case X86::PUSHFS64: 617 case X86::PUSHGS64: 618 return 8; 619 } 620 return 0; 621 } 622 623 bool isADD64rr(const MCInst &Inst) const override { 624 return Inst.getOpcode() == X86::ADD64rr; 625 } 626 627 bool isSUB(const MCInst &Inst) const override { 628 return ::isSUB(Inst.getOpcode()); 629 } 630 631 bool isADDri(const MCInst &Inst) const { 632 return Inst.getOpcode() == X86::ADD64ri32 || 633 Inst.getOpcode() == X86::ADD64ri8; 634 } 635 636 bool isLEA64r(const MCInst &Inst) const override { 637 return Inst.getOpcode() == X86::LEA64r; 638 } 639 640 bool isMOVSX64rm32(const MCInst &Inst) const override { 641 return Inst.getOpcode() == X86::MOVSX64rm32; 642 } 643 644 bool isLeave(const MCInst &Inst) const override { 645 return Inst.getOpcode() == X86::LEAVE || 646 Inst.getOpcode() == X86::LEAVE64; 647 } 648 649 bool isMoveMem2Reg(const MCInst &Inst) const override { 650 switch (Inst.getOpcode()) { 651 case X86::MOV16rm: 652 case X86::MOV32rm: 653 case X86::MOV64rm: 654 return true; 655 } 656 return false; 657 } 658 659 bool isUnsupportedBranch(unsigned Opcode) const override { 660 switch (Opcode) { 661 default: 662 return false; 663 case X86::LOOP: 664 case X86::LOOPE: 665 case X86::LOOPNE: 666 case X86::JECXZ: 667 case X86::JRCXZ: 668 return true; 669 } 670 } 671 672 bool isLoad(const MCInst &Inst) const override { 673 if (isPop(Inst)) 674 return true; 675 676 int MemOpNo = getMemoryOperandNo(Inst); 677 const MCInstrDesc &MCII = Info->get(Inst.getOpcode()); 678 679 if (MemOpNo == -1) 680 return false; 681 682 return MCII.mayLoad(); 683 } 684 685 bool isStore(const MCInst &Inst) const override { 686 if (isPush(Inst)) 687 return true; 688 689 int MemOpNo = getMemoryOperandNo(Inst); 690 const MCInstrDesc &MCII = Info->get(Inst.getOpcode()); 691 692 if (MemOpNo == -1) 693 return false; 694 695 return MCII.mayStore(); 696 } 697 698 bool isCleanRegXOR(const MCInst &Inst) const override { 699 switch (Inst.getOpcode()) { 700 case X86::XOR16rr: 701 case X86::XOR32rr: 702 case X86::XOR64rr: 703 break; 704 default: 705 return false; 706 } 707 return (Inst.getOperand(0).getReg() == 708 Inst.getOperand(2).getReg()); 709 } 710 711 bool isPacked(const MCInst &Inst) const override { 712 const MCInstrDesc &Desc = Info->get(Inst.getOpcode()); 713 return (Desc.TSFlags & X86II::OpPrefixMask) == X86II::PD; 714 } 715 716 unsigned getTrapFillValue() const override { return 0xCC; } 717 718 struct IndJmpMatcherFrag1 : MCInstMatcher { 719 std::unique_ptr<MCInstMatcher> Base; 720 std::unique_ptr<MCInstMatcher> Scale; 721 std::unique_ptr<MCInstMatcher> Index; 722 std::unique_ptr<MCInstMatcher> Offset; 723 724 IndJmpMatcherFrag1(std::unique_ptr<MCInstMatcher> Base, 725 std::unique_ptr<MCInstMatcher> Scale, 726 std::unique_ptr<MCInstMatcher> Index, 727 std::unique_ptr<MCInstMatcher> Offset) 728 : Base(std::move(Base)), Scale(std::move(Scale)), 729 Index(std::move(Index)), Offset(std::move(Offset)) {} 730 731 bool match(const MCRegisterInfo &MRI, MCPlusBuilder &MIB, 732 MutableArrayRef<MCInst> InInstrWindow, int OpNum) override { 733 if (!MCInstMatcher::match(MRI, MIB, InInstrWindow, OpNum)) 734 return false; 735 736 if (CurInst->getOpcode() != X86::JMP64m) 737 return false; 738 739 int MemOpNo = MIB.getMemoryOperandNo(*CurInst); 740 if (MemOpNo == -1) 741 return false; 742 743 if (!Base->match(MRI, MIB, this->InstrWindow, MemOpNo + X86::AddrBaseReg)) 744 return false; 745 if (!Scale->match(MRI, MIB, this->InstrWindow, 746 MemOpNo + X86::AddrScaleAmt)) 747 return false; 748 if (!Index->match(MRI, MIB, this->InstrWindow, 749 MemOpNo + X86::AddrIndexReg)) 750 return false; 751 if (!Offset->match(MRI, MIB, this->InstrWindow, MemOpNo + X86::AddrDisp)) 752 return false; 753 return true; 754 } 755 756 void annotate(MCPlusBuilder &MIB, StringRef Annotation) override { 757 MIB.addAnnotation(*CurInst, Annotation, true); 758 Base->annotate(MIB, Annotation); 759 Scale->annotate(MIB, Annotation); 760 Index->annotate(MIB, Annotation); 761 Offset->annotate(MIB, Annotation); 762 } 763 }; 764 765 std::unique_ptr<MCInstMatcher> 766 matchIndJmp(std::unique_ptr<MCInstMatcher> Base, 767 std::unique_ptr<MCInstMatcher> Scale, 768 std::unique_ptr<MCInstMatcher> Index, 769 std::unique_ptr<MCInstMatcher> Offset) const override { 770 return std::unique_ptr<MCInstMatcher>( 771 new IndJmpMatcherFrag1(std::move(Base), std::move(Scale), 772 std::move(Index), std::move(Offset))); 773 } 774 775 struct IndJmpMatcherFrag2 : MCInstMatcher { 776 std::unique_ptr<MCInstMatcher> Reg; 777 778 IndJmpMatcherFrag2(std::unique_ptr<MCInstMatcher> Reg) 779 : Reg(std::move(Reg)) {} 780 781 bool match(const MCRegisterInfo &MRI, MCPlusBuilder &MIB, 782 MutableArrayRef<MCInst> InInstrWindow, int OpNum) override { 783 if (!MCInstMatcher::match(MRI, MIB, InInstrWindow, OpNum)) 784 return false; 785 786 if (CurInst->getOpcode() != X86::JMP64r) 787 return false; 788 789 return Reg->match(MRI, MIB, this->InstrWindow, 0); 790 } 791 792 void annotate(MCPlusBuilder &MIB, StringRef Annotation) override { 793 MIB.addAnnotation(*CurInst, Annotation, true); 794 Reg->annotate(MIB, Annotation); 795 } 796 }; 797 798 std::unique_ptr<MCInstMatcher> 799 matchIndJmp(std::unique_ptr<MCInstMatcher> Target) const override { 800 return std::unique_ptr<MCInstMatcher>( 801 new IndJmpMatcherFrag2(std::move(Target))); 802 } 803 804 struct LoadMatcherFrag1 : MCInstMatcher { 805 std::unique_ptr<MCInstMatcher> Base; 806 std::unique_ptr<MCInstMatcher> Scale; 807 std::unique_ptr<MCInstMatcher> Index; 808 std::unique_ptr<MCInstMatcher> Offset; 809 810 LoadMatcherFrag1(std::unique_ptr<MCInstMatcher> Base, 811 std::unique_ptr<MCInstMatcher> Scale, 812 std::unique_ptr<MCInstMatcher> Index, 813 std::unique_ptr<MCInstMatcher> Offset) 814 : Base(std::move(Base)), Scale(std::move(Scale)), 815 Index(std::move(Index)), Offset(std::move(Offset)) {} 816 817 bool match(const MCRegisterInfo &MRI, MCPlusBuilder &MIB, 818 MutableArrayRef<MCInst> InInstrWindow, int OpNum) override { 819 if (!MCInstMatcher::match(MRI, MIB, InInstrWindow, OpNum)) 820 return false; 821 822 if (CurInst->getOpcode() != X86::MOV64rm && 823 CurInst->getOpcode() != X86::MOVSX64rm32) 824 return false; 825 826 int MemOpNo = MIB.getMemoryOperandNo(*CurInst); 827 if (MemOpNo == -1) 828 return false; 829 830 if (!Base->match(MRI, MIB, this->InstrWindow, MemOpNo + X86::AddrBaseReg)) 831 return false; 832 if (!Scale->match(MRI, MIB, this->InstrWindow, 833 MemOpNo + X86::AddrScaleAmt)) 834 return false; 835 if (!Index->match(MRI, MIB, this->InstrWindow, 836 MemOpNo + X86::AddrIndexReg)) 837 return false; 838 if (!Offset->match(MRI, MIB, this->InstrWindow, MemOpNo + X86::AddrDisp)) 839 return false; 840 return true; 841 } 842 843 void annotate(MCPlusBuilder &MIB, StringRef Annotation) override { 844 MIB.addAnnotation(*CurInst, Annotation, true); 845 Base->annotate(MIB, Annotation); 846 Scale->annotate(MIB, Annotation); 847 Index->annotate(MIB, Annotation); 848 Offset->annotate(MIB, Annotation); 849 } 850 }; 851 852 std::unique_ptr<MCInstMatcher> 853 matchLoad(std::unique_ptr<MCInstMatcher> Base, 854 std::unique_ptr<MCInstMatcher> Scale, 855 std::unique_ptr<MCInstMatcher> Index, 856 std::unique_ptr<MCInstMatcher> Offset) const override { 857 return std::unique_ptr<MCInstMatcher>( 858 new LoadMatcherFrag1(std::move(Base), std::move(Scale), 859 std::move(Index), std::move(Offset))); 860 } 861 862 struct AddMatcher : MCInstMatcher { 863 std::unique_ptr<MCInstMatcher> A; 864 std::unique_ptr<MCInstMatcher> B; 865 866 AddMatcher(std::unique_ptr<MCInstMatcher> A, 867 std::unique_ptr<MCInstMatcher> B) 868 : A(std::move(A)), B(std::move(B)) {} 869 870 bool match(const MCRegisterInfo &MRI, MCPlusBuilder &MIB, 871 MutableArrayRef<MCInst> InInstrWindow, int OpNum) override { 872 if (!MCInstMatcher::match(MRI, MIB, InInstrWindow, OpNum)) 873 return false; 874 875 if (CurInst->getOpcode() == X86::ADD64rr || 876 CurInst->getOpcode() == X86::ADD64rr_DB || 877 CurInst->getOpcode() == X86::ADD64rr_REV) { 878 if (!A->match(MRI, MIB, this->InstrWindow, 1)) { 879 if (!B->match(MRI, MIB, this->InstrWindow, 1)) 880 return false; 881 return A->match(MRI, MIB, this->InstrWindow, 2); 882 } 883 884 if (B->match(MRI, MIB, this->InstrWindow, 2)) 885 return true; 886 887 if (!B->match(MRI, MIB, this->InstrWindow, 1)) 888 return false; 889 return A->match(MRI, MIB, this->InstrWindow, 2); 890 } 891 892 return false; 893 } 894 895 void annotate(MCPlusBuilder &MIB, StringRef Annotation) override { 896 MIB.addAnnotation(*CurInst, Annotation, true); 897 A->annotate(MIB, Annotation); 898 B->annotate(MIB, Annotation); 899 } 900 }; 901 902 virtual std::unique_ptr<MCInstMatcher> 903 matchAdd(std::unique_ptr<MCInstMatcher> A, 904 std::unique_ptr<MCInstMatcher> B) const override { 905 return std::unique_ptr<MCInstMatcher>( 906 new AddMatcher(std::move(A), std::move(B))); 907 } 908 909 struct LEAMatcher : MCInstMatcher { 910 std::unique_ptr<MCInstMatcher> Target; 911 912 LEAMatcher(std::unique_ptr<MCInstMatcher> Target) 913 : Target(std::move(Target)) {} 914 915 bool match(const MCRegisterInfo &MRI, MCPlusBuilder &MIB, 916 MutableArrayRef<MCInst> InInstrWindow, int OpNum) override { 917 if (!MCInstMatcher::match(MRI, MIB, InInstrWindow, OpNum)) 918 return false; 919 920 if (CurInst->getOpcode() != X86::LEA64r) 921 return false; 922 923 if (CurInst->getOperand(1 + X86::AddrScaleAmt).getImm() != 1 || 924 CurInst->getOperand(1 + X86::AddrIndexReg).getReg() != 925 X86::NoRegister || 926 (CurInst->getOperand(1 + X86::AddrBaseReg).getReg() != 927 X86::NoRegister && 928 CurInst->getOperand(1 + X86::AddrBaseReg).getReg() != X86::RIP)) 929 return false; 930 931 return Target->match(MRI, MIB, this->InstrWindow, 1 + X86::AddrDisp); 932 } 933 934 void annotate(MCPlusBuilder &MIB, StringRef Annotation) override { 935 MIB.addAnnotation(*CurInst, Annotation, true); 936 Target->annotate(MIB, Annotation); 937 } 938 }; 939 940 virtual std::unique_ptr<MCInstMatcher> 941 matchLoadAddr(std::unique_ptr<MCInstMatcher> Target) const override { 942 return std::unique_ptr<MCInstMatcher>(new LEAMatcher(std::move(Target))); 943 } 944 945 bool hasPCRelOperand(const MCInst &Inst) const override { 946 for (const MCOperand &Operand : Inst) 947 if (Operand.isReg() && Operand.getReg() == X86::RIP) 948 return true; 949 return false; 950 } 951 952 int getMemoryOperandNo(const MCInst &Inst) const override { 953 unsigned Opcode = Inst.getOpcode(); 954 const MCInstrDesc &Desc = Info->get(Opcode); 955 int MemOpNo = X86II::getMemoryOperandNo(Desc.TSFlags); 956 if (MemOpNo >= 0) 957 MemOpNo += X86II::getOperandBias(Desc); 958 return MemOpNo; 959 } 960 961 bool hasEVEXEncoding(const MCInst &Inst) const override { 962 const MCInstrDesc &Desc = Info->get(Inst.getOpcode()); 963 return (Desc.TSFlags & X86II::EncodingMask) == X86II::EVEX; 964 } 965 966 bool isMacroOpFusionPair(ArrayRef<MCInst> Insts) const override { 967 // FIXME: the macro-op fusion is triggered under different conditions 968 // on different cores. This implementation is for sandy-bridge+. 969 const auto *I = Insts.begin(); 970 while (I != Insts.end() && isPrefix(*I)) 971 ++I; 972 if (I == Insts.end()) 973 return false; 974 975 const MCInst &FirstInst = *I; 976 ++I; 977 while (I != Insts.end() && isPrefix(*I)) 978 ++I; 979 if (I == Insts.end()) 980 return false; 981 const MCInst &SecondInst = *I; 982 983 if (!isConditionalBranch(SecondInst)) 984 return false; 985 // J?CXZ and LOOP cannot be fused 986 if (SecondInst.getOpcode() == X86::LOOP || 987 SecondInst.getOpcode() == X86::LOOPE || 988 SecondInst.getOpcode() == X86::LOOPNE || 989 SecondInst.getOpcode() == X86::JECXZ || 990 SecondInst.getOpcode() == X86::JRCXZ) 991 return false; 992 993 // Cannot fuse if first instruction operands are MEM-IMM. 994 const MCInstrDesc &Desc = Info->get(FirstInst.getOpcode()); 995 int MemOpNo = X86II::getMemoryOperandNo(Desc.TSFlags); 996 if (MemOpNo != -1 && X86II::hasImm(Desc.TSFlags)) 997 return false; 998 999 // Cannot fuse if the first instruction uses RIP-relative memory. 1000 // FIXME: verify that this is true. 1001 if (hasPCRelOperand(FirstInst)) 1002 return false; 1003 1004 // Check instructions against table 3-1 in Intel's Optimization Guide. 1005 unsigned FirstInstGroup = 0; 1006 if (isTEST(FirstInst.getOpcode()) || isAND(FirstInst.getOpcode())) 1007 FirstInstGroup = 1; 1008 else if (isCMP(FirstInst.getOpcode()) || isADD(FirstInst.getOpcode()) || 1009 ::isSUB(FirstInst.getOpcode())) 1010 FirstInstGroup = 2; 1011 else if (isINC(FirstInst.getOpcode()) || isDEC(FirstInst.getOpcode())) 1012 FirstInstGroup = 3; 1013 1014 if (FirstInstGroup == 0) 1015 return false; 1016 1017 const unsigned CondCode = 1018 getCanonicalBranchCondCode(getCondCode(SecondInst)); 1019 switch (CondCode) { 1020 default: 1021 llvm_unreachable("unexpected conditional code"); 1022 return false; 1023 case X86::COND_E: 1024 case X86::COND_L: 1025 case X86::COND_G: 1026 return true; 1027 case X86::COND_O: 1028 case X86::COND_P: 1029 case X86::COND_S: 1030 if (FirstInstGroup == 1) 1031 return true; 1032 return false; 1033 case X86::COND_A: 1034 case X86::COND_B: 1035 if (FirstInstGroup != 3) 1036 return true; 1037 return false; 1038 } 1039 } 1040 1041 bool evaluateX86MemoryOperand(const MCInst &Inst, 1042 unsigned *BaseRegNum, 1043 int64_t *ScaleImm, 1044 unsigned *IndexRegNum, 1045 int64_t *DispImm, 1046 unsigned *SegmentRegNum, 1047 const MCExpr **DispExpr = nullptr) 1048 const override { 1049 assert(BaseRegNum && ScaleImm && IndexRegNum && SegmentRegNum && 1050 "one of the input pointers is null"); 1051 int MemOpNo = getMemoryOperandNo(Inst); 1052 if (MemOpNo < 0) 1053 return false; 1054 unsigned MemOpOffset = static_cast<unsigned>(MemOpNo); 1055 1056 if (MemOpOffset + X86::AddrSegmentReg >= MCPlus::getNumPrimeOperands(Inst)) 1057 return false; 1058 1059 const MCOperand &Base = Inst.getOperand(MemOpOffset + X86::AddrBaseReg); 1060 const MCOperand &Scale = Inst.getOperand(MemOpOffset + X86::AddrScaleAmt); 1061 const MCOperand &Index = Inst.getOperand(MemOpOffset + X86::AddrIndexReg); 1062 const MCOperand &Disp = Inst.getOperand(MemOpOffset + X86::AddrDisp); 1063 const MCOperand &Segment = 1064 Inst.getOperand(MemOpOffset + X86::AddrSegmentReg); 1065 1066 // Make sure it is a well-formed memory operand. 1067 if (!Base.isReg() || !Scale.isImm() || !Index.isReg() || 1068 (!Disp.isImm() && !Disp.isExpr()) || !Segment.isReg()) 1069 return false; 1070 1071 *BaseRegNum = Base.getReg(); 1072 *ScaleImm = Scale.getImm(); 1073 *IndexRegNum = Index.getReg(); 1074 if (Disp.isImm()) { 1075 assert(DispImm && "DispImm needs to be set"); 1076 *DispImm = Disp.getImm(); 1077 if (DispExpr) 1078 *DispExpr = nullptr; 1079 } else { 1080 assert(DispExpr && "DispExpr needs to be set"); 1081 *DispExpr = Disp.getExpr(); 1082 if (DispImm) 1083 *DispImm = 0; 1084 } 1085 *SegmentRegNum = Segment.getReg(); 1086 return true; 1087 } 1088 1089 bool evaluateMemOperandTarget(const MCInst &Inst, 1090 uint64_t &Target, 1091 uint64_t Address, 1092 uint64_t Size) const override { 1093 unsigned BaseRegNum; 1094 int64_t ScaleValue; 1095 unsigned IndexRegNum; 1096 int64_t DispValue; 1097 unsigned SegRegNum; 1098 const MCExpr *DispExpr = nullptr; 1099 if (!evaluateX86MemoryOperand(Inst, &BaseRegNum, &ScaleValue, &IndexRegNum, 1100 &DispValue, &SegRegNum, &DispExpr)) 1101 return false; 1102 1103 // Make sure it's a well-formed addressing we can statically evaluate. 1104 if ((BaseRegNum != X86::RIP && BaseRegNum != X86::NoRegister) || 1105 IndexRegNum != X86::NoRegister || SegRegNum != X86::NoRegister || 1106 DispExpr) 1107 return false; 1108 1109 Target = DispValue; 1110 if (BaseRegNum == X86::RIP) { 1111 assert(Size != 0 && "instruction size required in order to statically " 1112 "evaluate RIP-relative address"); 1113 Target += Address + Size; 1114 } 1115 return true; 1116 } 1117 1118 MCInst::iterator getMemOperandDisp(MCInst &Inst) const override { 1119 int MemOpNo = getMemoryOperandNo(Inst); 1120 if (MemOpNo < 0) 1121 return Inst.end(); 1122 return Inst.begin() + (MemOpNo + X86::AddrDisp); 1123 } 1124 1125 bool replaceMemOperandDisp(MCInst &Inst, MCOperand Operand) const override { 1126 MCOperand *OI = getMemOperandDisp(Inst); 1127 if (OI == Inst.end()) 1128 return false; 1129 *OI = Operand; 1130 return true; 1131 } 1132 1133 /// Get the registers used as function parameters. 1134 /// This function is specific to the x86_64 abi on Linux. 1135 BitVector getRegsUsedAsParams() const override { 1136 BitVector Regs = BitVector(RegInfo->getNumRegs(), false); 1137 Regs |= getAliases(X86::RSI); 1138 Regs |= getAliases(X86::RDI); 1139 Regs |= getAliases(X86::RDX); 1140 Regs |= getAliases(X86::RCX); 1141 Regs |= getAliases(X86::R8); 1142 Regs |= getAliases(X86::R9); 1143 return Regs; 1144 } 1145 1146 void getCalleeSavedRegs(BitVector &Regs) const override { 1147 Regs |= getAliases(X86::RBX); 1148 Regs |= getAliases(X86::RBP); 1149 Regs |= getAliases(X86::R12); 1150 Regs |= getAliases(X86::R13); 1151 Regs |= getAliases(X86::R14); 1152 Regs |= getAliases(X86::R15); 1153 } 1154 1155 void getDefaultDefIn(BitVector &Regs) const override { 1156 assert(Regs.size() >= RegInfo->getNumRegs() && 1157 "The size of BitVector is less than RegInfo->getNumRegs()."); 1158 Regs.set(X86::RAX); 1159 Regs.set(X86::RCX); 1160 Regs.set(X86::RDX); 1161 Regs.set(X86::RSI); 1162 Regs.set(X86::RDI); 1163 Regs.set(X86::R8); 1164 Regs.set(X86::R9); 1165 Regs.set(X86::XMM0); 1166 Regs.set(X86::XMM1); 1167 Regs.set(X86::XMM2); 1168 Regs.set(X86::XMM3); 1169 Regs.set(X86::XMM4); 1170 Regs.set(X86::XMM5); 1171 Regs.set(X86::XMM6); 1172 Regs.set(X86::XMM7); 1173 } 1174 1175 void getDefaultLiveOut(BitVector &Regs) const override { 1176 assert(Regs.size() >= RegInfo->getNumRegs() && 1177 "The size of BitVector is less than RegInfo->getNumRegs()."); 1178 Regs |= getAliases(X86::RAX); 1179 Regs |= getAliases(X86::RDX); 1180 Regs |= getAliases(X86::RCX); 1181 Regs |= getAliases(X86::XMM0); 1182 Regs |= getAliases(X86::XMM1); 1183 } 1184 1185 void getGPRegs(BitVector &Regs, bool IncludeAlias) const override { 1186 if (IncludeAlias) { 1187 Regs |= getAliases(X86::RAX); 1188 Regs |= getAliases(X86::RBX); 1189 Regs |= getAliases(X86::RBP); 1190 Regs |= getAliases(X86::RSI); 1191 Regs |= getAliases(X86::RDI); 1192 Regs |= getAliases(X86::RDX); 1193 Regs |= getAliases(X86::RCX); 1194 Regs |= getAliases(X86::R8); 1195 Regs |= getAliases(X86::R9); 1196 Regs |= getAliases(X86::R10); 1197 Regs |= getAliases(X86::R11); 1198 Regs |= getAliases(X86::R12); 1199 Regs |= getAliases(X86::R13); 1200 Regs |= getAliases(X86::R14); 1201 Regs |= getAliases(X86::R15); 1202 return; 1203 } 1204 Regs.set(X86::RAX); 1205 Regs.set(X86::RBX); 1206 Regs.set(X86::RBP); 1207 Regs.set(X86::RSI); 1208 Regs.set(X86::RDI); 1209 Regs.set(X86::RDX); 1210 Regs.set(X86::RCX); 1211 Regs.set(X86::R8); 1212 Regs.set(X86::R9); 1213 Regs.set(X86::R10); 1214 Regs.set(X86::R11); 1215 Regs.set(X86::R12); 1216 Regs.set(X86::R13); 1217 Regs.set(X86::R14); 1218 Regs.set(X86::R15); 1219 } 1220 1221 void getClassicGPRegs(BitVector &Regs) const override { 1222 Regs |= getAliases(X86::RAX); 1223 Regs |= getAliases(X86::RBX); 1224 Regs |= getAliases(X86::RBP); 1225 Regs |= getAliases(X86::RSI); 1226 Regs |= getAliases(X86::RDI); 1227 Regs |= getAliases(X86::RDX); 1228 Regs |= getAliases(X86::RCX); 1229 } 1230 1231 void getRepRegs(BitVector &Regs) const override { 1232 Regs |= getAliases(X86::RCX); 1233 } 1234 1235 MCPhysReg getAliasSized(MCPhysReg Reg, uint8_t Size) const override { 1236 switch (Reg) { 1237 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: case X86::AH: 1238 switch (Size) { 1239 case 8: return X86::RAX; case 4: return X86::EAX; 1240 case 2: return X86::AX; case 1: return X86::AL; 1241 default: llvm_unreachable("Unexpected size"); 1242 } 1243 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: case X86::BH: 1244 switch (Size) { 1245 case 8: return X86::RBX; case 4: return X86::EBX; 1246 case 2: return X86::BX; case 1: return X86::BL; 1247 default: llvm_unreachable("Unexpected size"); 1248 } 1249 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: case X86::DH: 1250 switch (Size) { 1251 case 8: return X86::RDX; case 4: return X86::EDX; 1252 case 2: return X86::DX; case 1: return X86::DL; 1253 default: llvm_unreachable("Unexpected size"); 1254 } 1255 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: 1256 switch (Size) { 1257 case 8: return X86::RDI; case 4: return X86::EDI; 1258 case 2: return X86::DI; case 1: return X86::DIL; 1259 default: llvm_unreachable("Unexpected size"); 1260 } 1261 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: 1262 switch (Size) { 1263 case 8: return X86::RSI; case 4: return X86::ESI; 1264 case 2: return X86::SI; case 1: return X86::SIL; 1265 default: llvm_unreachable("Unexpected size"); 1266 } 1267 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: case X86::CH: 1268 switch (Size) { 1269 case 8: return X86::RCX; case 4: return X86::ECX; 1270 case 2: return X86::CX; case 1: return X86::CL; 1271 default: llvm_unreachable("Unexpected size"); 1272 } 1273 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: 1274 switch (Size) { 1275 case 8: return X86::RSP; case 4: return X86::ESP; 1276 case 2: return X86::SP; case 1: return X86::SPL; 1277 default: llvm_unreachable("Unexpected size"); 1278 } 1279 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: 1280 switch (Size) { 1281 case 8: return X86::RBP; case 4: return X86::EBP; 1282 case 2: return X86::BP; case 1: return X86::BPL; 1283 default: llvm_unreachable("Unexpected size"); 1284 } 1285 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B: 1286 switch (Size) { 1287 case 8: return X86::R8; case 4: return X86::R8D; 1288 case 2: return X86::R8W; case 1: return X86::R8B; 1289 default: llvm_unreachable("Unexpected size"); 1290 } 1291 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B: 1292 switch (Size) { 1293 case 8: return X86::R9; case 4: return X86::R9D; 1294 case 2: return X86::R9W; case 1: return X86::R9B; 1295 default: llvm_unreachable("Unexpected size"); 1296 } 1297 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B: 1298 switch (Size) { 1299 case 8: return X86::R10; case 4: return X86::R10D; 1300 case 2: return X86::R10W; case 1: return X86::R10B; 1301 default: llvm_unreachable("Unexpected size"); 1302 } 1303 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B: 1304 switch (Size) { 1305 case 8: return X86::R11; case 4: return X86::R11D; 1306 case 2: return X86::R11W; case 1: return X86::R11B; 1307 default: llvm_unreachable("Unexpected size"); 1308 } 1309 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B: 1310 switch (Size) { 1311 case 8: return X86::R12; case 4: return X86::R12D; 1312 case 2: return X86::R12W; case 1: return X86::R12B; 1313 default: llvm_unreachable("Unexpected size"); 1314 } 1315 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B: 1316 switch (Size) { 1317 case 8: return X86::R13; case 4: return X86::R13D; 1318 case 2: return X86::R13W; case 1: return X86::R13B; 1319 default: llvm_unreachable("Unexpected size"); 1320 } 1321 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B: 1322 switch (Size) { 1323 case 8: return X86::R14; case 4: return X86::R14D; 1324 case 2: return X86::R14W; case 1: return X86::R14B; 1325 default: llvm_unreachable("Unexpected size"); 1326 } 1327 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B: 1328 switch (Size) { 1329 case 8: return X86::R15; case 4: return X86::R15D; 1330 case 2: return X86::R15W; case 1: return X86::R15B; 1331 default: llvm_unreachable("Unexpected size"); 1332 } 1333 default: 1334 dbgs() << Reg << " (get alias sized)\n"; 1335 llvm_unreachable("Unexpected reg number"); 1336 break; 1337 } 1338 } 1339 1340 bool isUpper8BitReg(MCPhysReg Reg) const override { 1341 switch (Reg) { 1342 case X86::AH: case X86::BH: case X86::CH: case X86::DH: 1343 return true; 1344 default: 1345 return false; 1346 } 1347 } 1348 1349 bool cannotUseREX(const MCInst &Inst) const override { 1350 switch(Inst.getOpcode()) { 1351 case X86::MOV8mr_NOREX: 1352 case X86::MOV8rm_NOREX: 1353 case X86::MOV8rr_NOREX: 1354 case X86::MOVSX32rm8_NOREX: 1355 case X86::MOVSX32rr8_NOREX: 1356 case X86::MOVZX32rm8_NOREX: 1357 case X86::MOVZX32rr8_NOREX: 1358 case X86::MOV8mr: 1359 case X86::MOV8rm: 1360 case X86::MOV8rr: 1361 case X86::MOVSX32rm8: 1362 case X86::MOVSX32rr8: 1363 case X86::MOVZX32rm8: 1364 case X86::MOVZX32rr8: 1365 case X86::TEST8ri: 1366 for (int I = 0, E = MCPlus::getNumPrimeOperands(Inst); I != E; ++I) { 1367 const MCOperand &Operand = Inst.getOperand(I); 1368 if (!Operand.isReg()) 1369 continue; 1370 if (isUpper8BitReg(Operand.getReg())) 1371 return true; 1372 } 1373 LLVM_FALLTHROUGH; 1374 default: 1375 return false; 1376 } 1377 } 1378 1379 bool isStackAccess(const MCInst &Inst, bool &IsLoad, bool &IsStore, 1380 bool &IsStoreFromReg, MCPhysReg &Reg, int32_t &SrcImm, 1381 uint16_t &StackPtrReg, int64_t &StackOffset, 1382 uint8_t &Size, bool &IsSimple, 1383 bool &IsIndexed) const override { 1384 // Detect simple push/pop cases first 1385 if (int Sz = getPushSize(Inst)) { 1386 IsLoad = false; 1387 IsStore = true; 1388 IsStoreFromReg = true; 1389 StackPtrReg = X86::RSP; 1390 StackOffset = -Sz; 1391 Size = Sz; 1392 IsSimple = true; 1393 if (Inst.getOperand(0).isImm()) 1394 SrcImm = Inst.getOperand(0).getImm(); 1395 else if (Inst.getOperand(0).isReg()) 1396 Reg = Inst.getOperand(0).getReg(); 1397 else 1398 IsSimple = false; 1399 1400 return true; 1401 } 1402 if (int Sz = getPopSize(Inst)) { 1403 IsLoad = true; 1404 IsStore = false; 1405 if (Inst.getNumOperands() == 0 || !Inst.getOperand(0).isReg()) { 1406 IsSimple = false; 1407 } else { 1408 Reg = Inst.getOperand(0).getReg(); 1409 IsSimple = true; 1410 } 1411 StackPtrReg = X86::RSP; 1412 StackOffset = 0; 1413 Size = Sz; 1414 return true; 1415 } 1416 1417 struct InstInfo { 1418 // Size in bytes that Inst loads from memory. 1419 uint8_t DataSize; 1420 bool IsLoad; 1421 bool IsStore; 1422 bool StoreFromReg; 1423 bool Simple; 1424 }; 1425 1426 InstInfo I; 1427 int MemOpNo = getMemoryOperandNo(Inst); 1428 const MCInstrDesc &MCII = Info->get(Inst.getOpcode()); 1429 // If it is not dealing with a memory operand, we discard it 1430 if (MemOpNo == -1 || MCII.isCall()) 1431 return false; 1432 1433 switch (Inst.getOpcode()) { 1434 default: { 1435 uint8_t Sz = 0; 1436 bool IsLoad = MCII.mayLoad(); 1437 bool IsStore = MCII.mayStore(); 1438 // Is it LEA? (deals with memory but is not loading nor storing) 1439 if (!IsLoad && !IsStore) 1440 return false; 1441 1442 // Try to guess data size involved in the load/store by looking at the 1443 // register size. If there's no reg involved, return 0 as size, meaning 1444 // we don't know. 1445 for (unsigned I = 0, E = MCII.getNumOperands(); I != E; ++I) { 1446 if (MCII.OpInfo[I].OperandType != MCOI::OPERAND_REGISTER) 1447 continue; 1448 if (static_cast<int>(I) >= MemOpNo && I < X86::AddrNumOperands) 1449 continue; 1450 Sz = RegInfo->getRegClass(MCII.OpInfo[I].RegClass).getSizeInBits() / 8; 1451 break; 1452 } 1453 I = {Sz, IsLoad, IsStore, false, false}; 1454 break; 1455 } 1456 case X86::MOV16rm: I = {2, true, false, false, true}; break; 1457 case X86::MOV32rm: I = {4, true, false, false, true}; break; 1458 case X86::MOV64rm: I = {8, true, false, false, true}; break; 1459 case X86::MOV16mr: I = {2, false, true, true, true}; break; 1460 case X86::MOV32mr: I = {4, false, true, true, true}; break; 1461 case X86::MOV64mr: I = {8, false, true, true, true}; break; 1462 case X86::MOV16mi: I = {2, false, true, false, true}; break; 1463 case X86::MOV32mi: I = {4, false, true, false, true}; break; 1464 } // end switch (Inst.getOpcode()) 1465 1466 unsigned BaseRegNum; 1467 int64_t ScaleValue; 1468 unsigned IndexRegNum; 1469 int64_t DispValue; 1470 unsigned SegRegNum; 1471 const MCExpr *DispExpr; 1472 if (!evaluateX86MemoryOperand(Inst, &BaseRegNum, &ScaleValue, &IndexRegNum, 1473 &DispValue, &SegRegNum, &DispExpr)) { 1474 LLVM_DEBUG(dbgs() << "Evaluate failed on "); 1475 LLVM_DEBUG(Inst.dump()); 1476 return false; 1477 } 1478 1479 // Make sure it's a stack access 1480 if (BaseRegNum != X86::RBP && BaseRegNum != X86::RSP) 1481 return false; 1482 1483 IsLoad = I.IsLoad; 1484 IsStore = I.IsStore; 1485 IsStoreFromReg = I.StoreFromReg; 1486 Size = I.DataSize; 1487 IsSimple = I.Simple; 1488 StackPtrReg = BaseRegNum; 1489 StackOffset = DispValue; 1490 IsIndexed = IndexRegNum != X86::NoRegister || SegRegNum != X86::NoRegister; 1491 1492 if (!I.Simple) 1493 return true; 1494 1495 // Retrieve related register in simple MOV from/to stack operations. 1496 unsigned MemOpOffset = static_cast<unsigned>(MemOpNo); 1497 if (I.IsLoad) { 1498 MCOperand RegOpnd = Inst.getOperand(0); 1499 assert(RegOpnd.isReg() && "unexpected destination operand"); 1500 Reg = RegOpnd.getReg(); 1501 } else if (I.IsStore) { 1502 MCOperand SrcOpnd = 1503 Inst.getOperand(MemOpOffset + X86::AddrSegmentReg + 1); 1504 if (I.StoreFromReg) { 1505 assert(SrcOpnd.isReg() && "unexpected source operand"); 1506 Reg = SrcOpnd.getReg(); 1507 } else { 1508 assert(SrcOpnd.isImm() && "unexpected source operand"); 1509 SrcImm = SrcOpnd.getImm(); 1510 } 1511 } 1512 1513 return true; 1514 } 1515 1516 void changeToPushOrPop(MCInst &Inst) const override { 1517 assert(!isPush(Inst) && !isPop(Inst)); 1518 1519 struct InstInfo { 1520 // Size in bytes that Inst loads from memory. 1521 uint8_t DataSize; 1522 bool IsLoad; 1523 bool StoreFromReg; 1524 }; 1525 1526 InstInfo I; 1527 switch (Inst.getOpcode()) { 1528 default: { 1529 llvm_unreachable("Unhandled opcode"); 1530 return; 1531 } 1532 case X86::MOV16rm: I = {2, true, false}; break; 1533 case X86::MOV32rm: I = {4, true, false}; break; 1534 case X86::MOV64rm: I = {8, true, false}; break; 1535 case X86::MOV16mr: I = {2, false, true}; break; 1536 case X86::MOV32mr: I = {4, false, true}; break; 1537 case X86::MOV64mr: I = {8, false, true}; break; 1538 case X86::MOV16mi: I = {2, false, false}; break; 1539 case X86::MOV32mi: I = {4, false, false}; break; 1540 } // end switch (Inst.getOpcode()) 1541 1542 unsigned BaseRegNum; 1543 int64_t ScaleValue; 1544 unsigned IndexRegNum; 1545 int64_t DispValue; 1546 unsigned SegRegNum; 1547 const MCExpr *DispExpr; 1548 if (!evaluateX86MemoryOperand(Inst, &BaseRegNum, &ScaleValue, &IndexRegNum, 1549 &DispValue, &SegRegNum, &DispExpr)) { 1550 llvm_unreachable("Evaluate failed"); 1551 return; 1552 } 1553 // Make sure it's a stack access 1554 if (BaseRegNum != X86::RBP && BaseRegNum != X86::RSP) { 1555 llvm_unreachable("Not a stack access"); 1556 return; 1557 } 1558 1559 unsigned MemOpOffset = getMemoryOperandNo(Inst); 1560 unsigned NewOpcode = 0; 1561 if (I.IsLoad) { 1562 switch (I.DataSize) { 1563 case 2: NewOpcode = X86::POP16r; break; 1564 case 4: NewOpcode = X86::POP32r; break; 1565 case 8: NewOpcode = X86::POP64r; break; 1566 default: 1567 assert(false); 1568 } 1569 unsigned RegOpndNum = Inst.getOperand(0).getReg(); 1570 Inst.clear(); 1571 Inst.setOpcode(NewOpcode); 1572 Inst.addOperand(MCOperand::createReg(RegOpndNum)); 1573 } else { 1574 MCOperand SrcOpnd = 1575 Inst.getOperand(MemOpOffset + X86::AddrSegmentReg + 1); 1576 if (I.StoreFromReg) { 1577 switch (I.DataSize) { 1578 case 2: NewOpcode = X86::PUSH16r; break; 1579 case 4: NewOpcode = X86::PUSH32r; break; 1580 case 8: NewOpcode = X86::PUSH64r; break; 1581 default: 1582 assert(false); 1583 } 1584 assert(SrcOpnd.isReg() && "unexpected source operand"); 1585 unsigned RegOpndNum = SrcOpnd.getReg(); 1586 Inst.clear(); 1587 Inst.setOpcode(NewOpcode); 1588 Inst.addOperand(MCOperand::createReg(RegOpndNum)); 1589 } else { 1590 switch (I.DataSize) { 1591 case 2: NewOpcode = X86::PUSH16i8; break; 1592 case 4: NewOpcode = X86::PUSH32i8; break; 1593 case 8: NewOpcode = X86::PUSH64i32; break; 1594 default: 1595 assert(false); 1596 } 1597 assert(SrcOpnd.isImm() && "unexpected source operand"); 1598 int64_t SrcImm = SrcOpnd.getImm(); 1599 Inst.clear(); 1600 Inst.setOpcode(NewOpcode); 1601 Inst.addOperand(MCOperand::createImm(SrcImm)); 1602 } 1603 } 1604 } 1605 1606 bool isStackAdjustment(const MCInst &Inst) const override { 1607 switch (Inst.getOpcode()) { 1608 default: 1609 return false; 1610 case X86::SUB64ri32: 1611 case X86::SUB64ri8: 1612 case X86::ADD64ri32: 1613 case X86::ADD64ri8: 1614 case X86::LEA64r: 1615 break; 1616 } 1617 1618 const MCInstrDesc &MCII = Info->get(Inst.getOpcode()); 1619 for (int I = 0, E = MCII.getNumDefs(); I != E; ++I) { 1620 const MCOperand &Operand = Inst.getOperand(I); 1621 if (Operand.isReg() && Operand.getReg() == X86::RSP) 1622 return true; 1623 } 1624 return false; 1625 } 1626 1627 bool evaluateSimple(const MCInst &Inst, int64_t &Output, 1628 std::pair<MCPhysReg, int64_t> Input1, 1629 std::pair<MCPhysReg, int64_t> Input2) const override { 1630 1631 auto getOperandVal = [&](MCPhysReg Reg) -> ErrorOr<int64_t> { 1632 if (Reg == Input1.first) 1633 return Input1.second; 1634 if (Reg == Input2.first) 1635 return Input2.second; 1636 return make_error_code(errc::result_out_of_range); 1637 }; 1638 1639 switch (Inst.getOpcode()) { 1640 default: 1641 return false; 1642 1643 case X86::AND64ri32: 1644 case X86::AND64ri8: 1645 if (!Inst.getOperand(2).isImm()) 1646 return false; 1647 if (ErrorOr<int64_t> InputVal = 1648 getOperandVal(Inst.getOperand(1).getReg())) 1649 Output = *InputVal & Inst.getOperand(2).getImm(); 1650 else 1651 return false; 1652 break; 1653 case X86::SUB64ri32: 1654 case X86::SUB64ri8: 1655 if (!Inst.getOperand(2).isImm()) 1656 return false; 1657 if (ErrorOr<int64_t> InputVal = 1658 getOperandVal(Inst.getOperand(1).getReg())) 1659 Output = *InputVal - Inst.getOperand(2).getImm(); 1660 else 1661 return false; 1662 break; 1663 case X86::ADD64ri32: 1664 case X86::ADD64ri8: 1665 if (!Inst.getOperand(2).isImm()) 1666 return false; 1667 if (ErrorOr<int64_t> InputVal = 1668 getOperandVal(Inst.getOperand(1).getReg())) 1669 Output = *InputVal + Inst.getOperand(2).getImm(); 1670 else 1671 return false; 1672 break; 1673 case X86::ADD64i32: 1674 if (!Inst.getOperand(0).isImm()) 1675 return false; 1676 if (ErrorOr<int64_t> InputVal = getOperandVal(X86::RAX)) 1677 Output = *InputVal + Inst.getOperand(0).getImm(); 1678 else 1679 return false; 1680 break; 1681 1682 case X86::LEA64r: { 1683 unsigned BaseRegNum; 1684 int64_t ScaleValue; 1685 unsigned IndexRegNum; 1686 int64_t DispValue; 1687 unsigned SegRegNum; 1688 const MCExpr *DispExpr = nullptr; 1689 if (!evaluateX86MemoryOperand(Inst, &BaseRegNum, &ScaleValue, 1690 &IndexRegNum, &DispValue, &SegRegNum, 1691 &DispExpr)) 1692 return false; 1693 1694 if (BaseRegNum == X86::NoRegister || IndexRegNum != X86::NoRegister || 1695 SegRegNum != X86::NoRegister || DispExpr) 1696 return false; 1697 1698 if (ErrorOr<int64_t> InputVal = getOperandVal(BaseRegNum)) 1699 Output = *InputVal + DispValue; 1700 else 1701 return false; 1702 1703 break; 1704 } 1705 } 1706 return true; 1707 } 1708 1709 bool isRegToRegMove(const MCInst &Inst, MCPhysReg &From, 1710 MCPhysReg &To) const override { 1711 switch (Inst.getOpcode()) { 1712 default: 1713 return false; 1714 case X86::LEAVE: 1715 case X86::LEAVE64: 1716 To = getStackPointer(); 1717 From = getFramePointer(); 1718 return true; 1719 case X86::MOV64rr: 1720 To = Inst.getOperand(0).getReg(); 1721 From = Inst.getOperand(1).getReg(); 1722 return true; 1723 } 1724 } 1725 1726 MCPhysReg getStackPointer() const override { return X86::RSP; } 1727 MCPhysReg getFramePointer() const override { return X86::RBP; } 1728 MCPhysReg getFlagsReg() const override { return X86::EFLAGS; } 1729 1730 bool escapesVariable(const MCInst &Inst, bool HasFramePointer) const override { 1731 int MemOpNo = getMemoryOperandNo(Inst); 1732 const MCInstrDesc &MCII = Info->get(Inst.getOpcode()); 1733 const unsigned NumDefs = MCII.getNumDefs(); 1734 static BitVector SPBPAliases(BitVector(getAliases(X86::RSP)) |= 1735 getAliases(X86::RBP)); 1736 static BitVector SPAliases(getAliases(X86::RSP)); 1737 1738 // FIXME: PUSH can be technically a leak, but let's ignore this for now 1739 // because a lot of harmless prologue code will spill SP to the stack. 1740 // Unless push is clearly pushing an object address to the stack as 1741 // demonstrated by having a MemOp. 1742 bool IsPush = isPush(Inst); 1743 if (IsPush && MemOpNo == -1) 1744 return false; 1745 1746 // We use this to detect LEA (has memop but does not access mem) 1747 bool AccessMem = MCII.mayLoad() || MCII.mayStore(); 1748 bool DoesLeak = false; 1749 for (int I = 0, E = MCPlus::getNumPrimeOperands(Inst); I != E; ++I) { 1750 // Ignore if SP/BP is used to dereference memory -- that's fine 1751 if (MemOpNo != -1 && !IsPush && AccessMem && I >= MemOpNo && 1752 I <= MemOpNo + 5) 1753 continue; 1754 // Ignore if someone is writing to SP/BP 1755 if (I < static_cast<int>(NumDefs)) 1756 continue; 1757 1758 const MCOperand &Operand = Inst.getOperand(I); 1759 if (HasFramePointer && Operand.isReg() && SPBPAliases[Operand.getReg()]) { 1760 DoesLeak = true; 1761 break; 1762 } 1763 if (!HasFramePointer && Operand.isReg() && SPAliases[Operand.getReg()]) { 1764 DoesLeak = true; 1765 break; 1766 } 1767 } 1768 1769 // If potential leak, check if it is not just writing to itself/sp/bp 1770 if (DoesLeak) { 1771 for (int I = 0, E = NumDefs; I != E; ++I) { 1772 const MCOperand &Operand = Inst.getOperand(I); 1773 if (HasFramePointer && Operand.isReg() && 1774 SPBPAliases[Operand.getReg()]) { 1775 DoesLeak = false; 1776 break; 1777 } 1778 if (!HasFramePointer && Operand.isReg() && 1779 SPAliases[Operand.getReg()]) { 1780 DoesLeak = false; 1781 break; 1782 } 1783 } 1784 } 1785 return DoesLeak; 1786 } 1787 1788 bool addToImm(MCInst &Inst, int64_t &Amt, MCContext *Ctx) const override { 1789 unsigned ImmOpNo = -1U; 1790 int MemOpNo = getMemoryOperandNo(Inst); 1791 if (MemOpNo != -1) 1792 ImmOpNo = MemOpNo + X86::AddrDisp; 1793 else 1794 for (unsigned Index = 0; 1795 Index < MCPlus::getNumPrimeOperands(Inst); ++Index) 1796 if (Inst.getOperand(Index).isImm()) 1797 ImmOpNo = Index; 1798 if (ImmOpNo == -1U) 1799 return false; 1800 1801 MCOperand &Operand = Inst.getOperand(ImmOpNo); 1802 Amt += Operand.getImm(); 1803 Operand.setImm(Amt); 1804 // Check for the need for relaxation 1805 if (int64_t(Amt) == int64_t(int8_t(Amt))) 1806 return true; 1807 1808 // Relax instruction 1809 switch (Inst.getOpcode()) { 1810 case X86::SUB64ri8: 1811 Inst.setOpcode(X86::SUB64ri32); 1812 break; 1813 case X86::ADD64ri8: 1814 Inst.setOpcode(X86::ADD64ri32); 1815 break; 1816 default: 1817 // No need for relaxation 1818 break; 1819 } 1820 return true; 1821 } 1822 1823 /// TODO: this implementation currently works for the most common opcodes that 1824 /// load from memory. It can be extended to work with memory store opcodes as 1825 /// well as more memory load opcodes. 1826 bool replaceMemOperandWithImm(MCInst &Inst, StringRef ConstantData, 1827 uint64_t Offset) const override { 1828 enum CheckSignExt : uint8_t { 1829 NOCHECK = 0, 1830 CHECK8, 1831 CHECK32, 1832 }; 1833 1834 using CheckList = std::vector<std::pair<CheckSignExt, unsigned>>; 1835 struct InstInfo { 1836 // Size in bytes that Inst loads from memory. 1837 uint8_t DataSize; 1838 1839 // True when the target operand has to be duplicated because the opcode 1840 // expects a LHS operand. 1841 bool HasLHS; 1842 1843 // List of checks and corresponding opcodes to be used. We try to use the 1844 // smallest possible immediate value when various sizes are available, 1845 // hence we may need to check whether a larger constant fits in a smaller 1846 // immediate. 1847 CheckList Checks; 1848 }; 1849 1850 InstInfo I; 1851 1852 switch (Inst.getOpcode()) { 1853 default: { 1854 switch (getPopSize(Inst)) { 1855 case 2: I = {2, false, {{NOCHECK, X86::MOV16ri}}}; break; 1856 case 4: I = {4, false, {{NOCHECK, X86::MOV32ri}}}; break; 1857 case 8: I = {8, false, {{CHECK32, X86::MOV64ri32}, 1858 {NOCHECK, X86::MOV64rm}}}; break; 1859 default: return false; 1860 } 1861 break; 1862 } 1863 1864 // MOV 1865 case X86::MOV8rm: I = {1, false, {{NOCHECK, X86::MOV8ri}}}; break; 1866 case X86::MOV16rm: I = {2, false, {{NOCHECK, X86::MOV16ri}}}; break; 1867 case X86::MOV32rm: I = {4, false, {{NOCHECK, X86::MOV32ri}}}; break; 1868 case X86::MOV64rm: I = {8, false, {{CHECK32, X86::MOV64ri32}, 1869 {NOCHECK, X86::MOV64rm}}}; break; 1870 1871 // MOVZX 1872 case X86::MOVZX16rm8: I = {1, false, {{NOCHECK, X86::MOV16ri}}}; break; 1873 case X86::MOVZX32rm8: I = {1, false, {{NOCHECK, X86::MOV32ri}}}; break; 1874 case X86::MOVZX32rm16: I = {2, false, {{NOCHECK, X86::MOV32ri}}}; break; 1875 1876 // CMP 1877 case X86::CMP8rm: I = {1, false, {{NOCHECK, X86::CMP8ri}}}; break; 1878 case X86::CMP16rm: I = {2, false, {{CHECK8, X86::CMP16ri8}, 1879 {NOCHECK, X86::CMP16ri}}}; break; 1880 case X86::CMP32rm: I = {4, false, {{CHECK8, X86::CMP32ri8}, 1881 {NOCHECK, X86::CMP32ri}}}; break; 1882 case X86::CMP64rm: I = {8, false, {{CHECK8, X86::CMP64ri8}, 1883 {CHECK32, X86::CMP64ri32}, 1884 {NOCHECK, X86::CMP64rm}}}; break; 1885 1886 // TEST 1887 case X86::TEST8mr: I = {1, false, {{NOCHECK, X86::TEST8ri}}}; break; 1888 case X86::TEST16mr: I = {2, false, {{NOCHECK, X86::TEST16ri}}}; break; 1889 case X86::TEST32mr: I = {4, false, {{NOCHECK, X86::TEST32ri}}}; break; 1890 case X86::TEST64mr: I = {8, false, {{CHECK32, X86::TEST64ri32}, 1891 {NOCHECK, X86::TEST64mr}}}; break; 1892 1893 // ADD 1894 case X86::ADD8rm: I = {1, true, {{NOCHECK, X86::ADD8ri}}}; break; 1895 case X86::ADD16rm: I = {2, true, {{CHECK8, X86::ADD16ri8}, 1896 {NOCHECK, X86::ADD16ri}}}; break; 1897 case X86::ADD32rm: I = {4, true, {{CHECK8, X86::ADD32ri8}, 1898 {NOCHECK, X86::ADD32ri}}}; break; 1899 case X86::ADD64rm: I = {8, true, {{CHECK8, X86::ADD64ri8}, 1900 {CHECK32, X86::ADD64ri32}, 1901 {NOCHECK, X86::ADD64rm}}}; break; 1902 1903 // SUB 1904 case X86::SUB8rm: I = {1, true, {{NOCHECK, X86::SUB8ri}}}; break; 1905 case X86::SUB16rm: I = {2, true, {{CHECK8, X86::SUB16ri8}, 1906 {NOCHECK, X86::SUB16ri}}}; break; 1907 case X86::SUB32rm: I = {4, true, {{CHECK8, X86::SUB32ri8}, 1908 {NOCHECK, X86::SUB32ri}}}; break; 1909 case X86::SUB64rm: I = {8, true, {{CHECK8, X86::SUB64ri8}, 1910 {CHECK32, X86::SUB64ri32}, 1911 {NOCHECK, X86::SUB64rm}}}; break; 1912 1913 // AND 1914 case X86::AND8rm: I = {1, true, {{NOCHECK, X86::AND8ri}}}; break; 1915 case X86::AND16rm: I = {2, true, {{CHECK8, X86::AND16ri8}, 1916 {NOCHECK, X86::AND16ri}}}; break; 1917 case X86::AND32rm: I = {4, true, {{CHECK8, X86::AND32ri8}, 1918 {NOCHECK, X86::AND32ri}}}; break; 1919 case X86::AND64rm: I = {8, true, {{CHECK8, X86::AND64ri8}, 1920 {CHECK32, X86::AND64ri32}, 1921 {NOCHECK, X86::AND64rm}}}; break; 1922 1923 // OR 1924 case X86::OR8rm: I = {1, true, {{NOCHECK, X86::OR8ri}}}; break; 1925 case X86::OR16rm: I = {2, true, {{CHECK8, X86::OR16ri8}, 1926 {NOCHECK, X86::OR16ri}}}; break; 1927 case X86::OR32rm: I = {4, true, {{CHECK8, X86::OR32ri8}, 1928 {NOCHECK, X86::OR32ri}}}; break; 1929 case X86::OR64rm: I = {8, true, {{CHECK8, X86::OR64ri8}, 1930 {CHECK32, X86::OR64ri32}, 1931 {NOCHECK, X86::OR64rm}}}; break; 1932 1933 // XOR 1934 case X86::XOR8rm: I = {1, true, {{NOCHECK, X86::XOR8ri}}}; break; 1935 case X86::XOR16rm: I = {2, true, {{CHECK8, X86::XOR16ri8}, 1936 {NOCHECK, X86::XOR16ri}}}; break; 1937 case X86::XOR32rm: I = {4, true, {{CHECK8, X86::XOR32ri8}, 1938 {NOCHECK, X86::XOR32ri}}}; break; 1939 case X86::XOR64rm: I = {8, true, {{CHECK8, X86::XOR64ri8}, 1940 {CHECK32, X86::XOR64ri32}, 1941 {NOCHECK, X86::XOR64rm}}}; break; 1942 } 1943 1944 // Compute the immediate value. 1945 assert(Offset + I.DataSize <= ConstantData.size() && 1946 "invalid offset for given constant data"); 1947 int64_t ImmVal = 1948 DataExtractor(ConstantData, true, 8).getSigned(&Offset, I.DataSize); 1949 1950 // Compute the new opcode. 1951 unsigned NewOpcode = 0; 1952 for (const std::pair<CheckSignExt, unsigned> &Check : I.Checks) { 1953 NewOpcode = Check.second; 1954 if (Check.first == NOCHECK) 1955 break; 1956 if (Check.first == CHECK8 && 1957 ImmVal >= std::numeric_limits<int8_t>::min() && 1958 ImmVal <= std::numeric_limits<int8_t>::max()) 1959 break; 1960 if (Check.first == CHECK32 && 1961 ImmVal >= std::numeric_limits<int32_t>::min() && 1962 ImmVal <= std::numeric_limits<int32_t>::max()) 1963 break; 1964 } 1965 if (NewOpcode == Inst.getOpcode()) 1966 return false; 1967 1968 // Modify the instruction. 1969 MCOperand ImmOp = MCOperand::createImm(ImmVal); 1970 uint32_t TargetOpNum = 0; 1971 // Test instruction does not follow the regular pattern of putting the 1972 // memory reference of a load (5 MCOperands) last in the list of operands. 1973 // Since it is not modifying the register operand, it is not treated as 1974 // a destination operand and it is not the first operand as it is in the 1975 // other instructions we treat here. 1976 if (NewOpcode == X86::TEST8ri || 1977 NewOpcode == X86::TEST16ri || 1978 NewOpcode == X86::TEST32ri || 1979 NewOpcode == X86::TEST64ri32) 1980 TargetOpNum = getMemoryOperandNo(Inst) + X86::AddrNumOperands; 1981 1982 MCOperand TargetOp = Inst.getOperand(TargetOpNum); 1983 Inst.clear(); 1984 Inst.setOpcode(NewOpcode); 1985 Inst.addOperand(TargetOp); 1986 if (I.HasLHS) 1987 Inst.addOperand(TargetOp); 1988 Inst.addOperand(ImmOp); 1989 1990 return true; 1991 } 1992 1993 /// TODO: this implementation currently works for the most common opcodes that 1994 /// load from memory. It can be extended to work with memory store opcodes as 1995 /// well as more memory load opcodes. 1996 bool replaceMemOperandWithReg(MCInst &Inst, MCPhysReg RegNum) const override { 1997 unsigned NewOpcode; 1998 1999 switch (Inst.getOpcode()) { 2000 default: { 2001 switch (getPopSize(Inst)) { 2002 case 2: NewOpcode = X86::MOV16rr; break; 2003 case 4: NewOpcode = X86::MOV32rr; break; 2004 case 8: NewOpcode = X86::MOV64rr; break; 2005 default: return false; 2006 } 2007 break; 2008 } 2009 2010 // MOV 2011 case X86::MOV8rm: NewOpcode = X86::MOV8rr; break; 2012 case X86::MOV16rm: NewOpcode = X86::MOV16rr; break; 2013 case X86::MOV32rm: NewOpcode = X86::MOV32rr; break; 2014 case X86::MOV64rm: NewOpcode = X86::MOV64rr; break; 2015 } 2016 2017 // Modify the instruction. 2018 MCOperand RegOp = MCOperand::createReg(RegNum); 2019 MCOperand TargetOp = Inst.getOperand(0); 2020 Inst.clear(); 2021 Inst.setOpcode(NewOpcode); 2022 Inst.addOperand(TargetOp); 2023 Inst.addOperand(RegOp); 2024 2025 return true; 2026 } 2027 2028 bool isRedundantMove(const MCInst &Inst) const override { 2029 switch (Inst.getOpcode()) { 2030 default: 2031 return false; 2032 2033 // MOV 2034 case X86::MOV8rr: 2035 case X86::MOV16rr: 2036 case X86::MOV32rr: 2037 case X86::MOV64rr: 2038 break; 2039 } 2040 2041 assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg()); 2042 return Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg(); 2043 } 2044 2045 bool requiresAlignedAddress(const MCInst &Inst) const override { 2046 const MCInstrDesc &Desc = Info->get(Inst.getOpcode()); 2047 for (unsigned int I = 0; I < Desc.getNumOperands(); ++I) { 2048 const MCOperandInfo &Op = Desc.OpInfo[I]; 2049 if (Op.OperandType != MCOI::OPERAND_REGISTER) 2050 continue; 2051 if (Op.RegClass == X86::VR128RegClassID) 2052 return true; 2053 } 2054 return false; 2055 } 2056 2057 bool convertJmpToTailCall(MCInst &Inst) override { 2058 if (isTailCall(Inst)) 2059 return false; 2060 2061 int NewOpcode; 2062 switch (Inst.getOpcode()) { 2063 default: 2064 return false; 2065 case X86::JMP_1: 2066 case X86::JMP_2: 2067 case X86::JMP_4: 2068 NewOpcode = X86::JMP_4; 2069 break; 2070 case X86::JMP16m: 2071 case X86::JMP32m: 2072 case X86::JMP64m: 2073 NewOpcode = X86::JMP32m; 2074 break; 2075 case X86::JMP16r: 2076 case X86::JMP32r: 2077 case X86::JMP64r: 2078 NewOpcode = X86::JMP32r; 2079 break; 2080 } 2081 2082 Inst.setOpcode(NewOpcode); 2083 setTailCall(Inst); 2084 return true; 2085 } 2086 2087 bool convertTailCallToJmp(MCInst &Inst) override { 2088 int NewOpcode; 2089 switch (Inst.getOpcode()) { 2090 default: 2091 return false; 2092 case X86::JMP_4: 2093 NewOpcode = X86::JMP_1; 2094 break; 2095 case X86::JMP32m: 2096 NewOpcode = X86::JMP64m; 2097 break; 2098 case X86::JMP32r: 2099 NewOpcode = X86::JMP64r; 2100 break; 2101 } 2102 2103 Inst.setOpcode(NewOpcode); 2104 removeAnnotation(Inst, MCPlus::MCAnnotation::kTailCall); 2105 removeAnnotation(Inst, "Offset"); 2106 return true; 2107 } 2108 2109 bool convertTailCallToCall(MCInst &Inst) override { 2110 int NewOpcode; 2111 switch (Inst.getOpcode()) { 2112 default: 2113 return false; 2114 case X86::JMP_4: 2115 NewOpcode = X86::CALL64pcrel32; 2116 break; 2117 case X86::JMP32m: 2118 NewOpcode = X86::CALL64m; 2119 break; 2120 case X86::JMP32r: 2121 NewOpcode = X86::CALL64r; 2122 break; 2123 } 2124 2125 Inst.setOpcode(NewOpcode); 2126 removeAnnotation(Inst, MCPlus::MCAnnotation::kTailCall); 2127 return true; 2128 } 2129 2130 bool convertCallToIndirectCall(MCInst &Inst, 2131 const MCSymbol *TargetLocation, 2132 MCContext *Ctx) override { 2133 bool IsTailCall = isTailCall(Inst); 2134 assert((Inst.getOpcode() == X86::CALL64pcrel32 || 2135 (Inst.getOpcode() == X86::JMP_4 && IsTailCall)) && 2136 "64-bit direct (tail) call instruction expected"); 2137 const auto NewOpcode = (Inst.getOpcode() == X86::CALL64pcrel32) 2138 ? X86::CALL64m 2139 : X86::JMP32m; 2140 Inst.setOpcode(NewOpcode); 2141 2142 // Replace the first operand and preserve auxiliary operands of 2143 // the instruction. 2144 Inst.erase(Inst.begin()); 2145 Inst.insert(Inst.begin(), 2146 MCOperand::createReg(X86::NoRegister)); // AddrSegmentReg 2147 Inst.insert(Inst.begin(), 2148 MCOperand::createExpr( // Displacement 2149 MCSymbolRefExpr::create(TargetLocation, 2150 MCSymbolRefExpr::VK_None, 2151 *Ctx))); 2152 Inst.insert(Inst.begin(), 2153 MCOperand::createReg(X86::NoRegister)); // IndexReg 2154 Inst.insert(Inst.begin(), 2155 MCOperand::createImm(1)); // ScaleAmt 2156 Inst.insert(Inst.begin(), 2157 MCOperand::createReg(X86::RIP)); // BaseReg 2158 2159 return true; 2160 } 2161 2162 void convertIndirectCallToLoad(MCInst &Inst, MCPhysReg Reg) override { 2163 bool IsTailCall = isTailCall(Inst); 2164 if (IsTailCall) 2165 removeAnnotation(Inst, MCPlus::MCAnnotation::kTailCall); 2166 if (Inst.getOpcode() == X86::CALL64m || 2167 (Inst.getOpcode() == X86::JMP32m && IsTailCall)) { 2168 Inst.setOpcode(X86::MOV64rm); 2169 Inst.insert(Inst.begin(), MCOperand::createReg(Reg)); 2170 return; 2171 } 2172 if (Inst.getOpcode() == X86::CALL64r || 2173 (Inst.getOpcode() == X86::JMP32r && IsTailCall)) { 2174 Inst.setOpcode(X86::MOV64rr); 2175 Inst.insert(Inst.begin(), MCOperand::createReg(Reg)); 2176 return; 2177 } 2178 LLVM_DEBUG(Inst.dump()); 2179 llvm_unreachable("not implemented"); 2180 } 2181 2182 bool shortenInstruction(MCInst &Inst) const override { 2183 unsigned OldOpcode = Inst.getOpcode(); 2184 unsigned NewOpcode = OldOpcode; 2185 2186 // Check and remove EIZ/RIZ. These cases represent ambiguous cases where SIB 2187 // byte is present, but no index is used and modrm alone shoud have been 2188 // enough. Converting to NoRegister effectively removes the SIB byte. 2189 int MemOpNo = getMemoryOperandNo(Inst); 2190 if (MemOpNo >= 0) { 2191 MCOperand &IndexOp = 2192 Inst.getOperand(static_cast<unsigned>(MemOpNo) + X86::AddrIndexReg); 2193 if (IndexOp.getReg() == X86::EIZ || 2194 IndexOp.getReg() == X86::RIZ) 2195 IndexOp = MCOperand::createReg(X86::NoRegister); 2196 } 2197 2198 if (isBranch(Inst)) { 2199 NewOpcode = getShortBranchOpcode(OldOpcode); 2200 } else if (OldOpcode == X86::MOV64ri) { 2201 if (Inst.getOperand(MCPlus::getNumPrimeOperands(Inst) - 1).isImm()) { 2202 const int64_t Imm = 2203 Inst.getOperand(MCPlus::getNumPrimeOperands(Inst) - 1).getImm(); 2204 if (int64_t(Imm) == int64_t(int32_t(Imm))) 2205 NewOpcode = X86::MOV64ri32; 2206 } 2207 } else { 2208 // If it's arithmetic instruction check if signed operand fits in 1 byte. 2209 const unsigned ShortOpcode = getShortArithOpcode(OldOpcode); 2210 if (ShortOpcode != OldOpcode && 2211 Inst.getOperand(MCPlus::getNumPrimeOperands(Inst) - 1).isImm()) { 2212 int64_t Imm = 2213 Inst.getOperand(MCPlus::getNumPrimeOperands(Inst) - 1).getImm(); 2214 if (int64_t(Imm) == int64_t(int8_t(Imm))) 2215 NewOpcode = ShortOpcode; 2216 } 2217 } 2218 2219 if (NewOpcode == OldOpcode) 2220 return false; 2221 2222 Inst.setOpcode(NewOpcode); 2223 return true; 2224 } 2225 2226 bool lowerTailCall(MCInst &Inst) override { 2227 if (Inst.getOpcode() == X86::JMP_4 && isTailCall(Inst)) { 2228 Inst.setOpcode(X86::JMP_1); 2229 removeAnnotation(Inst, MCPlus::MCAnnotation::kTailCall); 2230 return true; 2231 } 2232 return false; 2233 } 2234 2235 const MCSymbol *getTargetSymbol(const MCInst &Inst, 2236 unsigned OpNum = 0) const override { 2237 if (OpNum >= MCPlus::getNumPrimeOperands(Inst)) 2238 return nullptr; 2239 2240 const MCOperand &Op = Inst.getOperand(OpNum); 2241 if (!Op.isExpr()) 2242 return nullptr; 2243 2244 auto *SymExpr = dyn_cast<MCSymbolRefExpr>(Op.getExpr()); 2245 if (!SymExpr || SymExpr->getKind() != MCSymbolRefExpr::VK_None) 2246 return nullptr; 2247 2248 return &SymExpr->getSymbol(); 2249 } 2250 2251 // This is the same as the base class, but since we are overriding one of 2252 // getTargetSymbol's signatures above, we need to override all of them. 2253 const MCSymbol *getTargetSymbol(const MCExpr *Expr) const override { 2254 return &cast<const MCSymbolRefExpr>(Expr)->getSymbol(); 2255 } 2256 2257 bool analyzeBranch(InstructionIterator Begin, 2258 InstructionIterator End, 2259 const MCSymbol *&TBB, 2260 const MCSymbol *&FBB, 2261 MCInst *&CondBranch, 2262 MCInst *&UncondBranch) const override { 2263 auto I = End; 2264 2265 // Bottom-up analysis 2266 while (I != Begin) { 2267 --I; 2268 2269 // Ignore nops and CFIs 2270 if (isPseudo(*I)) 2271 continue; 2272 2273 // Stop when we find the first non-terminator 2274 if (!isTerminator(*I)) 2275 break; 2276 2277 if (!isBranch(*I)) 2278 break; 2279 2280 // Handle unconditional branches. 2281 if ((I->getOpcode() == X86::JMP_1 || 2282 I->getOpcode() == X86::JMP_2 || 2283 I->getOpcode() == X86::JMP_4) && 2284 !isTailCall(*I)) { 2285 // If any code was seen after this unconditional branch, we've seen 2286 // unreachable code. Ignore them. 2287 CondBranch = nullptr; 2288 UncondBranch = &*I; 2289 const MCSymbol *Sym = getTargetSymbol(*I); 2290 assert(Sym != nullptr && 2291 "Couldn't extract BB symbol from jump operand"); 2292 TBB = Sym; 2293 continue; 2294 } 2295 2296 // Handle conditional branches and ignore indirect branches 2297 if (!isUnsupportedBranch(I->getOpcode()) && 2298 getCondCode(*I) == X86::COND_INVALID) { 2299 // Indirect branch 2300 return false; 2301 } 2302 2303 if (CondBranch == nullptr) { 2304 const MCSymbol *TargetBB = getTargetSymbol(*I); 2305 if (TargetBB == nullptr) { 2306 // Unrecognized branch target 2307 return false; 2308 } 2309 FBB = TBB; 2310 TBB = TargetBB; 2311 CondBranch = &*I; 2312 continue; 2313 } 2314 2315 llvm_unreachable("multiple conditional branches in one BB"); 2316 } 2317 return true; 2318 } 2319 2320 template <typename Itr> 2321 std::pair<IndirectBranchType, MCInst *> 2322 analyzePICJumpTable(Itr II, 2323 Itr IE, 2324 MCPhysReg R1, 2325 MCPhysReg R2) const { 2326 // Analyze PIC-style jump table code template: 2327 // 2328 // lea PIC_JUMP_TABLE(%rip), {%r1|%r2} <- MemLocInstr 2329 // mov ({%r1|%r2}, %index, 4), {%r2|%r1} 2330 // add %r2, %r1 2331 // jmp *%r1 2332 // 2333 // (with any irrelevant instructions in-between) 2334 // 2335 // When we call this helper we've already determined %r1 and %r2, and 2336 // reverse instruction iterator \p II is pointing to the ADD instruction. 2337 // 2338 // PIC jump table looks like following: 2339 // 2340 // JT: ---------- 2341 // E1:| L1 - JT | 2342 // |----------| 2343 // E2:| L2 - JT | 2344 // |----------| 2345 // | | 2346 // ...... 2347 // En:| Ln - JT | 2348 // ---------- 2349 // 2350 // Where L1, L2, ..., Ln represent labels in the function. 2351 // 2352 // The actual relocations in the table will be of the form: 2353 // 2354 // Ln - JT 2355 // = (Ln - En) + (En - JT) 2356 // = R_X86_64_PC32(Ln) + En - JT 2357 // = R_X86_64_PC32(Ln + offsetof(En)) 2358 // 2359 LLVM_DEBUG(dbgs() << "Checking for PIC jump table\n"); 2360 MCInst *MemLocInstr = nullptr; 2361 const MCInst *MovInstr = nullptr; 2362 while (++II != IE) { 2363 MCInst &Instr = *II; 2364 const MCInstrDesc &InstrDesc = Info->get(Instr.getOpcode()); 2365 if (!InstrDesc.hasDefOfPhysReg(Instr, R1, *RegInfo) && 2366 !InstrDesc.hasDefOfPhysReg(Instr, R2, *RegInfo)) { 2367 // Ignore instructions that don't affect R1, R2 registers. 2368 continue; 2369 } 2370 if (!MovInstr) { 2371 // Expect to see MOV instruction. 2372 if (!isMOVSX64rm32(Instr)) { 2373 LLVM_DEBUG(dbgs() << "MOV instruction expected.\n"); 2374 break; 2375 } 2376 2377 // Check if it's setting %r1 or %r2. In canonical form it sets %r2. 2378 // If it sets %r1 - rename the registers so we have to only check 2379 // a single form. 2380 unsigned MovDestReg = Instr.getOperand(0).getReg(); 2381 if (MovDestReg != R2) 2382 std::swap(R1, R2); 2383 if (MovDestReg != R2) { 2384 LLVM_DEBUG(dbgs() << "MOV instruction expected to set %r2\n"); 2385 break; 2386 } 2387 2388 // Verify operands for MOV. 2389 unsigned BaseRegNum; 2390 int64_t ScaleValue; 2391 unsigned IndexRegNum; 2392 int64_t DispValue; 2393 unsigned SegRegNum; 2394 if (!evaluateX86MemoryOperand(Instr, &BaseRegNum, 2395 &ScaleValue, &IndexRegNum, 2396 &DispValue, &SegRegNum)) 2397 break; 2398 if (BaseRegNum != R1 || 2399 ScaleValue != 4 || 2400 IndexRegNum == X86::NoRegister || 2401 DispValue != 0 || 2402 SegRegNum != X86::NoRegister) 2403 break; 2404 MovInstr = &Instr; 2405 } else { 2406 if (!InstrDesc.hasDefOfPhysReg(Instr, R1, *RegInfo)) 2407 continue; 2408 if (!isLEA64r(Instr)) { 2409 LLVM_DEBUG(dbgs() << "LEA instruction expected\n"); 2410 break; 2411 } 2412 if (Instr.getOperand(0).getReg() != R1) { 2413 LLVM_DEBUG(dbgs() << "LEA instruction expected to set %r1\n"); 2414 break; 2415 } 2416 2417 // Verify operands for LEA. 2418 unsigned BaseRegNum; 2419 int64_t ScaleValue; 2420 unsigned IndexRegNum; 2421 const MCExpr *DispExpr = nullptr; 2422 int64_t DispValue; 2423 unsigned SegRegNum; 2424 if (!evaluateX86MemoryOperand(Instr, &BaseRegNum, 2425 &ScaleValue, &IndexRegNum, 2426 &DispValue, &SegRegNum, &DispExpr)) 2427 break; 2428 if (BaseRegNum != RegInfo->getProgramCounter() || 2429 IndexRegNum != X86::NoRegister || 2430 SegRegNum != X86::NoRegister || 2431 DispExpr == nullptr) 2432 break; 2433 MemLocInstr = &Instr; 2434 break; 2435 } 2436 } 2437 2438 if (!MemLocInstr) 2439 return std::make_pair(IndirectBranchType::UNKNOWN, nullptr); 2440 2441 LLVM_DEBUG(dbgs() << "checking potential PIC jump table\n"); 2442 return std::make_pair(IndirectBranchType::POSSIBLE_PIC_JUMP_TABLE, 2443 MemLocInstr); 2444 } 2445 2446 IndirectBranchType analyzeIndirectBranch( 2447 MCInst &Instruction, 2448 InstructionIterator Begin, 2449 InstructionIterator End, 2450 const unsigned PtrSize, 2451 MCInst *&MemLocInstrOut, 2452 unsigned &BaseRegNumOut, 2453 unsigned &IndexRegNumOut, 2454 int64_t &DispValueOut, 2455 const MCExpr *&DispExprOut, 2456 MCInst *&PCRelBaseOut 2457 ) const override { 2458 // Try to find a (base) memory location from where the address for 2459 // the indirect branch is loaded. For X86-64 the memory will be specified 2460 // in the following format: 2461 // 2462 // {%rip}/{%basereg} + Imm + IndexReg * Scale 2463 // 2464 // We are interested in the cases where Scale == sizeof(uintptr_t) and 2465 // the contents of the memory are presumably an array of pointers to code. 2466 // 2467 // Normal jump table: 2468 // 2469 // jmp *(JUMP_TABLE, %index, Scale) <- MemLocInstr 2470 // 2471 // or 2472 // 2473 // mov (JUMP_TABLE, %index, Scale), %r1 <- MemLocInstr 2474 // ... 2475 // jmp %r1 2476 // 2477 // We handle PIC-style jump tables separately. 2478 // 2479 MemLocInstrOut = nullptr; 2480 BaseRegNumOut = X86::NoRegister; 2481 IndexRegNumOut = X86::NoRegister; 2482 DispValueOut = 0; 2483 DispExprOut = nullptr; 2484 2485 std::reverse_iterator<InstructionIterator> II(End); 2486 std::reverse_iterator<InstructionIterator> IE(Begin); 2487 2488 IndirectBranchType Type = IndirectBranchType::UNKNOWN; 2489 2490 // An instruction referencing memory used by jump instruction (directly or 2491 // via register). This location could be an array of function pointers 2492 // in case of indirect tail call, or a jump table. 2493 MCInst *MemLocInstr = nullptr; 2494 2495 if (MCPlus::getNumPrimeOperands(Instruction) == 1) { 2496 // If the indirect jump is on register - try to detect if the 2497 // register value is loaded from a memory location. 2498 assert(Instruction.getOperand(0).isReg() && "register operand expected"); 2499 const unsigned R1 = Instruction.getOperand(0).getReg(); 2500 // Check if one of the previous instructions defines the jump-on register. 2501 for (auto PrevII = II; PrevII != IE; ++PrevII) { 2502 MCInst &PrevInstr = *PrevII; 2503 const MCInstrDesc &PrevInstrDesc = Info->get(PrevInstr.getOpcode()); 2504 2505 if (!PrevInstrDesc.hasDefOfPhysReg(PrevInstr, R1, *RegInfo)) 2506 continue; 2507 2508 if (isMoveMem2Reg(PrevInstr)) { 2509 MemLocInstr = &PrevInstr; 2510 break; 2511 } 2512 if (isADD64rr(PrevInstr)) { 2513 unsigned R2 = PrevInstr.getOperand(2).getReg(); 2514 if (R1 == R2) 2515 return IndirectBranchType::UNKNOWN; 2516 std::tie(Type, MemLocInstr) = analyzePICJumpTable(PrevII, IE, R1, R2); 2517 break; 2518 } 2519 return IndirectBranchType::UNKNOWN; 2520 } 2521 if (!MemLocInstr) { 2522 // No definition seen for the register in this function so far. Could be 2523 // an input parameter - which means it is an external code reference. 2524 // It also could be that the definition happens to be in the code that 2525 // we haven't processed yet. Since we have to be conservative, return 2526 // as UNKNOWN case. 2527 return IndirectBranchType::UNKNOWN; 2528 } 2529 } else { 2530 MemLocInstr = &Instruction; 2531 } 2532 2533 const MCRegister RIPRegister = RegInfo->getProgramCounter(); 2534 2535 // Analyze the memory location. 2536 unsigned BaseRegNum, IndexRegNum, SegRegNum; 2537 int64_t ScaleValue, DispValue; 2538 const MCExpr *DispExpr; 2539 2540 if (!evaluateX86MemoryOperand(*MemLocInstr, &BaseRegNum, 2541 &ScaleValue, &IndexRegNum, 2542 &DispValue, &SegRegNum, 2543 &DispExpr)) 2544 return IndirectBranchType::UNKNOWN; 2545 2546 BaseRegNumOut = BaseRegNum; 2547 IndexRegNumOut = IndexRegNum; 2548 DispValueOut = DispValue; 2549 DispExprOut = DispExpr; 2550 2551 if ((BaseRegNum != X86::NoRegister && BaseRegNum != RIPRegister) || 2552 SegRegNum != X86::NoRegister) 2553 return IndirectBranchType::UNKNOWN; 2554 2555 if (MemLocInstr == &Instruction && 2556 (!ScaleValue || IndexRegNum == X86::NoRegister)) { 2557 MemLocInstrOut = MemLocInstr; 2558 return IndirectBranchType::POSSIBLE_FIXED_BRANCH; 2559 } 2560 2561 if (Type == IndirectBranchType::POSSIBLE_PIC_JUMP_TABLE && 2562 (ScaleValue != 1 || BaseRegNum != RIPRegister)) 2563 return IndirectBranchType::UNKNOWN; 2564 2565 if (Type != IndirectBranchType::POSSIBLE_PIC_JUMP_TABLE && 2566 ScaleValue != PtrSize) 2567 return IndirectBranchType::UNKNOWN; 2568 2569 MemLocInstrOut = MemLocInstr; 2570 2571 return Type; 2572 } 2573 2574 /// Analyze a callsite to see if it could be a virtual method call. This only 2575 /// checks to see if the overall pattern is satisfied, it does not guarantee 2576 /// that the callsite is a true virtual method call. 2577 /// The format of virtual method calls that are recognized is one of the 2578 /// following: 2579 /// 2580 /// Form 1: (found in debug code) 2581 /// add METHOD_OFFSET, %VtableReg 2582 /// mov (%VtableReg), %MethodReg 2583 /// ... 2584 /// call or jmp *%MethodReg 2585 /// 2586 /// Form 2: 2587 /// mov METHOD_OFFSET(%VtableReg), %MethodReg 2588 /// ... 2589 /// call or jmp *%MethodReg 2590 /// 2591 /// Form 3: 2592 /// ... 2593 /// call or jmp *METHOD_OFFSET(%VtableReg) 2594 /// 2595 bool analyzeVirtualMethodCall(InstructionIterator ForwardBegin, 2596 InstructionIterator ForwardEnd, 2597 std::vector<MCInst *> &MethodFetchInsns, 2598 unsigned &VtableRegNum, 2599 unsigned &MethodRegNum, 2600 uint64_t &MethodOffset) const override { 2601 VtableRegNum = X86::NoRegister; 2602 MethodRegNum = X86::NoRegister; 2603 MethodOffset = 0; 2604 2605 std::reverse_iterator<InstructionIterator> Itr(ForwardEnd); 2606 std::reverse_iterator<InstructionIterator> End(ForwardBegin); 2607 2608 MCInst &CallInst = *Itr++; 2609 assert(isIndirectBranch(CallInst) || isCall(CallInst)); 2610 2611 unsigned BaseReg, IndexReg, SegmentReg; 2612 int64_t Scale, Disp; 2613 const MCExpr *DispExpr; 2614 2615 // The call can just be jmp offset(reg) 2616 if (evaluateX86MemoryOperand(CallInst, 2617 &BaseReg, 2618 &Scale, 2619 &IndexReg, 2620 &Disp, 2621 &SegmentReg, 2622 &DispExpr)) { 2623 if (!DispExpr && 2624 BaseReg != X86::RIP && 2625 BaseReg != X86::RBP && 2626 BaseReg != X86::NoRegister) { 2627 MethodRegNum = BaseReg; 2628 if (Scale == 1 && 2629 IndexReg == X86::NoRegister && 2630 SegmentReg == X86::NoRegister) { 2631 VtableRegNum = MethodRegNum; 2632 MethodOffset = Disp; 2633 MethodFetchInsns.push_back(&CallInst); 2634 return true; 2635 } 2636 } 2637 return false; 2638 } 2639 if (CallInst.getOperand(0).isReg()) 2640 MethodRegNum = CallInst.getOperand(0).getReg(); 2641 else 2642 return false; 2643 2644 if (MethodRegNum == X86::RIP || MethodRegNum == X86::RBP) { 2645 VtableRegNum = X86::NoRegister; 2646 MethodRegNum = X86::NoRegister; 2647 return false; 2648 } 2649 2650 // find load from vtable, this may or may not include the method offset 2651 while (Itr != End) { 2652 MCInst &CurInst = *Itr++; 2653 const MCInstrDesc &Desc = Info->get(CurInst.getOpcode()); 2654 if (Desc.hasDefOfPhysReg(CurInst, MethodRegNum, *RegInfo)) { 2655 if (isLoad(CurInst) && 2656 evaluateX86MemoryOperand(CurInst, 2657 &BaseReg, 2658 &Scale, 2659 &IndexReg, 2660 &Disp, 2661 &SegmentReg, 2662 &DispExpr)) { 2663 if (!DispExpr && 2664 Scale == 1 && 2665 BaseReg != X86::RIP && 2666 BaseReg != X86::RBP && 2667 BaseReg != X86::NoRegister && 2668 IndexReg == X86::NoRegister && 2669 SegmentReg == X86::NoRegister && 2670 BaseReg != X86::RIP) { 2671 VtableRegNum = BaseReg; 2672 MethodOffset = Disp; 2673 MethodFetchInsns.push_back(&CurInst); 2674 if (MethodOffset != 0) 2675 return true; 2676 break; 2677 } 2678 } 2679 return false; 2680 } 2681 } 2682 2683 if (!VtableRegNum) 2684 return false; 2685 2686 // look for any adds affecting the method register. 2687 while (Itr != End) { 2688 MCInst &CurInst = *Itr++; 2689 const MCInstrDesc &Desc = Info->get(CurInst.getOpcode()); 2690 if (Desc.hasDefOfPhysReg(CurInst, VtableRegNum, *RegInfo)) { 2691 if (isADDri(CurInst)) { 2692 assert(!MethodOffset); 2693 MethodOffset = CurInst.getOperand(2).getImm(); 2694 MethodFetchInsns.insert(MethodFetchInsns.begin(), &CurInst); 2695 break; 2696 } 2697 } 2698 } 2699 2700 return true; 2701 } 2702 2703 bool createStackPointerIncrement(MCInst &Inst, int Size, 2704 bool NoFlagsClobber) const override { 2705 if (NoFlagsClobber) { 2706 Inst.setOpcode(X86::LEA64r); 2707 Inst.clear(); 2708 Inst.addOperand(MCOperand::createReg(X86::RSP)); 2709 Inst.addOperand(MCOperand::createReg(X86::RSP)); // BaseReg 2710 Inst.addOperand(MCOperand::createImm(1)); // ScaleAmt 2711 Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // IndexReg 2712 Inst.addOperand(MCOperand::createImm(-Size)); // Displacement 2713 Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // AddrSegmentReg 2714 return true; 2715 } 2716 Inst.setOpcode(X86::SUB64ri8); 2717 Inst.clear(); 2718 Inst.addOperand(MCOperand::createReg(X86::RSP)); 2719 Inst.addOperand(MCOperand::createReg(X86::RSP)); 2720 Inst.addOperand(MCOperand::createImm(Size)); 2721 return true; 2722 } 2723 2724 bool createStackPointerDecrement(MCInst &Inst, int Size, 2725 bool NoFlagsClobber) const override { 2726 if (NoFlagsClobber) { 2727 Inst.setOpcode(X86::LEA64r); 2728 Inst.clear(); 2729 Inst.addOperand(MCOperand::createReg(X86::RSP)); 2730 Inst.addOperand(MCOperand::createReg(X86::RSP)); // BaseReg 2731 Inst.addOperand(MCOperand::createImm(1)); // ScaleAmt 2732 Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // IndexReg 2733 Inst.addOperand(MCOperand::createImm(Size)); // Displacement 2734 Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // AddrSegmentReg 2735 return true; 2736 } 2737 Inst.setOpcode(X86::ADD64ri8); 2738 Inst.clear(); 2739 Inst.addOperand(MCOperand::createReg(X86::RSP)); 2740 Inst.addOperand(MCOperand::createReg(X86::RSP)); 2741 Inst.addOperand(MCOperand::createImm(Size)); 2742 return true; 2743 } 2744 2745 bool createSaveToStack(MCInst &Inst, const MCPhysReg &StackReg, int Offset, 2746 const MCPhysReg &SrcReg, int Size) const override { 2747 unsigned NewOpcode; 2748 switch (Size) { 2749 default: 2750 return false; 2751 case 2: NewOpcode = X86::MOV16mr; break; 2752 case 4: NewOpcode = X86::MOV32mr; break; 2753 case 8: NewOpcode = X86::MOV64mr; break; 2754 } 2755 Inst.setOpcode(NewOpcode); 2756 Inst.clear(); 2757 Inst.addOperand(MCOperand::createReg(StackReg)); // BaseReg 2758 Inst.addOperand(MCOperand::createImm(1)); // ScaleAmt 2759 Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // IndexReg 2760 Inst.addOperand(MCOperand::createImm(Offset)); // Displacement 2761 Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // AddrSegmentReg 2762 Inst.addOperand(MCOperand::createReg(SrcReg)); 2763 return true; 2764 } 2765 2766 bool createRestoreFromStack(MCInst &Inst, const MCPhysReg &StackReg, 2767 int Offset, const MCPhysReg &DstReg, 2768 int Size) const override { 2769 return createLoad(Inst, StackReg, /*Scale=*/1, /*IndexReg=*/X86::NoRegister, 2770 Offset, nullptr, /*AddrSegmentReg=*/X86::NoRegister, 2771 DstReg, Size); 2772 } 2773 2774 bool createLoad(MCInst &Inst, const MCPhysReg &BaseReg, int64_t Scale, 2775 const MCPhysReg &IndexReg, int64_t Offset, 2776 const MCExpr *OffsetExpr, const MCPhysReg &AddrSegmentReg, 2777 const MCPhysReg &DstReg, int Size) const override { 2778 unsigned NewOpcode; 2779 switch (Size) { 2780 default: 2781 return false; 2782 case 2: NewOpcode = X86::MOV16rm; break; 2783 case 4: NewOpcode = X86::MOV32rm; break; 2784 case 8: NewOpcode = X86::MOV64rm; break; 2785 } 2786 Inst.setOpcode(NewOpcode); 2787 Inst.clear(); 2788 Inst.addOperand(MCOperand::createReg(DstReg)); 2789 Inst.addOperand(MCOperand::createReg(BaseReg)); 2790 Inst.addOperand(MCOperand::createImm(Scale)); 2791 Inst.addOperand(MCOperand::createReg(IndexReg)); 2792 if (OffsetExpr) 2793 Inst.addOperand(MCOperand::createExpr(OffsetExpr)); // Displacement 2794 else 2795 Inst.addOperand(MCOperand::createImm(Offset)); // Displacement 2796 Inst.addOperand(MCOperand::createReg(AddrSegmentReg)); // AddrSegmentReg 2797 return true; 2798 } 2799 2800 void createLoadImmediate(MCInst &Inst, const MCPhysReg Dest, 2801 uint32_t Imm) const override { 2802 Inst.setOpcode(X86::MOV64ri32); 2803 Inst.clear(); 2804 Inst.addOperand(MCOperand::createReg(Dest)); 2805 Inst.addOperand(MCOperand::createImm(Imm)); 2806 } 2807 2808 bool createIncMemory(MCInst &Inst, const MCSymbol *Target, 2809 MCContext *Ctx) const override { 2810 2811 Inst.setOpcode(X86::LOCK_INC64m); 2812 Inst.clear(); 2813 Inst.addOperand(MCOperand::createReg(X86::RIP)); // BaseReg 2814 Inst.addOperand(MCOperand::createImm(1)); // ScaleAmt 2815 Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // IndexReg 2816 2817 Inst.addOperand(MCOperand::createExpr( 2818 MCSymbolRefExpr::create(Target, MCSymbolRefExpr::VK_None, 2819 *Ctx))); // Displacement 2820 Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // AddrSegmentReg 2821 return true; 2822 } 2823 2824 bool createIJmp32Frag(SmallVectorImpl<MCInst> &Insts, 2825 const MCOperand &BaseReg, const MCOperand &Scale, 2826 const MCOperand &IndexReg, const MCOperand &Offset, 2827 const MCOperand &TmpReg) const override { 2828 // The code fragment we emit here is: 2829 // 2830 // mov32 (%base, %index, scale), %tmpreg 2831 // ijmp *(%tmpreg) 2832 // 2833 MCInst IJmp; 2834 IJmp.setOpcode(X86::JMP64r); 2835 IJmp.addOperand(TmpReg); 2836 2837 MCInst Load; 2838 Load.setOpcode(X86::MOV32rm); 2839 Load.addOperand(TmpReg); 2840 Load.addOperand(BaseReg); 2841 Load.addOperand(Scale); 2842 Load.addOperand(IndexReg); 2843 Load.addOperand(Offset); 2844 Load.addOperand(MCOperand::createReg(X86::NoRegister)); 2845 2846 Insts.push_back(Load); 2847 Insts.push_back(IJmp); 2848 return true; 2849 } 2850 2851 bool createNoop(MCInst &Inst) const override { 2852 Inst.setOpcode(X86::NOOP); 2853 return true; 2854 } 2855 2856 bool createReturn(MCInst &Inst) const override { 2857 Inst.setOpcode(X86::RET64); 2858 return true; 2859 } 2860 2861 InstructionListType createInlineMemcpy(bool ReturnEnd) const override { 2862 InstructionListType Code; 2863 if (ReturnEnd) 2864 Code.emplace_back(MCInstBuilder(X86::LEA64r) 2865 .addReg(X86::RAX) 2866 .addReg(X86::RDI) 2867 .addImm(1) 2868 .addReg(X86::RDX) 2869 .addImm(0) 2870 .addReg(X86::NoRegister)); 2871 else 2872 Code.emplace_back(MCInstBuilder(X86::MOV64rr) 2873 .addReg(X86::RAX) 2874 .addReg(X86::RDI)); 2875 2876 Code.emplace_back(MCInstBuilder(X86::MOV32rr) 2877 .addReg(X86::ECX) 2878 .addReg(X86::EDX)); 2879 Code.emplace_back(MCInstBuilder(X86::REP_MOVSB_64)); 2880 2881 return Code; 2882 } 2883 2884 InstructionListType createOneByteMemcpy() const override { 2885 InstructionListType Code; 2886 Code.emplace_back(MCInstBuilder(X86::MOV8rm) 2887 .addReg(X86::CL) 2888 .addReg(X86::RSI) 2889 .addImm(0) 2890 .addReg(X86::NoRegister) 2891 .addImm(0) 2892 .addReg(X86::NoRegister)); 2893 Code.emplace_back(MCInstBuilder(X86::MOV8mr) 2894 .addReg(X86::RDI) 2895 .addImm(0) 2896 .addReg(X86::NoRegister) 2897 .addImm(0) 2898 .addReg(X86::NoRegister) 2899 .addReg(X86::CL)); 2900 Code.emplace_back(MCInstBuilder(X86::MOV64rr) 2901 .addReg(X86::RAX) 2902 .addReg(X86::RDI)); 2903 return Code; 2904 } 2905 2906 InstructionListType createCmpJE(MCPhysReg RegNo, int64_t Imm, 2907 const MCSymbol *Target, 2908 MCContext *Ctx) const override { 2909 InstructionListType Code; 2910 Code.emplace_back(MCInstBuilder(X86::CMP64ri8) 2911 .addReg(RegNo) 2912 .addImm(Imm)); 2913 Code.emplace_back(MCInstBuilder(X86::JCC_1) 2914 .addExpr(MCSymbolRefExpr::create( 2915 Target, MCSymbolRefExpr::VK_None, *Ctx)) 2916 .addImm(X86::COND_E)); 2917 return Code; 2918 } 2919 2920 Optional<Relocation> 2921 createRelocation(const MCFixup &Fixup, 2922 const MCAsmBackend &MAB) const override { 2923 const MCFixupKindInfo &FKI = MAB.getFixupKindInfo(Fixup.getKind()); 2924 2925 assert(FKI.TargetOffset == 0 && "0-bit relocation offset expected"); 2926 const uint64_t RelOffset = Fixup.getOffset(); 2927 2928 uint64_t RelType; 2929 if (FKI.Flags & MCFixupKindInfo::FKF_IsPCRel) { 2930 switch (FKI.TargetSize) { 2931 default: 2932 return NoneType(); 2933 case 8: RelType = ELF::R_X86_64_PC8; break; 2934 case 16: RelType = ELF::R_X86_64_PC16; break; 2935 case 32: RelType = ELF::R_X86_64_PC32; break; 2936 case 64: RelType = ELF::R_X86_64_PC64; break; 2937 } 2938 } else { 2939 switch (FKI.TargetSize) { 2940 default: 2941 return NoneType(); 2942 case 8: RelType = ELF::R_X86_64_8; break; 2943 case 16: RelType = ELF::R_X86_64_16; break; 2944 case 32: RelType = ELF::R_X86_64_32; break; 2945 case 64: RelType = ELF::R_X86_64_64; break; 2946 } 2947 } 2948 2949 // Extract a symbol and an addend out of the fixup value expression. 2950 // 2951 // Only the following limited expression types are supported: 2952 // Symbol + Addend 2953 // Symbol 2954 uint64_t Addend = 0; 2955 MCSymbol *Symbol = nullptr; 2956 const MCExpr *ValueExpr = Fixup.getValue(); 2957 if (ValueExpr->getKind() == MCExpr::Binary) { 2958 const auto *BinaryExpr = cast<MCBinaryExpr>(ValueExpr); 2959 assert(BinaryExpr->getOpcode() == MCBinaryExpr::Add && 2960 "unexpected binary expression"); 2961 const MCExpr *LHS = BinaryExpr->getLHS(); 2962 assert(LHS->getKind() == MCExpr::SymbolRef && "unexpected LHS"); 2963 Symbol = const_cast<MCSymbol *>(this->getTargetSymbol(LHS)); 2964 const MCExpr *RHS = BinaryExpr->getRHS(); 2965 assert(RHS->getKind() == MCExpr::Constant && "unexpected RHS"); 2966 Addend = cast<MCConstantExpr>(RHS)->getValue(); 2967 } else { 2968 assert(ValueExpr->getKind() == MCExpr::SymbolRef && "unexpected value"); 2969 Symbol = const_cast<MCSymbol *>(this->getTargetSymbol(ValueExpr)); 2970 } 2971 2972 return Relocation({RelOffset, Symbol, RelType, Addend, 0}); 2973 } 2974 2975 bool replaceImmWithSymbolRef(MCInst &Inst, const MCSymbol *Symbol, 2976 int64_t Addend, MCContext *Ctx, int64_t &Value, 2977 uint64_t RelType) const override { 2978 unsigned ImmOpNo = -1U; 2979 2980 for (unsigned Index = 0; 2981 Index < MCPlus::getNumPrimeOperands(Inst); ++Index) { 2982 if (Inst.getOperand(Index).isImm()) { 2983 ImmOpNo = Index; 2984 // TODO: this is a bit hacky. It finds the correct operand by 2985 // searching for a specific immediate value. If no value is 2986 // provided it defaults to the last immediate operand found. 2987 // This could lead to unexpected results if the instruction 2988 // has more than one immediate with the same value. 2989 if (Inst.getOperand(ImmOpNo).getImm() == Value) 2990 break; 2991 } 2992 } 2993 2994 if (ImmOpNo == -1U) 2995 return false; 2996 2997 Value = Inst.getOperand(ImmOpNo).getImm(); 2998 2999 setOperandToSymbolRef(Inst, ImmOpNo, Symbol, Addend, Ctx, RelType); 3000 3001 return true; 3002 } 3003 3004 bool replaceRegWithImm(MCInst &Inst, unsigned Register, 3005 int64_t Imm) const override { 3006 3007 enum CheckSignExt : uint8_t { 3008 NOCHECK = 0, 3009 CHECK8, 3010 CHECK32, 3011 }; 3012 3013 using CheckList = std::vector<std::pair<CheckSignExt, unsigned>>; 3014 struct InstInfo { 3015 // Size in bytes that Inst loads from memory. 3016 uint8_t DataSize; 3017 3018 // True when the target operand has to be duplicated because the opcode 3019 // expects a LHS operand. 3020 bool HasLHS; 3021 3022 // List of checks and corresponding opcodes to be used. We try to use the 3023 // smallest possible immediate value when various sizes are available, 3024 // hence we may need to check whether a larger constant fits in a smaller 3025 // immediate. 3026 CheckList Checks; 3027 }; 3028 3029 InstInfo I; 3030 3031 switch (Inst.getOpcode()) { 3032 default: { 3033 switch (getPushSize(Inst)) { 3034 3035 case 2: I = {2, false, {{CHECK8, X86::PUSH16i8}, {NOCHECK, X86::PUSHi16}}}; break; 3036 case 4: I = {4, false, {{CHECK8, X86::PUSH32i8}, {NOCHECK, X86::PUSHi32}}}; break; 3037 case 8: I = {8, false, {{CHECK8, X86::PUSH64i8}, 3038 {CHECK32, X86::PUSH64i32}, 3039 {NOCHECK, Inst.getOpcode()}}}; break; 3040 default: return false; 3041 } 3042 break; 3043 } 3044 3045 // MOV 3046 case X86::MOV8rr: I = {1, false, {{NOCHECK, X86::MOV8ri}}}; break; 3047 case X86::MOV16rr: I = {2, false, {{NOCHECK, X86::MOV16ri}}}; break; 3048 case X86::MOV32rr: I = {4, false, {{NOCHECK, X86::MOV32ri}}}; break; 3049 case X86::MOV64rr: I = {8, false, {{CHECK32, X86::MOV64ri32}, 3050 {NOCHECK, X86::MOV64ri}}}; break; 3051 3052 case X86::MOV8mr: I = {1, false, {{NOCHECK, X86::MOV8mi}}}; break; 3053 case X86::MOV16mr: I = {2, false, {{NOCHECK, X86::MOV16mi}}}; break; 3054 case X86::MOV32mr: I = {4, false, {{NOCHECK, X86::MOV32mi}}}; break; 3055 case X86::MOV64mr: I = {8, false, {{CHECK32, X86::MOV64mi32}, 3056 {NOCHECK, X86::MOV64mr}}}; break; 3057 3058 // MOVZX 3059 case X86::MOVZX16rr8: I = {1, false, {{NOCHECK, X86::MOV16ri}}}; break; 3060 case X86::MOVZX32rr8: I = {1, false, {{NOCHECK, X86::MOV32ri}}}; break; 3061 case X86::MOVZX32rr16: I = {2, false, {{NOCHECK, X86::MOV32ri}}}; break; 3062 3063 // CMP 3064 case X86::CMP8rr: I = {1, false, {{NOCHECK, X86::CMP8ri}}}; break; 3065 case X86::CMP16rr: I = {2, false, {{CHECK8, X86::CMP16ri8}, 3066 {NOCHECK, X86::CMP16ri}}}; break; 3067 case X86::CMP32rr: I = {4, false, {{CHECK8, X86::CMP32ri8}, 3068 {NOCHECK, X86::CMP32ri}}}; break; 3069 case X86::CMP64rr: I = {8, false, {{CHECK8, X86::CMP64ri8}, 3070 {CHECK32, X86::CMP64ri32}, 3071 {NOCHECK, X86::CMP64rr}}}; break; 3072 3073 // TEST 3074 case X86::TEST8rr: I = {1, false, {{NOCHECK, X86::TEST8ri}}}; break; 3075 case X86::TEST16rr: I = {2, false, {{NOCHECK, X86::TEST16ri}}}; break; 3076 case X86::TEST32rr: I = {4, false, {{NOCHECK, X86::TEST32ri}}}; break; 3077 case X86::TEST64rr: I = {8, false, {{CHECK32, X86::TEST64ri32}, 3078 {NOCHECK, X86::TEST64rr}}}; break; 3079 3080 // ADD 3081 case X86::ADD8rr: I = {1, true, {{NOCHECK, X86::ADD8ri}}}; break; 3082 case X86::ADD16rr: I = {2, true, {{CHECK8, X86::ADD16ri8}, 3083 {NOCHECK, X86::ADD16ri}}}; break; 3084 case X86::ADD32rr: I = {4, true, {{CHECK8, X86::ADD32ri8}, 3085 {NOCHECK, X86::ADD32ri}}}; break; 3086 case X86::ADD64rr: I = {8, true, {{CHECK8, X86::ADD64ri8}, 3087 {CHECK32, X86::ADD64ri32}, 3088 {NOCHECK, X86::ADD64rr}}}; break; 3089 3090 // SUB 3091 case X86::SUB8rr: I = {1, true, {{NOCHECK, X86::SUB8ri}}}; break; 3092 case X86::SUB16rr: I = {2, true, {{CHECK8, X86::SUB16ri8}, 3093 {NOCHECK, X86::SUB16ri}}}; break; 3094 case X86::SUB32rr: I = {4, true, {{CHECK8, X86::SUB32ri8}, 3095 {NOCHECK, X86::SUB32ri}}}; break; 3096 case X86::SUB64rr: I = {8, true, {{CHECK8, X86::SUB64ri8}, 3097 {CHECK32, X86::SUB64ri32}, 3098 {NOCHECK, X86::SUB64rr}}}; break; 3099 3100 // AND 3101 case X86::AND8rr: I = {1, true, {{NOCHECK, X86::AND8ri}}}; break; 3102 case X86::AND16rr: I = {2, true, {{CHECK8, X86::AND16ri8}, 3103 {NOCHECK, X86::AND16ri}}}; break; 3104 case X86::AND32rr: I = {4, true, {{CHECK8, X86::AND32ri8}, 3105 {NOCHECK, X86::AND32ri}}}; break; 3106 case X86::AND64rr: I = {8, true, {{CHECK8, X86::AND64ri8}, 3107 {CHECK32, X86::AND64ri32}, 3108 {NOCHECK, X86::AND64rr}}}; break; 3109 3110 // OR 3111 case X86::OR8rr: I = {1, true, {{NOCHECK, X86::OR8ri}}}; break; 3112 case X86::OR16rr: I = {2, true, {{CHECK8, X86::OR16ri8}, 3113 {NOCHECK, X86::OR16ri}}}; break; 3114 case X86::OR32rr: I = {4, true, {{CHECK8, X86::OR32ri8}, 3115 {NOCHECK, X86::OR32ri}}}; break; 3116 case X86::OR64rr: I = {8, true, {{CHECK8, X86::OR64ri8}, 3117 {CHECK32, X86::OR64ri32}, 3118 {NOCHECK, X86::OR64rr}}}; break; 3119 3120 // XOR 3121 case X86::XOR8rr: I = {1, true, {{NOCHECK, X86::XOR8ri}}}; break; 3122 case X86::XOR16rr: I = {2, true, {{CHECK8, X86::XOR16ri8}, 3123 {NOCHECK, X86::XOR16ri}}}; break; 3124 case X86::XOR32rr: I = {4, true, {{CHECK8, X86::XOR32ri8}, 3125 {NOCHECK, X86::XOR32ri}}}; break; 3126 case X86::XOR64rr: I = {8, true, {{CHECK8, X86::XOR64ri8}, 3127 {CHECK32, X86::XOR64ri32}, 3128 {NOCHECK, X86::XOR64rr}}}; break; 3129 } 3130 3131 // Compute the new opcode. 3132 unsigned NewOpcode = 0; 3133 for (const std::pair<CheckSignExt, unsigned> &Check : I.Checks) { 3134 NewOpcode = Check.second; 3135 if (Check.first == NOCHECK) 3136 break; 3137 if (Check.first == CHECK8 && Imm >= std::numeric_limits<int8_t>::min() && 3138 Imm <= std::numeric_limits<int8_t>::max()) 3139 break; 3140 if (Check.first == CHECK32 && 3141 Imm >= std::numeric_limits<int32_t>::min() && 3142 Imm <= std::numeric_limits<int32_t>::max()) 3143 break; 3144 } 3145 if (NewOpcode == Inst.getOpcode()) 3146 return false; 3147 3148 const MCInstrDesc &InstDesc = Info->get(Inst.getOpcode()); 3149 3150 unsigned NumFound = 0; 3151 for (unsigned Index = InstDesc.getNumDefs() + (I.HasLHS ? 1 : 0), 3152 E = InstDesc.getNumOperands(); Index != E; ++Index) 3153 if (Inst.getOperand(Index).isReg() && 3154 Inst.getOperand(Index).getReg() == Register) 3155 NumFound++; 3156 3157 if (NumFound != 1) 3158 return false; 3159 3160 // Iterate backwards to replace the src register before the src/dest 3161 // register as in AND, ADD, and SUB Only iterate through src operands that 3162 // arent also dest operands 3163 for (unsigned Index = InstDesc.getNumOperands() - 1, 3164 E = InstDesc.getNumDefs() + (I.HasLHS ? 0 : -1); 3165 Index != E; --Index) { 3166 if (!Inst.getOperand(Index).isReg() || 3167 Inst.getOperand(Index).getReg() != Register) 3168 continue; 3169 MCOperand NewOperand = MCOperand::createImm(Imm); 3170 Inst.getOperand(Index) = NewOperand; 3171 break; 3172 } 3173 3174 Inst.setOpcode(NewOpcode); 3175 3176 return true; 3177 } 3178 3179 bool replaceRegWithReg(MCInst &Inst, unsigned ToReplace, 3180 unsigned ReplaceWith) const override { 3181 3182 // Get the HasLHS value so that iteration can be done 3183 bool HasLHS; 3184 if (isAND(Inst.getOpcode()) || isADD(Inst.getOpcode()) || isSUB(Inst)) { 3185 HasLHS = true; 3186 } else if (isPop(Inst) || isPush(Inst) || isCMP(Inst.getOpcode()) || 3187 isTEST(Inst.getOpcode())) { 3188 HasLHS = false; 3189 } else { 3190 switch (Inst.getOpcode()) { 3191 case X86::MOV8rr: 3192 case X86::MOV8rm: 3193 case X86::MOV8mr: 3194 case X86::MOV8ri: 3195 case X86::MOV16rr: 3196 case X86::MOV16rm: 3197 case X86::MOV16mr: 3198 case X86::MOV16ri: 3199 case X86::MOV32rr: 3200 case X86::MOV32rm: 3201 case X86::MOV32mr: 3202 case X86::MOV32ri: 3203 case X86::MOV64rr: 3204 case X86::MOV64rm: 3205 case X86::MOV64mr: 3206 case X86::MOV64ri: 3207 case X86::MOVZX16rr8: 3208 case X86::MOVZX32rr8: 3209 case X86::MOVZX32rr16: 3210 case X86::MOVSX32rm8: 3211 case X86::MOVSX32rr8: 3212 case X86::MOVSX64rm32: 3213 case X86::LEA64r: 3214 HasLHS = false; 3215 break; 3216 default: 3217 return false; 3218 } 3219 } 3220 3221 const MCInstrDesc &InstDesc = Info->get(Inst.getOpcode()); 3222 3223 bool FoundOne = false; 3224 3225 // Iterate only through src operands that arent also dest operands 3226 for (unsigned Index = InstDesc.getNumDefs() + (HasLHS ? 1 : 0), 3227 E = InstDesc.getNumOperands(); 3228 Index != E; ++Index) { 3229 BitVector RegAliases = getAliases(ToReplace, true); 3230 if (!Inst.getOperand(Index).isReg() || 3231 !RegAliases.test(Inst.getOperand(Index).getReg())) 3232 continue; 3233 // Resize register if needed 3234 unsigned SizedReplaceWith = getAliasSized( 3235 ReplaceWith, getRegSize(Inst.getOperand(Index).getReg())); 3236 MCOperand NewOperand = MCOperand::createReg(SizedReplaceWith); 3237 Inst.getOperand(Index) = NewOperand; 3238 FoundOne = true; 3239 } 3240 3241 // Return true if at least one operand was replaced 3242 return FoundOne; 3243 } 3244 3245 bool createUncondBranch(MCInst &Inst, const MCSymbol *TBB, 3246 MCContext *Ctx) const override { 3247 Inst.setOpcode(X86::JMP_1); 3248 Inst.addOperand(MCOperand::createExpr( 3249 MCSymbolRefExpr::create(TBB, MCSymbolRefExpr::VK_None, *Ctx))); 3250 return true; 3251 } 3252 3253 bool createCall(MCInst &Inst, const MCSymbol *Target, 3254 MCContext *Ctx) override { 3255 Inst.setOpcode(X86::CALL64pcrel32); 3256 Inst.addOperand(MCOperand::createExpr( 3257 MCSymbolRefExpr::create(Target, MCSymbolRefExpr::VK_None, *Ctx))); 3258 return true; 3259 } 3260 3261 bool createTailCall(MCInst &Inst, const MCSymbol *Target, 3262 MCContext *Ctx) override { 3263 return createDirectCall(Inst, Target, Ctx, /*IsTailCall*/ true); 3264 } 3265 3266 void createLongTailCall(InstructionListType &Seq, const MCSymbol *Target, 3267 MCContext *Ctx) override { 3268 Seq.clear(); 3269 Seq.emplace_back(); 3270 createDirectCall(Seq.back(), Target, Ctx, /*IsTailCall*/ true); 3271 } 3272 3273 bool createTrap(MCInst &Inst) const override { 3274 Inst.clear(); 3275 Inst.setOpcode(X86::TRAP); 3276 return true; 3277 } 3278 3279 bool reverseBranchCondition(MCInst &Inst, const MCSymbol *TBB, 3280 MCContext *Ctx) const override { 3281 unsigned InvCC = getInvertedCondCode(getCondCode(Inst)); 3282 assert(InvCC != X86::COND_INVALID && "invalid branch instruction"); 3283 Inst.getOperand(Info->get(Inst.getOpcode()).NumOperands - 1).setImm(InvCC); 3284 Inst.getOperand(0) = MCOperand::createExpr( 3285 MCSymbolRefExpr::create(TBB, MCSymbolRefExpr::VK_None, *Ctx)); 3286 return true; 3287 } 3288 3289 bool replaceBranchCondition(MCInst &Inst, const MCSymbol *TBB, MCContext *Ctx, 3290 unsigned CC) const override { 3291 if (CC == X86::COND_INVALID) 3292 return false; 3293 Inst.getOperand(Info->get(Inst.getOpcode()).NumOperands - 1).setImm(CC); 3294 Inst.getOperand(0) = MCOperand::createExpr( 3295 MCSymbolRefExpr::create(TBB, MCSymbolRefExpr::VK_None, *Ctx)); 3296 return true; 3297 } 3298 3299 unsigned getCanonicalBranchCondCode(unsigned CC) const override { 3300 switch (CC) { 3301 default: return X86::COND_INVALID; 3302 3303 case X86::COND_E: return X86::COND_E; 3304 case X86::COND_NE: return X86::COND_E; 3305 3306 case X86::COND_L: return X86::COND_L; 3307 case X86::COND_GE: return X86::COND_L; 3308 3309 case X86::COND_LE: return X86::COND_G; 3310 case X86::COND_G: return X86::COND_G; 3311 3312 case X86::COND_B: return X86::COND_B; 3313 case X86::COND_AE: return X86::COND_B; 3314 3315 case X86::COND_BE: return X86::COND_A; 3316 case X86::COND_A: return X86::COND_A; 3317 3318 case X86::COND_S: return X86::COND_S; 3319 case X86::COND_NS: return X86::COND_S; 3320 3321 case X86::COND_P: return X86::COND_P; 3322 case X86::COND_NP: return X86::COND_P; 3323 3324 case X86::COND_O: return X86::COND_O; 3325 case X86::COND_NO: return X86::COND_O; 3326 } 3327 } 3328 3329 bool replaceBranchTarget(MCInst &Inst, const MCSymbol *TBB, 3330 MCContext *Ctx) const override { 3331 assert((isCall(Inst) || isBranch(Inst)) && !isIndirectBranch(Inst) && 3332 "Invalid instruction"); 3333 Inst.getOperand(0) = MCOperand::createExpr( 3334 MCSymbolRefExpr::create(TBB, MCSymbolRefExpr::VK_None, *Ctx)); 3335 return true; 3336 } 3337 3338 MCPhysReg getX86R11() const override { 3339 return X86::R11; 3340 } 3341 3342 MCPhysReg getNoRegister() const override { 3343 return X86::NoRegister; 3344 } 3345 3346 MCPhysReg getIntArgRegister(unsigned ArgNo) const override { 3347 // FIXME: this should depend on the calling convention. 3348 switch (ArgNo) { 3349 case 0: return X86::RDI; 3350 case 1: return X86::RSI; 3351 case 2: return X86::RDX; 3352 case 3: return X86::RCX; 3353 case 4: return X86::R8; 3354 case 5: return X86::R9; 3355 default: return getNoRegister(); 3356 } 3357 } 3358 3359 void createPause(MCInst &Inst) const override { 3360 Inst.clear(); 3361 Inst.setOpcode(X86::PAUSE); 3362 } 3363 3364 void createLfence(MCInst &Inst) const override { 3365 Inst.clear(); 3366 Inst.setOpcode(X86::LFENCE); 3367 } 3368 3369 bool createDirectCall(MCInst &Inst, const MCSymbol *Target, MCContext *Ctx, 3370 bool IsTailCall) override { 3371 Inst.clear(); 3372 Inst.setOpcode(IsTailCall ? X86::JMP_4 : X86::CALL64pcrel32); 3373 Inst.addOperand(MCOperand::createExpr( 3374 MCSymbolRefExpr::create(Target, MCSymbolRefExpr::VK_None, *Ctx))); 3375 if (IsTailCall) 3376 setTailCall(Inst); 3377 return true; 3378 } 3379 3380 void createShortJmp(InstructionListType &Seq, const MCSymbol *Target, 3381 MCContext *Ctx, bool IsTailCall) override { 3382 Seq.clear(); 3383 MCInst Inst; 3384 Inst.setOpcode(X86::JMP_1); 3385 Inst.addOperand(MCOperand::createExpr( 3386 MCSymbolRefExpr::create(Target, MCSymbolRefExpr::VK_None, *Ctx))); 3387 if (IsTailCall) 3388 setTailCall(Inst); 3389 Seq.emplace_back(Inst); 3390 } 3391 3392 bool isConditionalMove(const MCInst &Inst) const override { 3393 unsigned OpCode = Inst.getOpcode(); 3394 return (OpCode == X86::CMOV16rr || OpCode == X86::CMOV32rr || 3395 OpCode == X86::CMOV64rr); 3396 } 3397 3398 bool isBranchOnMem(const MCInst &Inst) const override { 3399 unsigned OpCode = Inst.getOpcode(); 3400 if (OpCode == X86::CALL64m || (OpCode == X86::JMP32m && isTailCall(Inst)) || 3401 OpCode == X86::JMP64m) 3402 return true; 3403 3404 return false; 3405 } 3406 3407 bool isBranchOnReg(const MCInst &Inst) const override { 3408 unsigned OpCode = Inst.getOpcode(); 3409 if (OpCode == X86::CALL64r || (OpCode == X86::JMP32r && isTailCall(Inst)) || 3410 OpCode == X86::JMP64r) 3411 return true; 3412 3413 return false; 3414 } 3415 3416 void createPushRegister(MCInst &Inst, MCPhysReg Reg, 3417 unsigned Size) const override { 3418 Inst.clear(); 3419 unsigned NewOpcode = 0; 3420 if (Reg == X86::EFLAGS) { 3421 switch (Size) { 3422 case 2: NewOpcode = X86::PUSHF16; break; 3423 case 4: NewOpcode = X86::PUSHF32; break; 3424 case 8: NewOpcode = X86::PUSHF64; break; 3425 default: 3426 assert(false); 3427 } 3428 Inst.setOpcode(NewOpcode); 3429 return; 3430 } 3431 switch (Size) { 3432 case 2: NewOpcode = X86::PUSH16r; break; 3433 case 4: NewOpcode = X86::PUSH32r; break; 3434 case 8: NewOpcode = X86::PUSH64r; break; 3435 default: 3436 assert(false); 3437 } 3438 Inst.setOpcode(NewOpcode); 3439 Inst.addOperand(MCOperand::createReg(Reg)); 3440 } 3441 3442 void createPopRegister(MCInst &Inst, MCPhysReg Reg, 3443 unsigned Size) const override { 3444 Inst.clear(); 3445 unsigned NewOpcode = 0; 3446 if (Reg == X86::EFLAGS) { 3447 switch (Size) { 3448 case 2: NewOpcode = X86::POPF16; break; 3449 case 4: NewOpcode = X86::POPF32; break; 3450 case 8: NewOpcode = X86::POPF64; break; 3451 default: 3452 assert(false); 3453 } 3454 Inst.setOpcode(NewOpcode); 3455 return; 3456 } 3457 switch (Size) { 3458 case 2: NewOpcode = X86::POP16r; break; 3459 case 4: NewOpcode = X86::POP32r; break; 3460 case 8: NewOpcode = X86::POP64r; break; 3461 default: 3462 assert(false); 3463 } 3464 Inst.setOpcode(NewOpcode); 3465 Inst.addOperand(MCOperand::createReg(Reg)); 3466 } 3467 3468 void createPushFlags(MCInst &Inst, unsigned Size) const override { 3469 return createPushRegister(Inst, X86::EFLAGS, Size); 3470 } 3471 3472 void createPopFlags(MCInst &Inst, unsigned Size) const override { 3473 return createPopRegister(Inst, X86::EFLAGS, Size); 3474 } 3475 3476 void createAddRegImm(MCInst &Inst, MCPhysReg Reg, int64_t Value, 3477 unsigned Size) const { 3478 unsigned int Opcode; 3479 switch (Size) { 3480 case 1: Opcode = X86::ADD8ri; break; 3481 case 2: Opcode = X86::ADD16ri; break; 3482 case 4: Opcode = X86::ADD32ri; break; 3483 default: 3484 llvm_unreachable("Unexpected size"); 3485 } 3486 Inst.setOpcode(Opcode); 3487 Inst.clear(); 3488 Inst.addOperand(MCOperand::createReg(Reg)); 3489 Inst.addOperand(MCOperand::createReg(Reg)); 3490 Inst.addOperand(MCOperand::createImm(Value)); 3491 } 3492 3493 void createClearRegWithNoEFlagsUpdate(MCInst &Inst, MCPhysReg Reg, 3494 unsigned Size) const { 3495 unsigned int Opcode; 3496 switch (Size) { 3497 case 1: Opcode = X86::MOV8ri; break; 3498 case 2: Opcode = X86::MOV16ri; break; 3499 case 4: Opcode = X86::MOV32ri; break; 3500 case 8: Opcode = X86::MOV64ri; break; 3501 default: 3502 llvm_unreachable("Unexpected size"); 3503 } 3504 Inst.setOpcode(Opcode); 3505 Inst.clear(); 3506 Inst.addOperand(MCOperand::createReg(Reg)); 3507 Inst.addOperand(MCOperand::createImm(0)); 3508 } 3509 3510 void createX86SaveOVFlagToRegister(MCInst &Inst, MCPhysReg Reg) const { 3511 Inst.setOpcode(X86::SETCCr); 3512 Inst.clear(); 3513 Inst.addOperand(MCOperand::createReg(Reg)); 3514 Inst.addOperand(MCOperand::createImm(X86::COND_O)); 3515 } 3516 3517 void createX86Lahf(MCInst &Inst) const { 3518 Inst.setOpcode(X86::LAHF); 3519 Inst.clear(); 3520 } 3521 3522 void createX86Sahf(MCInst &Inst) const { 3523 Inst.setOpcode(X86::SAHF); 3524 Inst.clear(); 3525 } 3526 3527 void createInstrIncMemory(InstructionListType &Instrs, const MCSymbol *Target, 3528 MCContext *Ctx, bool IsLeaf) const override { 3529 unsigned int I = 0; 3530 3531 Instrs.resize(IsLeaf ? 13 : 11); 3532 // Don't clobber application red zone (ABI dependent) 3533 if (IsLeaf) 3534 createStackPointerIncrement(Instrs[I++], 128, 3535 /*NoFlagsClobber=*/true); 3536 3537 // Performance improvements based on the optimization discussed at 3538 // https://reviews.llvm.org/D6629 3539 // LAHF/SAHF are used instead of PUSHF/POPF 3540 // PUSHF 3541 createPushRegister(Instrs[I++], X86::RAX, 8); 3542 createClearRegWithNoEFlagsUpdate(Instrs[I++], X86::RAX, 8); 3543 createX86Lahf(Instrs[I++]); 3544 createPushRegister(Instrs[I++], X86::RAX, 8); 3545 createClearRegWithNoEFlagsUpdate(Instrs[I++], X86::RAX, 8); 3546 createX86SaveOVFlagToRegister(Instrs[I++], X86::AL); 3547 // LOCK INC 3548 createIncMemory(Instrs[I++], Target, Ctx); 3549 // POPF 3550 createAddRegImm(Instrs[I++], X86::AL, 127, 1); 3551 createPopRegister(Instrs[I++], X86::RAX, 8); 3552 createX86Sahf(Instrs[I++]); 3553 createPopRegister(Instrs[I++], X86::RAX, 8); 3554 3555 if (IsLeaf) 3556 createStackPointerDecrement(Instrs[I], 128, 3557 /*NoFlagsClobber=*/true); 3558 } 3559 3560 void createSwap(MCInst &Inst, MCPhysReg Source, MCPhysReg MemBaseReg, 3561 int64_t Disp) const { 3562 Inst.setOpcode(X86::XCHG64rm); 3563 Inst.addOperand(MCOperand::createReg(Source)); 3564 Inst.addOperand(MCOperand::createReg(Source)); 3565 Inst.addOperand(MCOperand::createReg(MemBaseReg)); // BaseReg 3566 Inst.addOperand(MCOperand::createImm(1)); // ScaleAmt 3567 Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // IndexReg 3568 Inst.addOperand(MCOperand::createImm(Disp)); // Displacement 3569 Inst.addOperand(MCOperand::createReg(X86::NoRegister));//AddrSegmentReg 3570 } 3571 3572 void createIndirectBranch(MCInst &Inst, MCPhysReg MemBaseReg, 3573 int64_t Disp) const { 3574 Inst.setOpcode(X86::JMP64m); 3575 Inst.addOperand(MCOperand::createReg(MemBaseReg)); // BaseReg 3576 Inst.addOperand(MCOperand::createImm(1)); // ScaleAmt 3577 Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // IndexReg 3578 Inst.addOperand(MCOperand::createImm(Disp)); // Displacement 3579 Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // AddrSegmentReg 3580 } 3581 3582 InstructionListType createInstrumentedIndirectCall(const MCInst &CallInst, 3583 bool TailCall, 3584 MCSymbol *HandlerFuncAddr, 3585 int CallSiteID, 3586 MCContext *Ctx) override { 3587 // Check if the target address expression used in the original indirect call 3588 // uses the stack pointer, which we are going to clobber. 3589 static BitVector SPAliases(getAliases(X86::RSP)); 3590 bool UsesSP = false; 3591 // Skip defs. 3592 for (unsigned I = Info->get(CallInst.getOpcode()).getNumDefs(), 3593 E = MCPlus::getNumPrimeOperands(CallInst); I != E; ++I) { 3594 const MCOperand &Operand = CallInst.getOperand(I); 3595 if (Operand.isReg() && SPAliases[Operand.getReg()]) { 3596 UsesSP = true; 3597 break; 3598 } 3599 } 3600 3601 InstructionListType Insts; 3602 MCPhysReg TempReg = getIntArgRegister(0); 3603 // Code sequence used to enter indirect call instrumentation helper: 3604 // push %rdi 3605 // add $8, %rsp ;; $rsp may be used in target, so fix it to prev val 3606 // movq target, %rdi ;; via convertIndirectCallTargetToLoad 3607 // sub $8, %rsp ;; restore correct stack value 3608 // push %rdi 3609 // movq $CallSiteID, %rdi 3610 // push %rdi 3611 // callq/jmp HandlerFuncAddr 3612 Insts.emplace_back(); 3613 createPushRegister(Insts.back(), TempReg, 8); 3614 if (UsesSP) { // Only adjust SP if we really need to 3615 Insts.emplace_back(); 3616 createStackPointerDecrement(Insts.back(), 8, /*NoFlagsClobber=*/false); 3617 } 3618 Insts.emplace_back(CallInst); 3619 // Insts.back() and CallInst now share the same annotation instruction. 3620 // Strip it from Insts.back(), only preserving tail call annotation. 3621 stripAnnotations(Insts.back(), /*KeepTC=*/true); 3622 convertIndirectCallToLoad(Insts.back(), TempReg); 3623 if (UsesSP) { 3624 Insts.emplace_back(); 3625 createStackPointerIncrement(Insts.back(), 8, /*NoFlagsClobber=*/false); 3626 } 3627 Insts.emplace_back(); 3628 createPushRegister(Insts.back(), TempReg, 8); 3629 Insts.emplace_back(); 3630 createLoadImmediate(Insts.back(), TempReg, CallSiteID); 3631 Insts.emplace_back(); 3632 createPushRegister(Insts.back(), TempReg, 8); 3633 Insts.emplace_back(); 3634 createDirectCall(Insts.back(), HandlerFuncAddr, Ctx, 3635 /*TailCall=*/TailCall); 3636 // Carry over metadata 3637 for (int I = MCPlus::getNumPrimeOperands(CallInst), 3638 E = CallInst.getNumOperands(); 3639 I != E; ++I) 3640 Insts.back().addOperand(CallInst.getOperand(I)); 3641 3642 return Insts; 3643 } 3644 3645 InstructionListType createInstrumentedIndCallHandlerExitBB() const override { 3646 const MCPhysReg TempReg = getIntArgRegister(0); 3647 // We just need to undo the sequence created for every ind call in 3648 // instrumentIndirectTarget(), which can be accomplished minimally with: 3649 // popfq 3650 // pop %rdi 3651 // add $16, %rsp 3652 // xchg (%rsp), %rdi 3653 // jmp *-8(%rsp) 3654 InstructionListType Insts(5); 3655 createPopFlags(Insts[0], 8); 3656 createPopRegister(Insts[1], TempReg, 8); 3657 createStackPointerDecrement(Insts[2], 16, /*NoFlagsClobber=*/false); 3658 createSwap(Insts[3], TempReg, X86::RSP, 0); 3659 createIndirectBranch(Insts[4], X86::RSP, -8); 3660 return Insts; 3661 } 3662 3663 InstructionListType 3664 createInstrumentedIndTailCallHandlerExitBB() const override { 3665 const MCPhysReg TempReg = getIntArgRegister(0); 3666 // Same thing as above, but for tail calls 3667 // popfq 3668 // add $16, %rsp 3669 // pop %rdi 3670 // jmp *-16(%rsp) 3671 InstructionListType Insts(4); 3672 createPopFlags(Insts[0], 8); 3673 createStackPointerDecrement(Insts[1], 16, /*NoFlagsClobber=*/false); 3674 createPopRegister(Insts[2], TempReg, 8); 3675 createIndirectBranch(Insts[3], X86::RSP, -16); 3676 return Insts; 3677 } 3678 3679 InstructionListType 3680 createInstrumentedIndCallHandlerEntryBB(const MCSymbol *InstrTrampoline, 3681 const MCSymbol *IndCallHandler, 3682 MCContext *Ctx) override { 3683 const MCPhysReg TempReg = getIntArgRegister(0); 3684 // Code sequence used to check whether InstrTampoline was initialized 3685 // and call it if so, returns via IndCallHandler. 3686 // pushfq 3687 // mov InstrTrampoline,%rdi 3688 // cmp $0x0,%rdi 3689 // je IndCallHandler 3690 // callq *%rdi 3691 // jmpq IndCallHandler 3692 InstructionListType Insts; 3693 Insts.emplace_back(); 3694 createPushFlags(Insts.back(), 8); 3695 Insts.emplace_back(); 3696 createMove(Insts.back(), InstrTrampoline, TempReg, Ctx); 3697 InstructionListType cmpJmp = createCmpJE(TempReg, 0, IndCallHandler, Ctx); 3698 Insts.insert(Insts.end(), cmpJmp.begin(), cmpJmp.end()); 3699 Insts.emplace_back(); 3700 Insts.back().setOpcode(X86::CALL64r); 3701 Insts.back().addOperand(MCOperand::createReg(TempReg)); 3702 Insts.emplace_back(); 3703 createDirectCall(Insts.back(), IndCallHandler, Ctx, /*IsTailCall*/ true); 3704 return Insts; 3705 } 3706 3707 InstructionListType createNumCountersGetter(MCContext *Ctx) const override { 3708 InstructionListType Insts(2); 3709 MCSymbol *NumLocs = Ctx->getOrCreateSymbol("__bolt_num_counters"); 3710 createMove(Insts[0], NumLocs, X86::EAX, Ctx); 3711 createReturn(Insts[1]); 3712 return Insts; 3713 } 3714 3715 InstructionListType 3716 createInstrLocationsGetter(MCContext *Ctx) const override { 3717 InstructionListType Insts(2); 3718 MCSymbol *Locs = Ctx->getOrCreateSymbol("__bolt_instr_locations"); 3719 createLea(Insts[0], Locs, X86::EAX, Ctx); 3720 createReturn(Insts[1]); 3721 return Insts; 3722 } 3723 3724 InstructionListType createInstrTablesGetter(MCContext *Ctx) const override { 3725 InstructionListType Insts(2); 3726 MCSymbol *Locs = Ctx->getOrCreateSymbol("__bolt_instr_tables"); 3727 createLea(Insts[0], Locs, X86::EAX, Ctx); 3728 createReturn(Insts[1]); 3729 return Insts; 3730 } 3731 3732 InstructionListType createInstrNumFuncsGetter(MCContext *Ctx) const override { 3733 InstructionListType Insts(2); 3734 MCSymbol *NumFuncs = Ctx->getOrCreateSymbol("__bolt_instr_num_funcs"); 3735 createMove(Insts[0], NumFuncs, X86::EAX, Ctx); 3736 createReturn(Insts[1]); 3737 return Insts; 3738 } 3739 3740 InstructionListType createSymbolTrampoline(const MCSymbol *TgtSym, 3741 MCContext *Ctx) const override { 3742 InstructionListType Insts(1); 3743 createUncondBranch(Insts[0], TgtSym, Ctx); 3744 return Insts; 3745 } 3746 3747 InstructionListType createDummyReturnFunction(MCContext *Ctx) const override { 3748 InstructionListType Insts(1); 3749 createReturn(Insts[0]); 3750 return Insts; 3751 } 3752 3753 BlocksVectorTy indirectCallPromotion( 3754 const MCInst &CallInst, 3755 const std::vector<std::pair<MCSymbol *, uint64_t>> &Targets, 3756 const std::vector<std::pair<MCSymbol *, uint64_t>> &VtableSyms, 3757 const std::vector<MCInst *> &MethodFetchInsns, 3758 const bool MinimizeCodeSize, 3759 MCContext *Ctx 3760 ) override { 3761 const bool IsTailCall = isTailCall(CallInst); 3762 const bool IsJumpTable = getJumpTable(CallInst) != 0; 3763 BlocksVectorTy Results; 3764 3765 // Label for the current code block. 3766 MCSymbol *NextTarget = nullptr; 3767 3768 // The join block which contains all the instructions following CallInst. 3769 // MergeBlock remains null if CallInst is a tail call. 3770 MCSymbol *MergeBlock = nullptr; 3771 3772 unsigned FuncAddrReg = X86::R10; 3773 3774 const bool LoadElim = !VtableSyms.empty(); 3775 assert((!LoadElim || VtableSyms.size() == Targets.size()) && 3776 "There must be a vtable entry for every method " 3777 "in the targets vector."); 3778 3779 if (MinimizeCodeSize && !LoadElim) { 3780 std::set<unsigned> UsedRegs; 3781 3782 for (unsigned int I = 0; I < MCPlus::getNumPrimeOperands(CallInst); ++I) { 3783 const MCOperand &Op = CallInst.getOperand(I); 3784 if (Op.isReg()) 3785 UsedRegs.insert(Op.getReg()); 3786 } 3787 3788 if (UsedRegs.count(X86::R10) == 0) 3789 FuncAddrReg = X86::R10; 3790 else if (UsedRegs.count(X86::R11) == 0) 3791 FuncAddrReg = X86::R11; 3792 else 3793 return Results; 3794 } 3795 3796 const auto jumpToMergeBlock = [&](InstructionListType &NewCall) { 3797 assert(MergeBlock); 3798 NewCall.push_back(CallInst); 3799 MCInst &Merge = NewCall.back(); 3800 Merge.clear(); 3801 createUncondBranch(Merge, MergeBlock, Ctx); 3802 }; 3803 3804 for (unsigned int i = 0; i < Targets.size(); ++i) { 3805 Results.emplace_back(NextTarget, InstructionListType()); 3806 InstructionListType *NewCall = &Results.back().second; 3807 3808 if (MinimizeCodeSize && !LoadElim) { 3809 // Load the call target into FuncAddrReg. 3810 NewCall->push_back(CallInst); // Copy CallInst in order to get SMLoc 3811 MCInst &Target = NewCall->back(); 3812 Target.clear(); 3813 Target.setOpcode(X86::MOV64ri32); 3814 Target.addOperand(MCOperand::createReg(FuncAddrReg)); 3815 if (Targets[i].first) { 3816 // Is this OK? 3817 Target.addOperand( 3818 MCOperand::createExpr( 3819 MCSymbolRefExpr::create(Targets[i].first, 3820 MCSymbolRefExpr::VK_None, 3821 *Ctx))); 3822 } else { 3823 const uint64_t Addr = Targets[i].second; 3824 // Immediate address is out of sign extended 32 bit range. 3825 if (int64_t(Addr) != int64_t(int32_t(Addr))) 3826 return BlocksVectorTy(); 3827 3828 Target.addOperand(MCOperand::createImm(Addr)); 3829 } 3830 3831 // Compare current call target to a specific address. 3832 NewCall->push_back(CallInst); 3833 MCInst &Compare = NewCall->back(); 3834 Compare.clear(); 3835 if (isBranchOnReg(CallInst)) 3836 Compare.setOpcode(X86::CMP64rr); 3837 else if (CallInst.getOpcode() == X86::CALL64pcrel32) 3838 Compare.setOpcode(X86::CMP64ri32); 3839 else 3840 Compare.setOpcode(X86::CMP64rm); 3841 3842 Compare.addOperand(MCOperand::createReg(FuncAddrReg)); 3843 3844 // TODO: Would be preferable to only load this value once. 3845 for (unsigned i = 0; 3846 i < Info->get(CallInst.getOpcode()).getNumOperands(); 3847 ++i) 3848 if (!CallInst.getOperand(i).isInst()) 3849 Compare.addOperand(CallInst.getOperand(i)); 3850 } else { 3851 // Compare current call target to a specific address. 3852 NewCall->push_back(CallInst); 3853 MCInst &Compare = NewCall->back(); 3854 Compare.clear(); 3855 if (isBranchOnReg(CallInst)) 3856 Compare.setOpcode(X86::CMP64ri32); 3857 else 3858 Compare.setOpcode(X86::CMP64mi32); 3859 3860 // Original call address. 3861 for (unsigned i = 0; 3862 i < Info->get(CallInst.getOpcode()).getNumOperands(); 3863 ++i) 3864 if (!CallInst.getOperand(i).isInst()) 3865 Compare.addOperand(CallInst.getOperand(i)); 3866 3867 // Target address. 3868 if (Targets[i].first || LoadElim) { 3869 const MCSymbol *Sym = 3870 LoadElim ? VtableSyms[i].first : Targets[i].first; 3871 const uint64_t Addend = LoadElim ? VtableSyms[i].second : 0; 3872 3873 const MCExpr *Expr = MCSymbolRefExpr::create(Sym, *Ctx); 3874 3875 if (Addend) 3876 Expr = MCBinaryExpr::createAdd(Expr, 3877 MCConstantExpr::create(Addend, *Ctx), 3878 *Ctx); 3879 3880 Compare.addOperand(MCOperand::createExpr(Expr)); 3881 } else { 3882 const uint64_t Addr = Targets[i].second; 3883 // Immediate address is out of sign extended 32 bit range. 3884 if (int64_t(Addr) != int64_t(int32_t(Addr))) 3885 return BlocksVectorTy(); 3886 3887 Compare.addOperand(MCOperand::createImm(Addr)); 3888 } 3889 } 3890 3891 // jump to next target compare. 3892 NextTarget = 3893 Ctx->createNamedTempSymbol(); // generate label for the next block 3894 NewCall->push_back(CallInst); 3895 3896 if (IsJumpTable) { 3897 MCInst &Je = NewCall->back(); 3898 3899 // Jump to next compare if target addresses don't match. 3900 Je.clear(); 3901 Je.setOpcode(X86::JCC_1); 3902 if (Targets[i].first) 3903 Je.addOperand(MCOperand::createExpr( 3904 MCSymbolRefExpr::create(Targets[i].first, 3905 MCSymbolRefExpr::VK_None, 3906 *Ctx))); 3907 else 3908 Je.addOperand(MCOperand::createImm(Targets[i].second)); 3909 3910 Je.addOperand(MCOperand::createImm(X86::COND_E)); 3911 assert(!isInvoke(CallInst)); 3912 } else { 3913 MCInst &Jne = NewCall->back(); 3914 3915 // Jump to next compare if target addresses don't match. 3916 Jne.clear(); 3917 Jne.setOpcode(X86::JCC_1); 3918 Jne.addOperand(MCOperand::createExpr(MCSymbolRefExpr::create( 3919 NextTarget, MCSymbolRefExpr::VK_None, *Ctx))); 3920 Jne.addOperand(MCOperand::createImm(X86::COND_NE)); 3921 3922 // Call specific target directly. 3923 Results.emplace_back(Ctx->createNamedTempSymbol(), 3924 InstructionListType()); 3925 NewCall = &Results.back().second; 3926 NewCall->push_back(CallInst); 3927 MCInst &CallOrJmp = NewCall->back(); 3928 3929 CallOrJmp.clear(); 3930 3931 if (MinimizeCodeSize && !LoadElim) { 3932 CallOrJmp.setOpcode(IsTailCall ? X86::JMP32r : X86::CALL64r); 3933 CallOrJmp.addOperand(MCOperand::createReg(FuncAddrReg)); 3934 } else { 3935 CallOrJmp.setOpcode(IsTailCall ? X86::JMP_4 : X86::CALL64pcrel32); 3936 3937 if (Targets[i].first) 3938 CallOrJmp.addOperand(MCOperand::createExpr(MCSymbolRefExpr::create( 3939 Targets[i].first, MCSymbolRefExpr::VK_None, *Ctx))); 3940 else 3941 CallOrJmp.addOperand(MCOperand::createImm(Targets[i].second)); 3942 } 3943 if (IsTailCall) 3944 setTailCall(CallOrJmp); 3945 3946 if (CallOrJmp.getOpcode() == X86::CALL64r || 3947 CallOrJmp.getOpcode() == X86::CALL64pcrel32) { 3948 if (hasAnnotation(CallInst, "Offset")) 3949 // Annotated as duplicated call 3950 addAnnotation(CallOrJmp, "Offset", 3951 getAnnotationAs<uint32_t>(CallInst, "Offset")); 3952 } 3953 3954 if (isInvoke(CallInst) && !isInvoke(CallOrJmp)) { 3955 // Copy over any EH or GNU args size information from the original 3956 // call. 3957 Optional<MCPlus::MCLandingPad> EHInfo = getEHInfo(CallInst); 3958 if (EHInfo) 3959 addEHInfo(CallOrJmp, *EHInfo); 3960 int64_t GnuArgsSize = getGnuArgsSize(CallInst); 3961 if (GnuArgsSize >= 0) 3962 addGnuArgsSize(CallOrJmp, GnuArgsSize); 3963 } 3964 3965 if (!IsTailCall) { 3966 // The fallthrough block for the most common target should be 3967 // the merge block. 3968 if (i == 0) { 3969 // Fallthrough to merge block. 3970 MergeBlock = Ctx->createNamedTempSymbol(); 3971 } else { 3972 // Insert jump to the merge block if we are not doing a fallthrough. 3973 jumpToMergeBlock(*NewCall); 3974 } 3975 } 3976 } 3977 } 3978 3979 // Cold call block. 3980 Results.emplace_back(NextTarget, InstructionListType()); 3981 InstructionListType &NewCall = Results.back().second; 3982 for (const MCInst *Inst : MethodFetchInsns) 3983 if (Inst != &CallInst) 3984 NewCall.push_back(*Inst); 3985 NewCall.push_back(CallInst); 3986 3987 // Jump to merge block from cold call block 3988 if (!IsTailCall && !IsJumpTable) { 3989 jumpToMergeBlock(NewCall); 3990 3991 // Record merge block 3992 Results.emplace_back(MergeBlock, InstructionListType()); 3993 } 3994 3995 return Results; 3996 } 3997 3998 BlocksVectorTy jumpTablePromotion( 3999 const MCInst &IJmpInst, 4000 const std::vector<std::pair<MCSymbol *,uint64_t>> &Targets, 4001 const std::vector<MCInst *> &TargetFetchInsns, 4002 MCContext *Ctx 4003 ) const override { 4004 assert(getJumpTable(IJmpInst) != 0); 4005 uint16_t IndexReg = getAnnotationAs<uint16_t>(IJmpInst, "JTIndexReg"); 4006 if (IndexReg == 0) 4007 return BlocksVectorTy(); 4008 4009 BlocksVectorTy Results; 4010 4011 // Label for the current code block. 4012 MCSymbol *NextTarget = nullptr; 4013 4014 for (unsigned int i = 0; i < Targets.size(); ++i) { 4015 Results.emplace_back(NextTarget, InstructionListType()); 4016 InstructionListType *CurBB = &Results.back().second; 4017 4018 // Compare current index to a specific index. 4019 CurBB->emplace_back(MCInst()); 4020 MCInst &CompareInst = CurBB->back(); 4021 CompareInst.setLoc(IJmpInst.getLoc()); 4022 CompareInst.setOpcode(X86::CMP64ri32); 4023 CompareInst.addOperand(MCOperand::createReg(IndexReg)); 4024 4025 const uint64_t CaseIdx = Targets[i].second; 4026 // Immediate address is out of sign extended 32 bit range. 4027 if (int64_t(CaseIdx) != int64_t(int32_t(CaseIdx))) 4028 return BlocksVectorTy(); 4029 4030 CompareInst.addOperand(MCOperand::createImm(CaseIdx)); 4031 shortenInstruction(CompareInst); 4032 4033 // jump to next target compare. 4034 NextTarget = 4035 Ctx->createNamedTempSymbol(); // generate label for the next block 4036 CurBB->push_back(MCInst()); 4037 4038 MCInst &JEInst = CurBB->back(); 4039 JEInst.setLoc(IJmpInst.getLoc()); 4040 4041 // Jump to target if indices match 4042 JEInst.setOpcode(X86::JCC_1); 4043 JEInst.addOperand(MCOperand::createExpr(MCSymbolRefExpr::create( 4044 Targets[i].first, MCSymbolRefExpr::VK_None, *Ctx))); 4045 JEInst.addOperand(MCOperand::createImm(X86::COND_E)); 4046 } 4047 4048 // Cold call block. 4049 Results.emplace_back(NextTarget, InstructionListType()); 4050 InstructionListType &CurBB = Results.back().second; 4051 for (const MCInst *Inst : TargetFetchInsns) 4052 if (Inst != &IJmpInst) 4053 CurBB.push_back(*Inst); 4054 4055 CurBB.push_back(IJmpInst); 4056 4057 return Results; 4058 } 4059 4060 private: 4061 4062 bool createMove(MCInst &Inst, const MCSymbol *Src, unsigned Reg, 4063 MCContext *Ctx) const { 4064 Inst.setOpcode(X86::MOV64rm); 4065 Inst.addOperand(MCOperand::createReg(Reg)); 4066 Inst.addOperand(MCOperand::createReg(X86::RIP)); // BaseReg 4067 Inst.addOperand(MCOperand::createImm(1)); // ScaleAmt 4068 Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // IndexReg 4069 Inst.addOperand(MCOperand::createExpr( 4070 MCSymbolRefExpr::create(Src, MCSymbolRefExpr::VK_None, 4071 *Ctx))); // Displacement 4072 Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // AddrSegmentReg 4073 4074 return true; 4075 } 4076 4077 bool createLea(MCInst &Inst, const MCSymbol *Src, unsigned Reg, 4078 MCContext *Ctx) const { 4079 Inst.setOpcode(X86::LEA64r); 4080 Inst.addOperand(MCOperand::createReg(Reg)); 4081 Inst.addOperand(MCOperand::createReg(X86::RIP)); // BaseReg 4082 Inst.addOperand(MCOperand::createImm(1)); // ScaleAmt 4083 Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // IndexReg 4084 Inst.addOperand(MCOperand::createExpr( 4085 MCSymbolRefExpr::create(Src, MCSymbolRefExpr::VK_None, 4086 *Ctx))); // Displacement 4087 Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // AddrSegmentReg 4088 return true; 4089 } 4090 }; 4091 4092 } 4093 4094 namespace llvm { 4095 namespace bolt { 4096 4097 MCPlusBuilder *createX86MCPlusBuilder(const MCInstrAnalysis *Analysis, 4098 const MCInstrInfo *Info, 4099 const MCRegisterInfo *RegInfo) { 4100 return new X86MCPlusBuilder(Analysis, Info, RegInfo); 4101 } 4102 4103 } 4104 } 4105