1 //===- bolt/Target/X86/X86MCPlusBuilder.cpp -------------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file provides X86-specific MCPlus builder. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "MCTargetDesc/X86BaseInfo.h" 14 #include "MCTargetDesc/X86MCTargetDesc.h" 15 #include "bolt/Core/MCPlusBuilder.h" 16 #include "llvm/MC/MCContext.h" 17 #include "llvm/MC/MCFixupKindInfo.h" 18 #include "llvm/MC/MCInstBuilder.h" 19 #include "llvm/MC/MCInstrInfo.h" 20 #include "llvm/MC/MCRegisterInfo.h" 21 #include "llvm/Support/DataExtractor.h" 22 #include "llvm/Support/Debug.h" 23 #include "llvm/Support/Errc.h" 24 #include "llvm/Support/ErrorHandling.h" 25 #include "llvm/Support/ErrorOr.h" 26 #include <set> 27 28 #define DEBUG_TYPE "bolt-x86" 29 30 using namespace llvm; 31 using namespace bolt; 32 33 namespace { 34 35 unsigned getShortBranchOpcode(unsigned Opcode) { 36 switch (Opcode) { 37 default: 38 return Opcode; 39 case X86::JMP_2: return X86::JMP_1; 40 case X86::JMP_4: return X86::JMP_1; 41 case X86::JCC_2: return X86::JCC_1; 42 case X86::JCC_4: return X86::JCC_1; 43 } 44 } 45 46 unsigned getShortArithOpcode(unsigned Opcode) { 47 switch (Opcode) { 48 default: 49 return Opcode; 50 51 // IMUL 52 case X86::IMUL16rri: return X86::IMUL16rri8; 53 case X86::IMUL16rmi: return X86::IMUL16rmi8; 54 case X86::IMUL32rri: return X86::IMUL32rri8; 55 case X86::IMUL32rmi: return X86::IMUL32rmi8; 56 case X86::IMUL64rri32: return X86::IMUL64rri8; 57 case X86::IMUL64rmi32: return X86::IMUL64rmi8; 58 59 // OR 60 case X86::OR16ri: return X86::OR16ri8; 61 case X86::OR16mi: return X86::OR16mi8; 62 case X86::OR32ri: return X86::OR32ri8; 63 case X86::OR32mi: return X86::OR32mi8; 64 case X86::OR64ri32: return X86::OR64ri8; 65 case X86::OR64mi32: return X86::OR64mi8; 66 67 // AND 68 case X86::AND16ri: return X86::AND16ri8; 69 case X86::AND16mi: return X86::AND16mi8; 70 case X86::AND32ri: return X86::AND32ri8; 71 case X86::AND32mi: return X86::AND32mi8; 72 case X86::AND64ri32: return X86::AND64ri8; 73 case X86::AND64mi32: return X86::AND64mi8; 74 75 // XOR 76 case X86::XOR16ri: return X86::XOR16ri8; 77 case X86::XOR16mi: return X86::XOR16mi8; 78 case X86::XOR32ri: return X86::XOR32ri8; 79 case X86::XOR32mi: return X86::XOR32mi8; 80 case X86::XOR64ri32: return X86::XOR64ri8; 81 case X86::XOR64mi32: return X86::XOR64mi8; 82 83 // ADD 84 case X86::ADD16ri: return X86::ADD16ri8; 85 case X86::ADD16mi: return X86::ADD16mi8; 86 case X86::ADD32ri: return X86::ADD32ri8; 87 case X86::ADD32mi: return X86::ADD32mi8; 88 case X86::ADD64ri32: return X86::ADD64ri8; 89 case X86::ADD64mi32: return X86::ADD64mi8; 90 91 // SUB 92 case X86::SUB16ri: return X86::SUB16ri8; 93 case X86::SUB16mi: return X86::SUB16mi8; 94 case X86::SUB32ri: return X86::SUB32ri8; 95 case X86::SUB32mi: return X86::SUB32mi8; 96 case X86::SUB64ri32: return X86::SUB64ri8; 97 case X86::SUB64mi32: return X86::SUB64mi8; 98 99 // CMP 100 case X86::CMP16ri: return X86::CMP16ri8; 101 case X86::CMP16mi: return X86::CMP16mi8; 102 case X86::CMP32ri: return X86::CMP32ri8; 103 case X86::CMP32mi: return X86::CMP32mi8; 104 case X86::CMP64ri32: return X86::CMP64ri8; 105 case X86::CMP64mi32: return X86::CMP64mi8; 106 107 // PUSH 108 case X86::PUSHi32: return X86::PUSH32i8; 109 case X86::PUSHi16: return X86::PUSH16i8; 110 case X86::PUSH64i32: return X86::PUSH64i8; 111 } 112 } 113 114 bool isADD(unsigned Opcode) { 115 switch (Opcode) { 116 default: 117 return false; 118 case X86::ADD16i16: 119 case X86::ADD16mi: 120 case X86::ADD16mi8: 121 case X86::ADD16mr: 122 case X86::ADD16ri: 123 case X86::ADD16ri8: 124 case X86::ADD16ri8_DB: 125 case X86::ADD16ri_DB: 126 case X86::ADD16rm: 127 case X86::ADD16rr: 128 case X86::ADD16rr_DB: 129 case X86::ADD16rr_REV: 130 case X86::ADD32i32: 131 case X86::ADD32mi: 132 case X86::ADD32mi8: 133 case X86::ADD32mr: 134 case X86::ADD32ri: 135 case X86::ADD32ri8: 136 case X86::ADD32ri8_DB: 137 case X86::ADD32ri_DB: 138 case X86::ADD32rm: 139 case X86::ADD32rr: 140 case X86::ADD32rr_DB: 141 case X86::ADD32rr_REV: 142 case X86::ADD64i32: 143 case X86::ADD64mi32: 144 case X86::ADD64mi8: 145 case X86::ADD64mr: 146 case X86::ADD64ri32: 147 case X86::ADD64ri32_DB: 148 case X86::ADD64ri8: 149 case X86::ADD64ri8_DB: 150 case X86::ADD64rm: 151 case X86::ADD64rr: 152 case X86::ADD64rr_DB: 153 case X86::ADD64rr_REV: 154 case X86::ADD8i8: 155 case X86::ADD8mi: 156 case X86::ADD8mi8: 157 case X86::ADD8mr: 158 case X86::ADD8ri: 159 case X86::ADD8ri8: 160 case X86::ADD8rm: 161 case X86::ADD8rr: 162 case X86::ADD8rr_REV: 163 return true; 164 } 165 } 166 167 bool isAND(unsigned Opcode) { 168 switch (Opcode) { 169 default: 170 return false; 171 case X86::AND16i16: 172 case X86::AND16mi: 173 case X86::AND16mi8: 174 case X86::AND16mr: 175 case X86::AND16ri: 176 case X86::AND16ri8: 177 case X86::AND16rm: 178 case X86::AND16rr: 179 case X86::AND16rr_REV: 180 case X86::AND32i32: 181 case X86::AND32mi: 182 case X86::AND32mi8: 183 case X86::AND32mr: 184 case X86::AND32ri: 185 case X86::AND32ri8: 186 case X86::AND32rm: 187 case X86::AND32rr: 188 case X86::AND32rr_REV: 189 case X86::AND64i32: 190 case X86::AND64mi32: 191 case X86::AND64mi8: 192 case X86::AND64mr: 193 case X86::AND64ri32: 194 case X86::AND64ri8: 195 case X86::AND64rm: 196 case X86::AND64rr: 197 case X86::AND64rr_REV: 198 case X86::AND8i8: 199 case X86::AND8mi: 200 case X86::AND8mi8: 201 case X86::AND8mr: 202 case X86::AND8ri: 203 case X86::AND8ri8: 204 case X86::AND8rm: 205 case X86::AND8rr: 206 case X86::AND8rr_REV: 207 return true; 208 } 209 } 210 211 bool isCMP(unsigned Opcode) { 212 switch (Opcode) { 213 default: 214 return false; 215 case X86::CMP16i16: 216 case X86::CMP16mi: 217 case X86::CMP16mi8: 218 case X86::CMP16mr: 219 case X86::CMP16ri: 220 case X86::CMP16ri8: 221 case X86::CMP16rm: 222 case X86::CMP16rr: 223 case X86::CMP16rr_REV: 224 case X86::CMP32i32: 225 case X86::CMP32mi: 226 case X86::CMP32mi8: 227 case X86::CMP32mr: 228 case X86::CMP32ri: 229 case X86::CMP32ri8: 230 case X86::CMP32rm: 231 case X86::CMP32rr: 232 case X86::CMP32rr_REV: 233 case X86::CMP64i32: 234 case X86::CMP64mi32: 235 case X86::CMP64mi8: 236 case X86::CMP64mr: 237 case X86::CMP64ri32: 238 case X86::CMP64ri8: 239 case X86::CMP64rm: 240 case X86::CMP64rr: 241 case X86::CMP64rr_REV: 242 case X86::CMP8i8: 243 case X86::CMP8mi: 244 case X86::CMP8mi8: 245 case X86::CMP8mr: 246 case X86::CMP8ri: 247 case X86::CMP8ri8: 248 case X86::CMP8rm: 249 case X86::CMP8rr: 250 case X86::CMP8rr_REV: 251 return true; 252 } 253 } 254 255 bool isDEC(unsigned Opcode) { 256 switch (Opcode) { 257 default: 258 return false; 259 case X86::DEC16m: 260 case X86::DEC16r: 261 case X86::DEC16r_alt: 262 case X86::DEC32m: 263 case X86::DEC32r: 264 case X86::DEC32r_alt: 265 case X86::DEC64r: 266 case X86::DEC64m: 267 case X86::DEC8m: 268 case X86::DEC8r: 269 return true; 270 } 271 } 272 273 bool isINC(unsigned Opcode) { 274 switch (Opcode) { 275 default: 276 return false; 277 case X86::INC16m: 278 case X86::INC16r: 279 case X86::INC16r_alt: 280 case X86::INC32m: 281 case X86::INC32r: 282 case X86::INC32r_alt: 283 case X86::INC64r: 284 case X86::INC64m: 285 case X86::INC8m: 286 case X86::INC8r: 287 return true; 288 } 289 } 290 291 bool isSUB(unsigned Opcode) { 292 switch (Opcode) { 293 default: 294 return false; 295 case X86::SUB16i16: 296 case X86::SUB16mi: 297 case X86::SUB16mi8: 298 case X86::SUB16mr: 299 case X86::SUB16ri: 300 case X86::SUB16ri8: 301 case X86::SUB16rm: 302 case X86::SUB16rr: 303 case X86::SUB16rr_REV: 304 case X86::SUB32i32: 305 case X86::SUB32mi: 306 case X86::SUB32mi8: 307 case X86::SUB32mr: 308 case X86::SUB32ri: 309 case X86::SUB32ri8: 310 case X86::SUB32rm: 311 case X86::SUB32rr: 312 case X86::SUB32rr_REV: 313 case X86::SUB64i32: 314 case X86::SUB64mi32: 315 case X86::SUB64mi8: 316 case X86::SUB64mr: 317 case X86::SUB64ri32: 318 case X86::SUB64ri8: 319 case X86::SUB64rm: 320 case X86::SUB64rr: 321 case X86::SUB64rr_REV: 322 case X86::SUB8i8: 323 case X86::SUB8mi: 324 case X86::SUB8mi8: 325 case X86::SUB8mr: 326 case X86::SUB8ri: 327 case X86::SUB8ri8: 328 case X86::SUB8rm: 329 case X86::SUB8rr: 330 case X86::SUB8rr_REV: 331 return true; 332 } 333 } 334 335 bool isTEST(unsigned Opcode) { 336 switch (Opcode) { 337 default: 338 return false; 339 case X86::TEST16i16: 340 case X86::TEST16mi: 341 case X86::TEST16mr: 342 case X86::TEST16ri: 343 case X86::TEST16rr: 344 case X86::TEST32i32: 345 case X86::TEST32mi: 346 case X86::TEST32mr: 347 case X86::TEST32ri: 348 case X86::TEST32rr: 349 case X86::TEST64i32: 350 case X86::TEST64mi32: 351 case X86::TEST64mr: 352 case X86::TEST64ri32: 353 case X86::TEST64rr: 354 case X86::TEST8i8: 355 case X86::TEST8mi: 356 case X86::TEST8mr: 357 case X86::TEST8ri: 358 case X86::TEST8rr: 359 return true; 360 } 361 } 362 363 class X86MCPlusBuilder : public MCPlusBuilder { 364 public: 365 X86MCPlusBuilder(const MCInstrAnalysis *Analysis, const MCInstrInfo *Info, 366 const MCRegisterInfo *RegInfo) 367 : MCPlusBuilder(Analysis, Info, RegInfo) {} 368 369 bool isBranch(const MCInst &Inst) const override { 370 return Analysis->isBranch(Inst) && !isTailCall(Inst); 371 } 372 373 bool isUnconditionalBranch(const MCInst &Inst) const override { 374 return Analysis->isUnconditionalBranch(Inst) && !isTailCall(Inst); 375 } 376 377 bool isNoop(const MCInst &Inst) const override { 378 switch (Inst.getOpcode()) { 379 case X86::NOOP: 380 case X86::NOOPL: 381 case X86::NOOPLr: 382 case X86::NOOPQ: 383 case X86::NOOPQr: 384 case X86::NOOPW: 385 case X86::NOOPWr: 386 return true; 387 } 388 return false; 389 } 390 391 unsigned getCondCode(const MCInst &Inst) const override { 392 switch (Inst.getOpcode()) { 393 default: 394 return X86::COND_INVALID; 395 case X86::JCC_1: 396 case X86::JCC_2: 397 case X86::JCC_4: 398 return Inst.getOperand(Info->get(Inst.getOpcode()).NumOperands - 1) 399 .getImm(); 400 } 401 } 402 403 unsigned getInvertedCondCode(unsigned CC) const override { 404 switch (CC) { 405 default: return X86::COND_INVALID; 406 case X86::COND_E: return X86::COND_NE; 407 case X86::COND_NE: return X86::COND_E; 408 case X86::COND_L: return X86::COND_GE; 409 case X86::COND_LE: return X86::COND_G; 410 case X86::COND_G: return X86::COND_LE; 411 case X86::COND_GE: return X86::COND_L; 412 case X86::COND_B: return X86::COND_AE; 413 case X86::COND_BE: return X86::COND_A; 414 case X86::COND_A: return X86::COND_BE; 415 case X86::COND_AE: return X86::COND_B; 416 case X86::COND_S: return X86::COND_NS; 417 case X86::COND_NS: return X86::COND_S; 418 case X86::COND_P: return X86::COND_NP; 419 case X86::COND_NP: return X86::COND_P; 420 case X86::COND_O: return X86::COND_NO; 421 case X86::COND_NO: return X86::COND_O; 422 } 423 } 424 425 unsigned getCondCodesLogicalOr(unsigned CC1, unsigned CC2) const override { 426 enum DecodedCondCode : uint8_t { 427 DCC_EQUAL = 0x1, 428 DCC_GREATER = 0x2, 429 DCC_LESSER = 0x4, 430 DCC_GREATER_OR_LESSER = 0x6, 431 DCC_UNSIGNED = 0x8, 432 DCC_SIGNED = 0x10, 433 DCC_INVALID = 0x20, 434 }; 435 436 auto decodeCondCode = [&](unsigned CC) -> uint8_t { 437 switch (CC) { 438 default: return DCC_INVALID; 439 case X86::COND_E: return DCC_EQUAL; 440 case X86::COND_NE: return DCC_GREATER | DCC_LESSER; 441 case X86::COND_L: return DCC_LESSER | DCC_SIGNED; 442 case X86::COND_LE: return DCC_EQUAL | DCC_LESSER | DCC_SIGNED; 443 case X86::COND_G: return DCC_GREATER | DCC_SIGNED; 444 case X86::COND_GE: return DCC_GREATER | DCC_EQUAL | DCC_SIGNED; 445 case X86::COND_B: return DCC_LESSER | DCC_UNSIGNED; 446 case X86::COND_BE: return DCC_EQUAL | DCC_LESSER | DCC_UNSIGNED; 447 case X86::COND_A: return DCC_GREATER | DCC_UNSIGNED; 448 case X86::COND_AE: return DCC_GREATER | DCC_EQUAL | DCC_UNSIGNED; 449 } 450 }; 451 452 uint8_t DCC = decodeCondCode(CC1) | decodeCondCode(CC2); 453 454 if (DCC & DCC_INVALID) 455 return X86::COND_INVALID; 456 457 if (DCC & DCC_SIGNED && DCC & DCC_UNSIGNED) 458 return X86::COND_INVALID; 459 460 switch (DCC) { 461 default: return X86::COND_INVALID; 462 case DCC_EQUAL | DCC_LESSER | DCC_SIGNED: return X86::COND_LE; 463 case DCC_EQUAL | DCC_LESSER | DCC_UNSIGNED: return X86::COND_BE; 464 case DCC_EQUAL | DCC_GREATER | DCC_SIGNED: return X86::COND_GE; 465 case DCC_EQUAL | DCC_GREATER | DCC_UNSIGNED: return X86::COND_AE; 466 case DCC_GREATER | DCC_LESSER | DCC_SIGNED: return X86::COND_NE; 467 case DCC_GREATER | DCC_LESSER | DCC_UNSIGNED: return X86::COND_NE; 468 case DCC_GREATER | DCC_LESSER: return X86::COND_NE; 469 case DCC_EQUAL | DCC_SIGNED: return X86::COND_E; 470 case DCC_EQUAL | DCC_UNSIGNED: return X86::COND_E; 471 case DCC_EQUAL: return X86::COND_E; 472 case DCC_LESSER | DCC_SIGNED: return X86::COND_L; 473 case DCC_LESSER | DCC_UNSIGNED: return X86::COND_B; 474 case DCC_GREATER | DCC_SIGNED: return X86::COND_G; 475 case DCC_GREATER | DCC_UNSIGNED: return X86::COND_A; 476 } 477 } 478 479 bool isValidCondCode(unsigned CC) const override { 480 return (CC != X86::COND_INVALID); 481 } 482 483 bool isBreakpoint(const MCInst &Inst) const override { 484 return Inst.getOpcode() == X86::INT3; 485 } 486 487 bool isPrefix(const MCInst &Inst) const override { 488 switch (Inst.getOpcode()) { 489 case X86::LOCK_PREFIX: 490 case X86::REPNE_PREFIX: 491 case X86::REP_PREFIX: 492 return true; 493 } 494 return false; 495 } 496 497 bool isRep(const MCInst &Inst) const override { 498 return Inst.getFlags() == X86::IP_HAS_REPEAT; 499 } 500 501 bool deleteREPPrefix(MCInst &Inst) const override { 502 if (Inst.getFlags() == X86::IP_HAS_REPEAT) { 503 Inst.setFlags(0); 504 return true; 505 } 506 return false; 507 } 508 509 // FIXME: For compatibility with old LLVM only! 510 bool isTerminator(const MCInst &Inst) const override { 511 if (Info->get(Inst.getOpcode()).isTerminator()) 512 return true; 513 switch (Inst.getOpcode()) { 514 default: 515 return false; 516 case X86::TRAP: 517 // Opcodes previously known as X86::UD2B 518 case X86::UD1Wm: 519 case X86::UD1Lm: 520 case X86::UD1Qm: 521 case X86::UD1Wr: 522 case X86::UD1Lr: 523 case X86::UD1Qr: 524 return true; 525 } 526 } 527 528 bool isIndirectCall(const MCInst &Inst) const override { 529 return isCall(Inst) && 530 ((getMemoryOperandNo(Inst) != -1) || Inst.getOperand(0).isReg()); 531 } 532 533 bool isPop(const MCInst &Inst) const override { 534 return getPopSize(Inst) == 0 ? false : true; 535 } 536 537 bool isTerminateBranch(const MCInst &Inst) const override { 538 return Inst.getOpcode() == X86::ENDBR32 || Inst.getOpcode() == X86::ENDBR64; 539 } 540 541 int getPopSize(const MCInst &Inst) const override { 542 switch (Inst.getOpcode()) { 543 case X86::POP16r: 544 case X86::POP16rmm: 545 case X86::POP16rmr: 546 case X86::POPF16: 547 case X86::POPA16: 548 case X86::POPDS16: 549 case X86::POPES16: 550 case X86::POPFS16: 551 case X86::POPGS16: 552 case X86::POPSS16: 553 return 2; 554 case X86::POP32r: 555 case X86::POP32rmm: 556 case X86::POP32rmr: 557 case X86::POPA32: 558 case X86::POPDS32: 559 case X86::POPES32: 560 case X86::POPF32: 561 case X86::POPFS32: 562 case X86::POPGS32: 563 case X86::POPSS32: 564 return 4; 565 case X86::POP64r: 566 case X86::POP64rmm: 567 case X86::POP64rmr: 568 case X86::POPF64: 569 case X86::POPFS64: 570 case X86::POPGS64: 571 return 8; 572 } 573 return 0; 574 } 575 576 bool isPush(const MCInst &Inst) const override { 577 return getPushSize(Inst) == 0 ? false : true; 578 } 579 580 int getPushSize(const MCInst &Inst) const override { 581 switch (Inst.getOpcode()) { 582 case X86::PUSH16i8: 583 case X86::PUSH16r: 584 case X86::PUSH16rmm: 585 case X86::PUSH16rmr: 586 case X86::PUSHA16: 587 case X86::PUSHCS16: 588 case X86::PUSHDS16: 589 case X86::PUSHES16: 590 case X86::PUSHF16: 591 case X86::PUSHFS16: 592 case X86::PUSHGS16: 593 case X86::PUSHSS16: 594 case X86::PUSHi16: 595 return 2; 596 case X86::PUSH32i8: 597 case X86::PUSH32r: 598 case X86::PUSH32rmm: 599 case X86::PUSH32rmr: 600 case X86::PUSHA32: 601 case X86::PUSHCS32: 602 case X86::PUSHDS32: 603 case X86::PUSHES32: 604 case X86::PUSHF32: 605 case X86::PUSHFS32: 606 case X86::PUSHGS32: 607 case X86::PUSHSS32: 608 case X86::PUSHi32: 609 return 4; 610 case X86::PUSH64i32: 611 case X86::PUSH64i8: 612 case X86::PUSH64r: 613 case X86::PUSH64rmm: 614 case X86::PUSH64rmr: 615 case X86::PUSHF64: 616 case X86::PUSHFS64: 617 case X86::PUSHGS64: 618 return 8; 619 } 620 return 0; 621 } 622 623 bool isADD64rr(const MCInst &Inst) const override { 624 return Inst.getOpcode() == X86::ADD64rr; 625 } 626 627 bool isSUB(const MCInst &Inst) const override { 628 return ::isSUB(Inst.getOpcode()); 629 } 630 631 bool isADDri(const MCInst &Inst) const { 632 return Inst.getOpcode() == X86::ADD64ri32 || 633 Inst.getOpcode() == X86::ADD64ri8; 634 } 635 636 bool isLEA64r(const MCInst &Inst) const override { 637 return Inst.getOpcode() == X86::LEA64r; 638 } 639 640 bool isMOVSX64rm32(const MCInst &Inst) const override { 641 return Inst.getOpcode() == X86::MOVSX64rm32; 642 } 643 644 bool isLeave(const MCInst &Inst) const override { 645 return Inst.getOpcode() == X86::LEAVE || 646 Inst.getOpcode() == X86::LEAVE64; 647 } 648 649 bool isMoveMem2Reg(const MCInst &Inst) const override { 650 switch (Inst.getOpcode()) { 651 case X86::MOV16rm: 652 case X86::MOV32rm: 653 case X86::MOV64rm: 654 return true; 655 } 656 return false; 657 } 658 659 bool isUnsupportedBranch(unsigned Opcode) const override { 660 switch (Opcode) { 661 default: 662 return false; 663 case X86::LOOP: 664 case X86::LOOPE: 665 case X86::LOOPNE: 666 case X86::JECXZ: 667 case X86::JRCXZ: 668 return true; 669 } 670 } 671 672 bool isLoad(const MCInst &Inst) const override { 673 if (isPop(Inst)) 674 return true; 675 676 int MemOpNo = getMemoryOperandNo(Inst); 677 const MCInstrDesc &MCII = Info->get(Inst.getOpcode()); 678 679 if (MemOpNo == -1) 680 return false; 681 682 return MCII.mayLoad(); 683 } 684 685 bool isStore(const MCInst &Inst) const override { 686 if (isPush(Inst)) 687 return true; 688 689 int MemOpNo = getMemoryOperandNo(Inst); 690 const MCInstrDesc &MCII = Info->get(Inst.getOpcode()); 691 692 if (MemOpNo == -1) 693 return false; 694 695 return MCII.mayStore(); 696 } 697 698 bool isCleanRegXOR(const MCInst &Inst) const override { 699 switch (Inst.getOpcode()) { 700 case X86::XOR16rr: 701 case X86::XOR32rr: 702 case X86::XOR64rr: 703 break; 704 default: 705 return false; 706 } 707 return (Inst.getOperand(0).getReg() == 708 Inst.getOperand(2).getReg()); 709 } 710 711 bool isPacked(const MCInst &Inst) const override { 712 const MCInstrDesc &Desc = Info->get(Inst.getOpcode()); 713 return (Desc.TSFlags & X86II::OpPrefixMask) == X86II::PD; 714 } 715 716 unsigned getTrapFillValue() const override { return 0xCC; } 717 718 struct IndJmpMatcherFrag1 : MCInstMatcher { 719 std::unique_ptr<MCInstMatcher> Base; 720 std::unique_ptr<MCInstMatcher> Scale; 721 std::unique_ptr<MCInstMatcher> Index; 722 std::unique_ptr<MCInstMatcher> Offset; 723 724 IndJmpMatcherFrag1(std::unique_ptr<MCInstMatcher> Base, 725 std::unique_ptr<MCInstMatcher> Scale, 726 std::unique_ptr<MCInstMatcher> Index, 727 std::unique_ptr<MCInstMatcher> Offset) 728 : Base(std::move(Base)), Scale(std::move(Scale)), 729 Index(std::move(Index)), Offset(std::move(Offset)) {} 730 731 bool match(const MCRegisterInfo &MRI, MCPlusBuilder &MIB, 732 MutableArrayRef<MCInst> InInstrWindow, int OpNum) override { 733 if (!MCInstMatcher::match(MRI, MIB, InInstrWindow, OpNum)) 734 return false; 735 736 if (CurInst->getOpcode() != X86::JMP64m) 737 return false; 738 739 int MemOpNo = MIB.getMemoryOperandNo(*CurInst); 740 if (MemOpNo == -1) 741 return false; 742 743 if (!Base->match(MRI, MIB, this->InstrWindow, MemOpNo + X86::AddrBaseReg)) 744 return false; 745 if (!Scale->match(MRI, MIB, this->InstrWindow, 746 MemOpNo + X86::AddrScaleAmt)) 747 return false; 748 if (!Index->match(MRI, MIB, this->InstrWindow, 749 MemOpNo + X86::AddrIndexReg)) 750 return false; 751 if (!Offset->match(MRI, MIB, this->InstrWindow, MemOpNo + X86::AddrDisp)) 752 return false; 753 return true; 754 } 755 756 void annotate(MCPlusBuilder &MIB, StringRef Annotation) override { 757 MIB.addAnnotation(*CurInst, Annotation, true); 758 Base->annotate(MIB, Annotation); 759 Scale->annotate(MIB, Annotation); 760 Index->annotate(MIB, Annotation); 761 Offset->annotate(MIB, Annotation); 762 } 763 }; 764 765 std::unique_ptr<MCInstMatcher> 766 matchIndJmp(std::unique_ptr<MCInstMatcher> Base, 767 std::unique_ptr<MCInstMatcher> Scale, 768 std::unique_ptr<MCInstMatcher> Index, 769 std::unique_ptr<MCInstMatcher> Offset) const override { 770 return std::unique_ptr<MCInstMatcher>( 771 new IndJmpMatcherFrag1(std::move(Base), std::move(Scale), 772 std::move(Index), std::move(Offset))); 773 } 774 775 struct IndJmpMatcherFrag2 : MCInstMatcher { 776 std::unique_ptr<MCInstMatcher> Reg; 777 778 IndJmpMatcherFrag2(std::unique_ptr<MCInstMatcher> Reg) 779 : Reg(std::move(Reg)) {} 780 781 bool match(const MCRegisterInfo &MRI, MCPlusBuilder &MIB, 782 MutableArrayRef<MCInst> InInstrWindow, int OpNum) override { 783 if (!MCInstMatcher::match(MRI, MIB, InInstrWindow, OpNum)) 784 return false; 785 786 if (CurInst->getOpcode() != X86::JMP64r) 787 return false; 788 789 return Reg->match(MRI, MIB, this->InstrWindow, 0); 790 } 791 792 void annotate(MCPlusBuilder &MIB, StringRef Annotation) override { 793 MIB.addAnnotation(*CurInst, Annotation, true); 794 Reg->annotate(MIB, Annotation); 795 } 796 }; 797 798 std::unique_ptr<MCInstMatcher> 799 matchIndJmp(std::unique_ptr<MCInstMatcher> Target) const override { 800 return std::unique_ptr<MCInstMatcher>( 801 new IndJmpMatcherFrag2(std::move(Target))); 802 } 803 804 struct LoadMatcherFrag1 : MCInstMatcher { 805 std::unique_ptr<MCInstMatcher> Base; 806 std::unique_ptr<MCInstMatcher> Scale; 807 std::unique_ptr<MCInstMatcher> Index; 808 std::unique_ptr<MCInstMatcher> Offset; 809 810 LoadMatcherFrag1(std::unique_ptr<MCInstMatcher> Base, 811 std::unique_ptr<MCInstMatcher> Scale, 812 std::unique_ptr<MCInstMatcher> Index, 813 std::unique_ptr<MCInstMatcher> Offset) 814 : Base(std::move(Base)), Scale(std::move(Scale)), 815 Index(std::move(Index)), Offset(std::move(Offset)) {} 816 817 bool match(const MCRegisterInfo &MRI, MCPlusBuilder &MIB, 818 MutableArrayRef<MCInst> InInstrWindow, int OpNum) override { 819 if (!MCInstMatcher::match(MRI, MIB, InInstrWindow, OpNum)) 820 return false; 821 822 if (CurInst->getOpcode() != X86::MOV64rm && 823 CurInst->getOpcode() != X86::MOVSX64rm32) 824 return false; 825 826 int MemOpNo = MIB.getMemoryOperandNo(*CurInst); 827 if (MemOpNo == -1) 828 return false; 829 830 if (!Base->match(MRI, MIB, this->InstrWindow, MemOpNo + X86::AddrBaseReg)) 831 return false; 832 if (!Scale->match(MRI, MIB, this->InstrWindow, 833 MemOpNo + X86::AddrScaleAmt)) 834 return false; 835 if (!Index->match(MRI, MIB, this->InstrWindow, 836 MemOpNo + X86::AddrIndexReg)) 837 return false; 838 if (!Offset->match(MRI, MIB, this->InstrWindow, MemOpNo + X86::AddrDisp)) 839 return false; 840 return true; 841 } 842 843 void annotate(MCPlusBuilder &MIB, StringRef Annotation) override { 844 MIB.addAnnotation(*CurInst, Annotation, true); 845 Base->annotate(MIB, Annotation); 846 Scale->annotate(MIB, Annotation); 847 Index->annotate(MIB, Annotation); 848 Offset->annotate(MIB, Annotation); 849 } 850 }; 851 852 std::unique_ptr<MCInstMatcher> 853 matchLoad(std::unique_ptr<MCInstMatcher> Base, 854 std::unique_ptr<MCInstMatcher> Scale, 855 std::unique_ptr<MCInstMatcher> Index, 856 std::unique_ptr<MCInstMatcher> Offset) const override { 857 return std::unique_ptr<MCInstMatcher>( 858 new LoadMatcherFrag1(std::move(Base), std::move(Scale), 859 std::move(Index), std::move(Offset))); 860 } 861 862 struct AddMatcher : MCInstMatcher { 863 std::unique_ptr<MCInstMatcher> A; 864 std::unique_ptr<MCInstMatcher> B; 865 866 AddMatcher(std::unique_ptr<MCInstMatcher> A, 867 std::unique_ptr<MCInstMatcher> B) 868 : A(std::move(A)), B(std::move(B)) {} 869 870 bool match(const MCRegisterInfo &MRI, MCPlusBuilder &MIB, 871 MutableArrayRef<MCInst> InInstrWindow, int OpNum) override { 872 if (!MCInstMatcher::match(MRI, MIB, InInstrWindow, OpNum)) 873 return false; 874 875 if (CurInst->getOpcode() == X86::ADD64rr || 876 CurInst->getOpcode() == X86::ADD64rr_DB || 877 CurInst->getOpcode() == X86::ADD64rr_REV) { 878 if (!A->match(MRI, MIB, this->InstrWindow, 1)) { 879 if (!B->match(MRI, MIB, this->InstrWindow, 1)) 880 return false; 881 return A->match(MRI, MIB, this->InstrWindow, 2); 882 } 883 884 if (B->match(MRI, MIB, this->InstrWindow, 2)) 885 return true; 886 887 if (!B->match(MRI, MIB, this->InstrWindow, 1)) 888 return false; 889 return A->match(MRI, MIB, this->InstrWindow, 2); 890 } 891 892 return false; 893 } 894 895 void annotate(MCPlusBuilder &MIB, StringRef Annotation) override { 896 MIB.addAnnotation(*CurInst, Annotation, true); 897 A->annotate(MIB, Annotation); 898 B->annotate(MIB, Annotation); 899 } 900 }; 901 902 virtual std::unique_ptr<MCInstMatcher> 903 matchAdd(std::unique_ptr<MCInstMatcher> A, 904 std::unique_ptr<MCInstMatcher> B) const override { 905 return std::unique_ptr<MCInstMatcher>( 906 new AddMatcher(std::move(A), std::move(B))); 907 } 908 909 struct LEAMatcher : MCInstMatcher { 910 std::unique_ptr<MCInstMatcher> Target; 911 912 LEAMatcher(std::unique_ptr<MCInstMatcher> Target) 913 : Target(std::move(Target)) {} 914 915 bool match(const MCRegisterInfo &MRI, MCPlusBuilder &MIB, 916 MutableArrayRef<MCInst> InInstrWindow, int OpNum) override { 917 if (!MCInstMatcher::match(MRI, MIB, InInstrWindow, OpNum)) 918 return false; 919 920 if (CurInst->getOpcode() != X86::LEA64r) 921 return false; 922 923 if (CurInst->getOperand(1 + X86::AddrScaleAmt).getImm() != 1 || 924 CurInst->getOperand(1 + X86::AddrIndexReg).getReg() != 925 X86::NoRegister || 926 (CurInst->getOperand(1 + X86::AddrBaseReg).getReg() != 927 X86::NoRegister && 928 CurInst->getOperand(1 + X86::AddrBaseReg).getReg() != X86::RIP)) 929 return false; 930 931 return Target->match(MRI, MIB, this->InstrWindow, 1 + X86::AddrDisp); 932 } 933 934 void annotate(MCPlusBuilder &MIB, StringRef Annotation) override { 935 MIB.addAnnotation(*CurInst, Annotation, true); 936 Target->annotate(MIB, Annotation); 937 } 938 }; 939 940 virtual std::unique_ptr<MCInstMatcher> 941 matchLoadAddr(std::unique_ptr<MCInstMatcher> Target) const override { 942 return std::unique_ptr<MCInstMatcher>(new LEAMatcher(std::move(Target))); 943 } 944 945 bool hasPCRelOperand(const MCInst &Inst) const override { 946 for (const MCOperand &Operand : Inst) { 947 if (Operand.isReg() && Operand.getReg() == X86::RIP) 948 return true; 949 } 950 return false; 951 } 952 953 int getMemoryOperandNo(const MCInst &Inst) const override { 954 unsigned Opcode = Inst.getOpcode(); 955 const MCInstrDesc &Desc = Info->get(Opcode); 956 int MemOpNo = X86II::getMemoryOperandNo(Desc.TSFlags); 957 if (MemOpNo >= 0) 958 MemOpNo += X86II::getOperandBias(Desc); 959 return MemOpNo; 960 } 961 962 bool hasEVEXEncoding(const MCInst &Inst) const override { 963 const MCInstrDesc &Desc = Info->get(Inst.getOpcode()); 964 return (Desc.TSFlags & X86II::EncodingMask) == X86II::EVEX; 965 } 966 967 bool isMacroOpFusionPair(ArrayRef<MCInst> Insts) const override { 968 // FIXME: the macro-op fusion is triggered under different conditions 969 // on different cores. This implementation is for sandy-bridge+. 970 const auto *I = Insts.begin(); 971 while (I != Insts.end() && isPrefix(*I)) 972 ++I; 973 if (I == Insts.end()) 974 return false; 975 976 const MCInst &FirstInst = *I; 977 ++I; 978 while (I != Insts.end() && isPrefix(*I)) 979 ++I; 980 if (I == Insts.end()) 981 return false; 982 const MCInst &SecondInst = *I; 983 984 if (!isConditionalBranch(SecondInst)) 985 return false; 986 // J?CXZ and LOOP cannot be fused 987 if (SecondInst.getOpcode() == X86::LOOP || 988 SecondInst.getOpcode() == X86::LOOPE || 989 SecondInst.getOpcode() == X86::LOOPNE || 990 SecondInst.getOpcode() == X86::JECXZ || 991 SecondInst.getOpcode() == X86::JRCXZ) 992 return false; 993 994 // Cannot fuse if first instruction operands are MEM-IMM. 995 const MCInstrDesc &Desc = Info->get(FirstInst.getOpcode()); 996 int MemOpNo = X86II::getMemoryOperandNo(Desc.TSFlags); 997 if (MemOpNo != -1 && X86II::hasImm(Desc.TSFlags)) 998 return false; 999 1000 // Cannot fuse if the first instruction uses RIP-relative memory. 1001 // FIXME: verify that this is true. 1002 if (hasPCRelOperand(FirstInst)) 1003 return false; 1004 1005 // Check instructions against table 3-1 in Intel's Optimization Guide. 1006 unsigned FirstInstGroup = 0; 1007 if (isTEST(FirstInst.getOpcode()) || isAND(FirstInst.getOpcode())) { 1008 FirstInstGroup = 1; 1009 } else if (isCMP(FirstInst.getOpcode()) || isADD(FirstInst.getOpcode()) || 1010 ::isSUB(FirstInst.getOpcode())) { 1011 FirstInstGroup = 2; 1012 } else if (isINC(FirstInst.getOpcode()) || isDEC(FirstInst.getOpcode())) { 1013 FirstInstGroup = 3; 1014 } 1015 if (FirstInstGroup == 0) 1016 return false; 1017 1018 const unsigned CondCode = 1019 getCanonicalBranchCondCode(getCondCode(SecondInst)); 1020 switch (CondCode) { 1021 default: 1022 llvm_unreachable("unexpected conditional code"); 1023 return false; 1024 case X86::COND_E: 1025 case X86::COND_L: 1026 case X86::COND_G: 1027 return true; 1028 case X86::COND_O: 1029 case X86::COND_P: 1030 case X86::COND_S: 1031 if (FirstInstGroup == 1) 1032 return true; 1033 return false; 1034 case X86::COND_A: 1035 case X86::COND_B: 1036 if (FirstInstGroup != 3) 1037 return true; 1038 return false; 1039 } 1040 } 1041 1042 bool evaluateX86MemoryOperand(const MCInst &Inst, 1043 unsigned *BaseRegNum, 1044 int64_t *ScaleImm, 1045 unsigned *IndexRegNum, 1046 int64_t *DispImm, 1047 unsigned *SegmentRegNum, 1048 const MCExpr **DispExpr = nullptr) 1049 const override { 1050 assert(BaseRegNum && ScaleImm && IndexRegNum && SegmentRegNum && 1051 "one of the input pointers is null"); 1052 int MemOpNo = getMemoryOperandNo(Inst); 1053 if (MemOpNo < 0) 1054 return false; 1055 unsigned MemOpOffset = static_cast<unsigned>(MemOpNo); 1056 1057 if (MemOpOffset + X86::AddrSegmentReg >= MCPlus::getNumPrimeOperands(Inst)) 1058 return false; 1059 1060 const MCOperand &Base = Inst.getOperand(MemOpOffset + X86::AddrBaseReg); 1061 const MCOperand &Scale = Inst.getOperand(MemOpOffset + X86::AddrScaleAmt); 1062 const MCOperand &Index = Inst.getOperand(MemOpOffset + X86::AddrIndexReg); 1063 const MCOperand &Disp = Inst.getOperand(MemOpOffset + X86::AddrDisp); 1064 const MCOperand &Segment = 1065 Inst.getOperand(MemOpOffset + X86::AddrSegmentReg); 1066 1067 // Make sure it is a well-formed memory operand. 1068 if (!Base.isReg() || !Scale.isImm() || !Index.isReg() || 1069 (!Disp.isImm() && !Disp.isExpr()) || !Segment.isReg()) 1070 return false; 1071 1072 *BaseRegNum = Base.getReg(); 1073 *ScaleImm = Scale.getImm(); 1074 *IndexRegNum = Index.getReg(); 1075 if (Disp.isImm()) { 1076 assert(DispImm && "DispImm needs to be set"); 1077 *DispImm = Disp.getImm(); 1078 if (DispExpr) { 1079 *DispExpr = nullptr; 1080 } 1081 } else { 1082 assert(DispExpr && "DispExpr needs to be set"); 1083 *DispExpr = Disp.getExpr(); 1084 if (DispImm) { 1085 *DispImm = 0; 1086 } 1087 } 1088 *SegmentRegNum = Segment.getReg(); 1089 return true; 1090 } 1091 1092 bool evaluateMemOperandTarget(const MCInst &Inst, 1093 uint64_t &Target, 1094 uint64_t Address, 1095 uint64_t Size) const override { 1096 unsigned BaseRegNum; 1097 int64_t ScaleValue; 1098 unsigned IndexRegNum; 1099 int64_t DispValue; 1100 unsigned SegRegNum; 1101 const MCExpr *DispExpr = nullptr; 1102 if (!evaluateX86MemoryOperand(Inst, &BaseRegNum, &ScaleValue, &IndexRegNum, 1103 &DispValue, &SegRegNum, &DispExpr)) { 1104 return false; 1105 } 1106 1107 // Make sure it's a well-formed addressing we can statically evaluate. 1108 if ((BaseRegNum != X86::RIP && BaseRegNum != X86::NoRegister) || 1109 IndexRegNum != X86::NoRegister || SegRegNum != X86::NoRegister || 1110 DispExpr) { 1111 return false; 1112 } 1113 Target = DispValue; 1114 if (BaseRegNum == X86::RIP) { 1115 assert(Size != 0 && "instruction size required in order to statically " 1116 "evaluate RIP-relative address"); 1117 Target += Address + Size; 1118 } 1119 return true; 1120 } 1121 1122 MCInst::iterator getMemOperandDisp(MCInst &Inst) const override { 1123 int MemOpNo = getMemoryOperandNo(Inst); 1124 if (MemOpNo < 0) 1125 return Inst.end(); 1126 return Inst.begin() + (MemOpNo + X86::AddrDisp); 1127 } 1128 1129 bool replaceMemOperandDisp(MCInst &Inst, MCOperand Operand) const override { 1130 MCOperand *OI = getMemOperandDisp(Inst); 1131 if (OI == Inst.end()) 1132 return false; 1133 *OI = Operand; 1134 return true; 1135 } 1136 1137 /// Get the registers used as function parameters. 1138 /// This function is specific to the x86_64 abi on Linux. 1139 BitVector getRegsUsedAsParams() const override { 1140 BitVector Regs = BitVector(RegInfo->getNumRegs(), false); 1141 Regs |= getAliases(X86::RSI); 1142 Regs |= getAliases(X86::RDI); 1143 Regs |= getAliases(X86::RDX); 1144 Regs |= getAliases(X86::RCX); 1145 Regs |= getAliases(X86::R8); 1146 Regs |= getAliases(X86::R9); 1147 return Regs; 1148 } 1149 1150 void getCalleeSavedRegs(BitVector &Regs) const override { 1151 Regs |= getAliases(X86::RBX); 1152 Regs |= getAliases(X86::RBP); 1153 Regs |= getAliases(X86::R12); 1154 Regs |= getAliases(X86::R13); 1155 Regs |= getAliases(X86::R14); 1156 Regs |= getAliases(X86::R15); 1157 } 1158 1159 void getDefaultDefIn(BitVector &Regs) const override { 1160 assert(Regs.size() >= RegInfo->getNumRegs() && 1161 "The size of BitVector is less than RegInfo->getNumRegs()."); 1162 Regs.set(X86::RAX); 1163 Regs.set(X86::RCX); 1164 Regs.set(X86::RDX); 1165 Regs.set(X86::RSI); 1166 Regs.set(X86::RDI); 1167 Regs.set(X86::R8); 1168 Regs.set(X86::R9); 1169 Regs.set(X86::XMM0); 1170 Regs.set(X86::XMM1); 1171 Regs.set(X86::XMM2); 1172 Regs.set(X86::XMM3); 1173 Regs.set(X86::XMM4); 1174 Regs.set(X86::XMM5); 1175 Regs.set(X86::XMM6); 1176 Regs.set(X86::XMM7); 1177 } 1178 1179 void getDefaultLiveOut(BitVector &Regs) const override { 1180 assert(Regs.size() >= RegInfo->getNumRegs() && 1181 "The size of BitVector is less than RegInfo->getNumRegs()."); 1182 Regs |= getAliases(X86::RAX); 1183 Regs |= getAliases(X86::RDX); 1184 Regs |= getAliases(X86::RCX); 1185 Regs |= getAliases(X86::XMM0); 1186 Regs |= getAliases(X86::XMM1); 1187 } 1188 1189 void getGPRegs(BitVector &Regs, bool IncludeAlias) const override { 1190 if (IncludeAlias) { 1191 Regs |= getAliases(X86::RAX); 1192 Regs |= getAliases(X86::RBX); 1193 Regs |= getAliases(X86::RBP); 1194 Regs |= getAliases(X86::RSI); 1195 Regs |= getAliases(X86::RDI); 1196 Regs |= getAliases(X86::RDX); 1197 Regs |= getAliases(X86::RCX); 1198 Regs |= getAliases(X86::R8); 1199 Regs |= getAliases(X86::R9); 1200 Regs |= getAliases(X86::R10); 1201 Regs |= getAliases(X86::R11); 1202 Regs |= getAliases(X86::R12); 1203 Regs |= getAliases(X86::R13); 1204 Regs |= getAliases(X86::R14); 1205 Regs |= getAliases(X86::R15); 1206 return; 1207 } 1208 Regs.set(X86::RAX); 1209 Regs.set(X86::RBX); 1210 Regs.set(X86::RBP); 1211 Regs.set(X86::RSI); 1212 Regs.set(X86::RDI); 1213 Regs.set(X86::RDX); 1214 Regs.set(X86::RCX); 1215 Regs.set(X86::R8); 1216 Regs.set(X86::R9); 1217 Regs.set(X86::R10); 1218 Regs.set(X86::R11); 1219 Regs.set(X86::R12); 1220 Regs.set(X86::R13); 1221 Regs.set(X86::R14); 1222 Regs.set(X86::R15); 1223 } 1224 1225 void getClassicGPRegs(BitVector &Regs) const override { 1226 Regs |= getAliases(X86::RAX); 1227 Regs |= getAliases(X86::RBX); 1228 Regs |= getAliases(X86::RBP); 1229 Regs |= getAliases(X86::RSI); 1230 Regs |= getAliases(X86::RDI); 1231 Regs |= getAliases(X86::RDX); 1232 Regs |= getAliases(X86::RCX); 1233 } 1234 1235 void getRepRegs(BitVector &Regs) const override { 1236 Regs |= getAliases(X86::RCX); 1237 } 1238 1239 MCPhysReg getAliasSized(MCPhysReg Reg, uint8_t Size) const override { 1240 switch (Reg) { 1241 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: case X86::AH: 1242 switch (Size) { 1243 case 8: return X86::RAX; case 4: return X86::EAX; 1244 case 2: return X86::AX; case 1: return X86::AL; 1245 default: llvm_unreachable("Unexpected size"); 1246 } 1247 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: case X86::BH: 1248 switch (Size) { 1249 case 8: return X86::RBX; case 4: return X86::EBX; 1250 case 2: return X86::BX; case 1: return X86::BL; 1251 default: llvm_unreachable("Unexpected size"); 1252 } 1253 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: case X86::DH: 1254 switch (Size) { 1255 case 8: return X86::RDX; case 4: return X86::EDX; 1256 case 2: return X86::DX; case 1: return X86::DL; 1257 default: llvm_unreachable("Unexpected size"); 1258 } 1259 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: 1260 switch (Size) { 1261 case 8: return X86::RDI; case 4: return X86::EDI; 1262 case 2: return X86::DI; case 1: return X86::DIL; 1263 default: llvm_unreachable("Unexpected size"); 1264 } 1265 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: 1266 switch (Size) { 1267 case 8: return X86::RSI; case 4: return X86::ESI; 1268 case 2: return X86::SI; case 1: return X86::SIL; 1269 default: llvm_unreachable("Unexpected size"); 1270 } 1271 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: case X86::CH: 1272 switch (Size) { 1273 case 8: return X86::RCX; case 4: return X86::ECX; 1274 case 2: return X86::CX; case 1: return X86::CL; 1275 default: llvm_unreachable("Unexpected size"); 1276 } 1277 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: 1278 switch (Size) { 1279 case 8: return X86::RSP; case 4: return X86::ESP; 1280 case 2: return X86::SP; case 1: return X86::SPL; 1281 default: llvm_unreachable("Unexpected size"); 1282 } 1283 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: 1284 switch (Size) { 1285 case 8: return X86::RBP; case 4: return X86::EBP; 1286 case 2: return X86::BP; case 1: return X86::BPL; 1287 default: llvm_unreachable("Unexpected size"); 1288 } 1289 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B: 1290 switch (Size) { 1291 case 8: return X86::R8; case 4: return X86::R8D; 1292 case 2: return X86::R8W; case 1: return X86::R8B; 1293 default: llvm_unreachable("Unexpected size"); 1294 } 1295 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B: 1296 switch (Size) { 1297 case 8: return X86::R9; case 4: return X86::R9D; 1298 case 2: return X86::R9W; case 1: return X86::R9B; 1299 default: llvm_unreachable("Unexpected size"); 1300 } 1301 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B: 1302 switch (Size) { 1303 case 8: return X86::R10; case 4: return X86::R10D; 1304 case 2: return X86::R10W; case 1: return X86::R10B; 1305 default: llvm_unreachable("Unexpected size"); 1306 } 1307 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B: 1308 switch (Size) { 1309 case 8: return X86::R11; case 4: return X86::R11D; 1310 case 2: return X86::R11W; case 1: return X86::R11B; 1311 default: llvm_unreachable("Unexpected size"); 1312 } 1313 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B: 1314 switch (Size) { 1315 case 8: return X86::R12; case 4: return X86::R12D; 1316 case 2: return X86::R12W; case 1: return X86::R12B; 1317 default: llvm_unreachable("Unexpected size"); 1318 } 1319 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B: 1320 switch (Size) { 1321 case 8: return X86::R13; case 4: return X86::R13D; 1322 case 2: return X86::R13W; case 1: return X86::R13B; 1323 default: llvm_unreachable("Unexpected size"); 1324 } 1325 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B: 1326 switch (Size) { 1327 case 8: return X86::R14; case 4: return X86::R14D; 1328 case 2: return X86::R14W; case 1: return X86::R14B; 1329 default: llvm_unreachable("Unexpected size"); 1330 } 1331 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B: 1332 switch (Size) { 1333 case 8: return X86::R15; case 4: return X86::R15D; 1334 case 2: return X86::R15W; case 1: return X86::R15B; 1335 default: llvm_unreachable("Unexpected size"); 1336 } 1337 default: 1338 dbgs() << Reg << " (get alias sized)\n"; 1339 llvm_unreachable("Unexpected reg number"); 1340 break; 1341 } 1342 } 1343 1344 bool isUpper8BitReg(MCPhysReg Reg) const override { 1345 switch (Reg) { 1346 case X86::AH: case X86::BH: case X86::CH: case X86::DH: 1347 return true; 1348 default: 1349 return false; 1350 } 1351 } 1352 1353 bool cannotUseREX(const MCInst &Inst) const override { 1354 switch(Inst.getOpcode()) { 1355 case X86::MOV8mr_NOREX: 1356 case X86::MOV8rm_NOREX: 1357 case X86::MOV8rr_NOREX: 1358 case X86::MOVSX32rm8_NOREX: 1359 case X86::MOVSX32rr8_NOREX: 1360 case X86::MOVZX32rm8_NOREX: 1361 case X86::MOVZX32rr8_NOREX: 1362 case X86::MOV8mr: 1363 case X86::MOV8rm: 1364 case X86::MOV8rr: 1365 case X86::MOVSX32rm8: 1366 case X86::MOVSX32rr8: 1367 case X86::MOVZX32rm8: 1368 case X86::MOVZX32rr8: 1369 case X86::TEST8ri: 1370 for (int I = 0, E = MCPlus::getNumPrimeOperands(Inst); I != E; ++I) { 1371 const MCOperand &Operand = Inst.getOperand(I); 1372 if (!Operand.isReg()) 1373 continue; 1374 if (isUpper8BitReg(Operand.getReg())) 1375 return true; 1376 } 1377 LLVM_FALLTHROUGH; 1378 default: 1379 return false; 1380 } 1381 } 1382 1383 bool isStackAccess(const MCInst &Inst, bool &IsLoad, bool &IsStore, 1384 bool &IsStoreFromReg, MCPhysReg &Reg, int32_t &SrcImm, 1385 uint16_t &StackPtrReg, int64_t &StackOffset, 1386 uint8_t &Size, bool &IsSimple, 1387 bool &IsIndexed) const override { 1388 // Detect simple push/pop cases first 1389 if (int Sz = getPushSize(Inst)) { 1390 IsLoad = false; 1391 IsStore = true; 1392 IsStoreFromReg = true; 1393 StackPtrReg = X86::RSP; 1394 StackOffset = -Sz; 1395 Size = Sz; 1396 IsSimple = true; 1397 if (Inst.getOperand(0).isImm()) { 1398 SrcImm = Inst.getOperand(0).getImm(); 1399 } else if (Inst.getOperand(0).isReg()) { 1400 Reg = Inst.getOperand(0).getReg(); 1401 } else { 1402 IsSimple = false; 1403 } 1404 return true; 1405 } 1406 if (int Sz = getPopSize(Inst)) { 1407 IsLoad = true; 1408 IsStore = false; 1409 if (Inst.getNumOperands() == 0 || !Inst.getOperand(0).isReg()) { 1410 IsSimple = false; 1411 } else { 1412 Reg = Inst.getOperand(0).getReg(); 1413 IsSimple = true; 1414 } 1415 StackPtrReg = X86::RSP; 1416 StackOffset = 0; 1417 Size = Sz; 1418 return true; 1419 } 1420 1421 struct InstInfo { 1422 // Size in bytes that Inst loads from memory. 1423 uint8_t DataSize; 1424 bool IsLoad; 1425 bool IsStore; 1426 bool StoreFromReg; 1427 bool Simple; 1428 }; 1429 1430 InstInfo I; 1431 int MemOpNo = getMemoryOperandNo(Inst); 1432 const MCInstrDesc &MCII = Info->get(Inst.getOpcode()); 1433 // If it is not dealing with a memory operand, we discard it 1434 if (MemOpNo == -1 || MCII.isCall()) 1435 return false; 1436 1437 switch (Inst.getOpcode()) { 1438 default: { 1439 uint8_t Sz = 0; 1440 bool IsLoad = MCII.mayLoad(); 1441 bool IsStore = MCII.mayStore(); 1442 // Is it LEA? (deals with memory but is not loading nor storing) 1443 if (!IsLoad && !IsStore) 1444 return false; 1445 1446 // Try to guess data size involved in the load/store by looking at the 1447 // register size. If there's no reg involved, return 0 as size, meaning 1448 // we don't know. 1449 for (unsigned I = 0, E = MCII.getNumOperands(); I != E; ++I) { 1450 if (MCII.OpInfo[I].OperandType != MCOI::OPERAND_REGISTER) 1451 continue; 1452 if (static_cast<int>(I) >= MemOpNo && I < X86::AddrNumOperands) 1453 continue; 1454 Sz = RegInfo->getRegClass(MCII.OpInfo[I].RegClass).getSizeInBits() / 8; 1455 break; 1456 } 1457 I = {Sz, IsLoad, IsStore, false, false}; 1458 break; 1459 } 1460 case X86::MOV16rm: I = {2, true, false, false, true}; break; 1461 case X86::MOV32rm: I = {4, true, false, false, true}; break; 1462 case X86::MOV64rm: I = {8, true, false, false, true}; break; 1463 case X86::MOV16mr: I = {2, false, true, true, true}; break; 1464 case X86::MOV32mr: I = {4, false, true, true, true}; break; 1465 case X86::MOV64mr: I = {8, false, true, true, true}; break; 1466 case X86::MOV16mi: I = {2, false, true, false, true}; break; 1467 case X86::MOV32mi: I = {4, false, true, false, true}; break; 1468 } // end switch (Inst.getOpcode()) 1469 1470 unsigned BaseRegNum; 1471 int64_t ScaleValue; 1472 unsigned IndexRegNum; 1473 int64_t DispValue; 1474 unsigned SegRegNum; 1475 const MCExpr *DispExpr; 1476 if (!evaluateX86MemoryOperand(Inst, &BaseRegNum, &ScaleValue, &IndexRegNum, 1477 &DispValue, &SegRegNum, &DispExpr)) { 1478 LLVM_DEBUG(dbgs() << "Evaluate failed on "); 1479 LLVM_DEBUG(Inst.dump()); 1480 return false; 1481 } 1482 1483 // Make sure it's a stack access 1484 if (BaseRegNum != X86::RBP && BaseRegNum != X86::RSP) { 1485 return false; 1486 } 1487 1488 IsLoad = I.IsLoad; 1489 IsStore = I.IsStore; 1490 IsStoreFromReg = I.StoreFromReg; 1491 Size = I.DataSize; 1492 IsSimple = I.Simple; 1493 StackPtrReg = BaseRegNum; 1494 StackOffset = DispValue; 1495 IsIndexed = IndexRegNum != X86::NoRegister || SegRegNum != X86::NoRegister; 1496 1497 if (!I.Simple) 1498 return true; 1499 1500 // Retrieve related register in simple MOV from/to stack operations. 1501 unsigned MemOpOffset = static_cast<unsigned>(MemOpNo); 1502 if (I.IsLoad) { 1503 MCOperand RegOpnd = Inst.getOperand(0); 1504 assert(RegOpnd.isReg() && "unexpected destination operand"); 1505 Reg = RegOpnd.getReg(); 1506 } else if (I.IsStore) { 1507 MCOperand SrcOpnd = 1508 Inst.getOperand(MemOpOffset + X86::AddrSegmentReg + 1); 1509 if (I.StoreFromReg) { 1510 assert(SrcOpnd.isReg() && "unexpected source operand"); 1511 Reg = SrcOpnd.getReg(); 1512 } else { 1513 assert(SrcOpnd.isImm() && "unexpected source operand"); 1514 SrcImm = SrcOpnd.getImm(); 1515 } 1516 } 1517 1518 return true; 1519 } 1520 1521 void changeToPushOrPop(MCInst &Inst) const override { 1522 assert(!isPush(Inst) && !isPop(Inst)); 1523 1524 struct InstInfo { 1525 // Size in bytes that Inst loads from memory. 1526 uint8_t DataSize; 1527 bool IsLoad; 1528 bool StoreFromReg; 1529 }; 1530 1531 InstInfo I; 1532 switch (Inst.getOpcode()) { 1533 default: { 1534 llvm_unreachable("Unhandled opcode"); 1535 return; 1536 } 1537 case X86::MOV16rm: I = {2, true, false}; break; 1538 case X86::MOV32rm: I = {4, true, false}; break; 1539 case X86::MOV64rm: I = {8, true, false}; break; 1540 case X86::MOV16mr: I = {2, false, true}; break; 1541 case X86::MOV32mr: I = {4, false, true}; break; 1542 case X86::MOV64mr: I = {8, false, true}; break; 1543 case X86::MOV16mi: I = {2, false, false}; break; 1544 case X86::MOV32mi: I = {4, false, false}; break; 1545 } // end switch (Inst.getOpcode()) 1546 1547 unsigned BaseRegNum; 1548 int64_t ScaleValue; 1549 unsigned IndexRegNum; 1550 int64_t DispValue; 1551 unsigned SegRegNum; 1552 const MCExpr *DispExpr; 1553 if (!evaluateX86MemoryOperand(Inst, &BaseRegNum, &ScaleValue, &IndexRegNum, 1554 &DispValue, &SegRegNum, &DispExpr)) { 1555 llvm_unreachable("Evaluate failed"); 1556 return; 1557 } 1558 // Make sure it's a stack access 1559 if (BaseRegNum != X86::RBP && BaseRegNum != X86::RSP) { 1560 llvm_unreachable("Not a stack access"); 1561 return; 1562 } 1563 1564 unsigned MemOpOffset = getMemoryOperandNo(Inst); 1565 unsigned NewOpcode = 0; 1566 if (I.IsLoad) { 1567 switch (I.DataSize) { 1568 case 2: NewOpcode = X86::POP16r; break; 1569 case 4: NewOpcode = X86::POP32r; break; 1570 case 8: NewOpcode = X86::POP64r; break; 1571 default: 1572 assert(false); 1573 } 1574 unsigned RegOpndNum = Inst.getOperand(0).getReg(); 1575 Inst.clear(); 1576 Inst.setOpcode(NewOpcode); 1577 Inst.addOperand(MCOperand::createReg(RegOpndNum)); 1578 } else { 1579 MCOperand SrcOpnd = 1580 Inst.getOperand(MemOpOffset + X86::AddrSegmentReg + 1); 1581 if (I.StoreFromReg) { 1582 switch (I.DataSize) { 1583 case 2: NewOpcode = X86::PUSH16r; break; 1584 case 4: NewOpcode = X86::PUSH32r; break; 1585 case 8: NewOpcode = X86::PUSH64r; break; 1586 default: 1587 assert(false); 1588 } 1589 assert(SrcOpnd.isReg() && "unexpected source operand"); 1590 unsigned RegOpndNum = SrcOpnd.getReg(); 1591 Inst.clear(); 1592 Inst.setOpcode(NewOpcode); 1593 Inst.addOperand(MCOperand::createReg(RegOpndNum)); 1594 } else { 1595 switch (I.DataSize) { 1596 case 2: NewOpcode = X86::PUSH16i8; break; 1597 case 4: NewOpcode = X86::PUSH32i8; break; 1598 case 8: NewOpcode = X86::PUSH64i32; break; 1599 default: 1600 assert(false); 1601 } 1602 assert(SrcOpnd.isImm() && "unexpected source operand"); 1603 int64_t SrcImm = SrcOpnd.getImm(); 1604 Inst.clear(); 1605 Inst.setOpcode(NewOpcode); 1606 Inst.addOperand(MCOperand::createImm(SrcImm)); 1607 } 1608 } 1609 } 1610 1611 bool isStackAdjustment(const MCInst &Inst) const override { 1612 switch (Inst.getOpcode()) { 1613 default: 1614 return false; 1615 case X86::SUB64ri32: 1616 case X86::SUB64ri8: 1617 case X86::ADD64ri32: 1618 case X86::ADD64ri8: 1619 case X86::LEA64r: 1620 break; 1621 } 1622 1623 const MCInstrDesc &MCII = Info->get(Inst.getOpcode()); 1624 for (int I = 0, E = MCII.getNumDefs(); I != E; ++I) { 1625 const MCOperand &Operand = Inst.getOperand(I); 1626 if (Operand.isReg() && Operand.getReg() == X86::RSP) { 1627 return true; 1628 } 1629 } 1630 return false; 1631 } 1632 1633 bool evaluateSimple(const MCInst &Inst, int64_t &Output, 1634 std::pair<MCPhysReg, int64_t> Input1, 1635 std::pair<MCPhysReg, int64_t> Input2) const override { 1636 1637 auto getOperandVal = [&](MCPhysReg Reg) -> ErrorOr<int64_t> { 1638 if (Reg == Input1.first) 1639 return Input1.second; 1640 if (Reg == Input2.first) 1641 return Input2.second; 1642 return make_error_code(errc::result_out_of_range); 1643 }; 1644 1645 switch (Inst.getOpcode()) { 1646 default: 1647 return false; 1648 1649 case X86::AND64ri32: 1650 case X86::AND64ri8: 1651 if (!Inst.getOperand(2).isImm()) 1652 return false; 1653 if (ErrorOr<int64_t> InputVal = 1654 getOperandVal(Inst.getOperand(1).getReg())) { 1655 Output = *InputVal & Inst.getOperand(2).getImm(); 1656 } else { 1657 return false; 1658 } 1659 break; 1660 case X86::SUB64ri32: 1661 case X86::SUB64ri8: 1662 if (!Inst.getOperand(2).isImm()) 1663 return false; 1664 if (ErrorOr<int64_t> InputVal = 1665 getOperandVal(Inst.getOperand(1).getReg())) { 1666 Output = *InputVal - Inst.getOperand(2).getImm(); 1667 } else { 1668 return false; 1669 } 1670 break; 1671 case X86::ADD64ri32: 1672 case X86::ADD64ri8: 1673 if (!Inst.getOperand(2).isImm()) 1674 return false; 1675 if (ErrorOr<int64_t> InputVal = 1676 getOperandVal(Inst.getOperand(1).getReg())) { 1677 Output = *InputVal + Inst.getOperand(2).getImm(); 1678 } else { 1679 return false; 1680 } 1681 break; 1682 case X86::ADD64i32: 1683 if (!Inst.getOperand(0).isImm()) 1684 return false; 1685 if (ErrorOr<int64_t> InputVal = getOperandVal(X86::RAX)) { 1686 Output = *InputVal + Inst.getOperand(0).getImm(); 1687 } else { 1688 return false; 1689 } 1690 break; 1691 1692 case X86::LEA64r: { 1693 unsigned BaseRegNum; 1694 int64_t ScaleValue; 1695 unsigned IndexRegNum; 1696 int64_t DispValue; 1697 unsigned SegRegNum; 1698 const MCExpr *DispExpr = nullptr; 1699 if (!evaluateX86MemoryOperand(Inst, &BaseRegNum, &ScaleValue, 1700 &IndexRegNum, &DispValue, &SegRegNum, 1701 &DispExpr)) { 1702 return false; 1703 } 1704 1705 if (BaseRegNum == X86::NoRegister || IndexRegNum != X86::NoRegister || 1706 SegRegNum != X86::NoRegister || DispExpr) { 1707 return false; 1708 } 1709 1710 if (ErrorOr<int64_t> InputVal = getOperandVal(BaseRegNum)) { 1711 Output = *InputVal + DispValue; 1712 } else { 1713 return false; 1714 } 1715 1716 break; 1717 } 1718 } 1719 return true; 1720 } 1721 1722 bool isRegToRegMove(const MCInst &Inst, MCPhysReg &From, 1723 MCPhysReg &To) const override { 1724 switch (Inst.getOpcode()) { 1725 default: 1726 return false; 1727 case X86::LEAVE: 1728 case X86::LEAVE64: 1729 To = getStackPointer(); 1730 From = getFramePointer(); 1731 return true; 1732 case X86::MOV64rr: 1733 To = Inst.getOperand(0).getReg(); 1734 From = Inst.getOperand(1).getReg(); 1735 return true; 1736 } 1737 } 1738 1739 MCPhysReg getStackPointer() const override { return X86::RSP; } 1740 MCPhysReg getFramePointer() const override { return X86::RBP; } 1741 MCPhysReg getFlagsReg() const override { return X86::EFLAGS; } 1742 1743 bool escapesVariable(const MCInst &Inst, bool HasFramePointer) const override { 1744 int MemOpNo = getMemoryOperandNo(Inst); 1745 const MCInstrDesc &MCII = Info->get(Inst.getOpcode()); 1746 const unsigned NumDefs = MCII.getNumDefs(); 1747 static BitVector SPBPAliases(BitVector(getAliases(X86::RSP)) |= 1748 getAliases(X86::RBP)); 1749 static BitVector SPAliases(getAliases(X86::RSP)); 1750 1751 // FIXME: PUSH can be technically a leak, but let's ignore this for now 1752 // because a lot of harmless prologue code will spill SP to the stack. 1753 // Unless push is clearly pushing an object address to the stack as 1754 // demonstrated by having a MemOp. 1755 bool IsPush = isPush(Inst); 1756 if (IsPush && MemOpNo == -1) 1757 return false; 1758 1759 // We use this to detect LEA (has memop but does not access mem) 1760 bool AccessMem = MCII.mayLoad() || MCII.mayStore(); 1761 bool DoesLeak = false; 1762 for (int I = 0, E = MCPlus::getNumPrimeOperands(Inst); I != E; ++I) { 1763 // Ignore if SP/BP is used to dereference memory -- that's fine 1764 if (MemOpNo != -1 && !IsPush && AccessMem && I >= MemOpNo && 1765 I <= MemOpNo + 5) 1766 continue; 1767 // Ignore if someone is writing to SP/BP 1768 if (I < static_cast<int>(NumDefs)) 1769 continue; 1770 1771 const MCOperand &Operand = Inst.getOperand(I); 1772 if (HasFramePointer && Operand.isReg() && SPBPAliases[Operand.getReg()]) { 1773 DoesLeak = true; 1774 break; 1775 } 1776 if (!HasFramePointer && Operand.isReg() && SPAliases[Operand.getReg()]) { 1777 DoesLeak = true; 1778 break; 1779 } 1780 } 1781 1782 // If potential leak, check if it is not just writing to itself/sp/bp 1783 if (DoesLeak) { 1784 for (int I = 0, E = NumDefs; I != E; ++I) { 1785 const MCOperand &Operand = Inst.getOperand(I); 1786 if (HasFramePointer && Operand.isReg() && 1787 SPBPAliases[Operand.getReg()]) { 1788 DoesLeak = false; 1789 break; 1790 } 1791 if (!HasFramePointer && Operand.isReg() && 1792 SPAliases[Operand.getReg()]) { 1793 DoesLeak = false; 1794 break; 1795 } 1796 } 1797 } 1798 return DoesLeak; 1799 } 1800 1801 bool addToImm(MCInst &Inst, int64_t &Amt, MCContext *Ctx) const override { 1802 unsigned ImmOpNo = -1U; 1803 int MemOpNo = getMemoryOperandNo(Inst); 1804 if (MemOpNo != -1) { 1805 ImmOpNo = MemOpNo + X86::AddrDisp; 1806 } else { 1807 for (unsigned Index = 0; 1808 Index < MCPlus::getNumPrimeOperands(Inst); ++Index) { 1809 if (Inst.getOperand(Index).isImm()) { 1810 ImmOpNo = Index; 1811 } 1812 } 1813 } 1814 if (ImmOpNo == -1U) 1815 return false; 1816 1817 MCOperand &Operand = Inst.getOperand(ImmOpNo); 1818 Amt += Operand.getImm(); 1819 Operand.setImm(Amt); 1820 // Check for the need for relaxation 1821 if (int64_t(Amt) == int64_t(int8_t(Amt))) 1822 return true; 1823 1824 // Relax instruction 1825 switch (Inst.getOpcode()) { 1826 case X86::SUB64ri8: 1827 Inst.setOpcode(X86::SUB64ri32); 1828 break; 1829 case X86::ADD64ri8: 1830 Inst.setOpcode(X86::ADD64ri32); 1831 break; 1832 default: 1833 // No need for relaxation 1834 break; 1835 } 1836 return true; 1837 } 1838 1839 /// TODO: this implementation currently works for the most common opcodes that 1840 /// load from memory. It can be extended to work with memory store opcodes as 1841 /// well as more memory load opcodes. 1842 bool replaceMemOperandWithImm(MCInst &Inst, StringRef ConstantData, 1843 uint64_t Offset) const override { 1844 enum CheckSignExt : uint8_t { 1845 NOCHECK = 0, 1846 CHECK8, 1847 CHECK32, 1848 }; 1849 1850 using CheckList = std::vector<std::pair<CheckSignExt, unsigned>>; 1851 struct InstInfo { 1852 // Size in bytes that Inst loads from memory. 1853 uint8_t DataSize; 1854 1855 // True when the target operand has to be duplicated because the opcode 1856 // expects a LHS operand. 1857 bool HasLHS; 1858 1859 // List of checks and corresponding opcodes to be used. We try to use the 1860 // smallest possible immediate value when various sizes are available, 1861 // hence we may need to check whether a larger constant fits in a smaller 1862 // immediate. 1863 CheckList Checks; 1864 }; 1865 1866 InstInfo I; 1867 1868 switch (Inst.getOpcode()) { 1869 default: { 1870 switch (getPopSize(Inst)) { 1871 case 2: I = {2, false, {{NOCHECK, X86::MOV16ri}}}; break; 1872 case 4: I = {4, false, {{NOCHECK, X86::MOV32ri}}}; break; 1873 case 8: I = {8, false, {{CHECK32, X86::MOV64ri32}, 1874 {NOCHECK, X86::MOV64rm}}}; break; 1875 default: return false; 1876 } 1877 break; 1878 } 1879 1880 // MOV 1881 case X86::MOV8rm: I = {1, false, {{NOCHECK, X86::MOV8ri}}}; break; 1882 case X86::MOV16rm: I = {2, false, {{NOCHECK, X86::MOV16ri}}}; break; 1883 case X86::MOV32rm: I = {4, false, {{NOCHECK, X86::MOV32ri}}}; break; 1884 case X86::MOV64rm: I = {8, false, {{CHECK32, X86::MOV64ri32}, 1885 {NOCHECK, X86::MOV64rm}}}; break; 1886 1887 // MOVZX 1888 case X86::MOVZX16rm8: I = {1, false, {{NOCHECK, X86::MOV16ri}}}; break; 1889 case X86::MOVZX32rm8: I = {1, false, {{NOCHECK, X86::MOV32ri}}}; break; 1890 case X86::MOVZX32rm16: I = {2, false, {{NOCHECK, X86::MOV32ri}}}; break; 1891 1892 // CMP 1893 case X86::CMP8rm: I = {1, false, {{NOCHECK, X86::CMP8ri}}}; break; 1894 case X86::CMP16rm: I = {2, false, {{CHECK8, X86::CMP16ri8}, 1895 {NOCHECK, X86::CMP16ri}}}; break; 1896 case X86::CMP32rm: I = {4, false, {{CHECK8, X86::CMP32ri8}, 1897 {NOCHECK, X86::CMP32ri}}}; break; 1898 case X86::CMP64rm: I = {8, false, {{CHECK8, X86::CMP64ri8}, 1899 {CHECK32, X86::CMP64ri32}, 1900 {NOCHECK, X86::CMP64rm}}}; break; 1901 1902 // TEST 1903 case X86::TEST8mr: I = {1, false, {{NOCHECK, X86::TEST8ri}}}; break; 1904 case X86::TEST16mr: I = {2, false, {{NOCHECK, X86::TEST16ri}}}; break; 1905 case X86::TEST32mr: I = {4, false, {{NOCHECK, X86::TEST32ri}}}; break; 1906 case X86::TEST64mr: I = {8, false, {{CHECK32, X86::TEST64ri32}, 1907 {NOCHECK, X86::TEST64mr}}}; break; 1908 1909 // ADD 1910 case X86::ADD8rm: I = {1, true, {{NOCHECK, X86::ADD8ri}}}; break; 1911 case X86::ADD16rm: I = {2, true, {{CHECK8, X86::ADD16ri8}, 1912 {NOCHECK, X86::ADD16ri}}}; break; 1913 case X86::ADD32rm: I = {4, true, {{CHECK8, X86::ADD32ri8}, 1914 {NOCHECK, X86::ADD32ri}}}; break; 1915 case X86::ADD64rm: I = {8, true, {{CHECK8, X86::ADD64ri8}, 1916 {CHECK32, X86::ADD64ri32}, 1917 {NOCHECK, X86::ADD64rm}}}; break; 1918 1919 // SUB 1920 case X86::SUB8rm: I = {1, true, {{NOCHECK, X86::SUB8ri}}}; break; 1921 case X86::SUB16rm: I = {2, true, {{CHECK8, X86::SUB16ri8}, 1922 {NOCHECK, X86::SUB16ri}}}; break; 1923 case X86::SUB32rm: I = {4, true, {{CHECK8, X86::SUB32ri8}, 1924 {NOCHECK, X86::SUB32ri}}}; break; 1925 case X86::SUB64rm: I = {8, true, {{CHECK8, X86::SUB64ri8}, 1926 {CHECK32, X86::SUB64ri32}, 1927 {NOCHECK, X86::SUB64rm}}}; break; 1928 1929 // AND 1930 case X86::AND8rm: I = {1, true, {{NOCHECK, X86::AND8ri}}}; break; 1931 case X86::AND16rm: I = {2, true, {{CHECK8, X86::AND16ri8}, 1932 {NOCHECK, X86::AND16ri}}}; break; 1933 case X86::AND32rm: I = {4, true, {{CHECK8, X86::AND32ri8}, 1934 {NOCHECK, X86::AND32ri}}}; break; 1935 case X86::AND64rm: I = {8, true, {{CHECK8, X86::AND64ri8}, 1936 {CHECK32, X86::AND64ri32}, 1937 {NOCHECK, X86::AND64rm}}}; break; 1938 1939 // OR 1940 case X86::OR8rm: I = {1, true, {{NOCHECK, X86::OR8ri}}}; break; 1941 case X86::OR16rm: I = {2, true, {{CHECK8, X86::OR16ri8}, 1942 {NOCHECK, X86::OR16ri}}}; break; 1943 case X86::OR32rm: I = {4, true, {{CHECK8, X86::OR32ri8}, 1944 {NOCHECK, X86::OR32ri}}}; break; 1945 case X86::OR64rm: I = {8, true, {{CHECK8, X86::OR64ri8}, 1946 {CHECK32, X86::OR64ri32}, 1947 {NOCHECK, X86::OR64rm}}}; break; 1948 1949 // XOR 1950 case X86::XOR8rm: I = {1, true, {{NOCHECK, X86::XOR8ri}}}; break; 1951 case X86::XOR16rm: I = {2, true, {{CHECK8, X86::XOR16ri8}, 1952 {NOCHECK, X86::XOR16ri}}}; break; 1953 case X86::XOR32rm: I = {4, true, {{CHECK8, X86::XOR32ri8}, 1954 {NOCHECK, X86::XOR32ri}}}; break; 1955 case X86::XOR64rm: I = {8, true, {{CHECK8, X86::XOR64ri8}, 1956 {CHECK32, X86::XOR64ri32}, 1957 {NOCHECK, X86::XOR64rm}}}; break; 1958 } 1959 1960 // Compute the immediate value. 1961 assert(Offset + I.DataSize <= ConstantData.size() && 1962 "invalid offset for given constant data"); 1963 int64_t ImmVal = 1964 DataExtractor(ConstantData, true, 8).getSigned(&Offset, I.DataSize); 1965 1966 // Compute the new opcode. 1967 unsigned NewOpcode = 0; 1968 for (const std::pair<CheckSignExt, unsigned> &Check : I.Checks) { 1969 NewOpcode = Check.second; 1970 if (Check.first == NOCHECK) 1971 break; 1972 if (Check.first == CHECK8 && 1973 ImmVal >= std::numeric_limits<int8_t>::min() && 1974 ImmVal <= std::numeric_limits<int8_t>::max()) 1975 break; 1976 if (Check.first == CHECK32 && 1977 ImmVal >= std::numeric_limits<int32_t>::min() && 1978 ImmVal <= std::numeric_limits<int32_t>::max()) 1979 break; 1980 } 1981 if (NewOpcode == Inst.getOpcode()) 1982 return false; 1983 1984 // Modify the instruction. 1985 MCOperand ImmOp = MCOperand::createImm(ImmVal); 1986 uint32_t TargetOpNum = 0; 1987 // Test instruction does not follow the regular pattern of putting the 1988 // memory reference of a load (5 MCOperands) last in the list of operands. 1989 // Since it is not modifying the register operand, it is not treated as 1990 // a destination operand and it is not the first operand as it is in the 1991 // other instructions we treat here. 1992 if (NewOpcode == X86::TEST8ri || 1993 NewOpcode == X86::TEST16ri || 1994 NewOpcode == X86::TEST32ri || 1995 NewOpcode == X86::TEST64ri32) { 1996 TargetOpNum = getMemoryOperandNo(Inst) + X86::AddrNumOperands; 1997 } 1998 MCOperand TargetOp = Inst.getOperand(TargetOpNum); 1999 Inst.clear(); 2000 Inst.setOpcode(NewOpcode); 2001 Inst.addOperand(TargetOp); 2002 if (I.HasLHS) 2003 Inst.addOperand(TargetOp); 2004 Inst.addOperand(ImmOp); 2005 2006 return true; 2007 } 2008 2009 /// TODO: this implementation currently works for the most common opcodes that 2010 /// load from memory. It can be extended to work with memory store opcodes as 2011 /// well as more memory load opcodes. 2012 bool replaceMemOperandWithReg(MCInst &Inst, MCPhysReg RegNum) const override { 2013 unsigned NewOpcode; 2014 2015 switch (Inst.getOpcode()) { 2016 default: { 2017 switch (getPopSize(Inst)) { 2018 case 2: NewOpcode = X86::MOV16rr; break; 2019 case 4: NewOpcode = X86::MOV32rr; break; 2020 case 8: NewOpcode = X86::MOV64rr; break; 2021 default: return false; 2022 } 2023 break; 2024 } 2025 2026 // MOV 2027 case X86::MOV8rm: NewOpcode = X86::MOV8rr; break; 2028 case X86::MOV16rm: NewOpcode = X86::MOV16rr; break; 2029 case X86::MOV32rm: NewOpcode = X86::MOV32rr; break; 2030 case X86::MOV64rm: NewOpcode = X86::MOV64rr; break; 2031 } 2032 2033 // Modify the instruction. 2034 MCOperand RegOp = MCOperand::createReg(RegNum); 2035 MCOperand TargetOp = Inst.getOperand(0); 2036 Inst.clear(); 2037 Inst.setOpcode(NewOpcode); 2038 Inst.addOperand(TargetOp); 2039 Inst.addOperand(RegOp); 2040 2041 return true; 2042 } 2043 2044 bool isRedundantMove(const MCInst &Inst) const override { 2045 switch (Inst.getOpcode()) { 2046 default: 2047 return false; 2048 2049 // MOV 2050 case X86::MOV8rr: 2051 case X86::MOV16rr: 2052 case X86::MOV32rr: 2053 case X86::MOV64rr: 2054 break; 2055 } 2056 2057 assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg()); 2058 return Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg(); 2059 } 2060 2061 bool requiresAlignedAddress(const MCInst &Inst) const override { 2062 const MCInstrDesc &Desc = Info->get(Inst.getOpcode()); 2063 for (unsigned int I = 0; I < Desc.getNumOperands(); ++I) { 2064 const MCOperandInfo &Op = Desc.OpInfo[I]; 2065 if (Op.OperandType != MCOI::OPERAND_REGISTER) 2066 continue; 2067 if (Op.RegClass == X86::VR128RegClassID) 2068 return true; 2069 } 2070 return false; 2071 } 2072 2073 bool convertJmpToTailCall(MCInst &Inst) override { 2074 if (isTailCall(Inst)) 2075 return false; 2076 2077 int NewOpcode; 2078 switch (Inst.getOpcode()) { 2079 default: 2080 return false; 2081 case X86::JMP_1: 2082 case X86::JMP_2: 2083 case X86::JMP_4: 2084 NewOpcode = X86::JMP_4; 2085 break; 2086 case X86::JMP16m: 2087 case X86::JMP32m: 2088 case X86::JMP64m: 2089 NewOpcode = X86::JMP32m; 2090 break; 2091 case X86::JMP16r: 2092 case X86::JMP32r: 2093 case X86::JMP64r: 2094 NewOpcode = X86::JMP32r; 2095 break; 2096 } 2097 2098 Inst.setOpcode(NewOpcode); 2099 setTailCall(Inst); 2100 return true; 2101 } 2102 2103 bool convertTailCallToJmp(MCInst &Inst) override { 2104 int NewOpcode; 2105 switch (Inst.getOpcode()) { 2106 default: 2107 return false; 2108 case X86::JMP_4: 2109 NewOpcode = X86::JMP_1; 2110 break; 2111 case X86::JMP32m: 2112 NewOpcode = X86::JMP64m; 2113 break; 2114 case X86::JMP32r: 2115 NewOpcode = X86::JMP64r; 2116 break; 2117 } 2118 2119 Inst.setOpcode(NewOpcode); 2120 removeAnnotation(Inst, MCPlus::MCAnnotation::kTailCall); 2121 removeAnnotation(Inst, "Offset"); 2122 return true; 2123 } 2124 2125 bool convertTailCallToCall(MCInst &Inst) override { 2126 int NewOpcode; 2127 switch (Inst.getOpcode()) { 2128 default: 2129 return false; 2130 case X86::JMP_4: 2131 NewOpcode = X86::CALL64pcrel32; 2132 break; 2133 case X86::JMP32m: 2134 NewOpcode = X86::CALL64m; 2135 break; 2136 case X86::JMP32r: 2137 NewOpcode = X86::CALL64r; 2138 break; 2139 } 2140 2141 Inst.setOpcode(NewOpcode); 2142 removeAnnotation(Inst, MCPlus::MCAnnotation::kTailCall); 2143 return true; 2144 } 2145 2146 bool convertCallToIndirectCall(MCInst &Inst, 2147 const MCSymbol *TargetLocation, 2148 MCContext *Ctx) override { 2149 bool IsTailCall = isTailCall(Inst); 2150 assert((Inst.getOpcode() == X86::CALL64pcrel32 || 2151 (Inst.getOpcode() == X86::JMP_4 && IsTailCall)) && 2152 "64-bit direct (tail) call instruction expected"); 2153 const auto NewOpcode = (Inst.getOpcode() == X86::CALL64pcrel32) 2154 ? X86::CALL64m 2155 : X86::JMP32m; 2156 Inst.setOpcode(NewOpcode); 2157 2158 // Replace the first operand and preserve auxiliary operands of 2159 // the instruction. 2160 Inst.erase(Inst.begin()); 2161 Inst.insert(Inst.begin(), 2162 MCOperand::createReg(X86::NoRegister)); // AddrSegmentReg 2163 Inst.insert(Inst.begin(), 2164 MCOperand::createExpr( // Displacement 2165 MCSymbolRefExpr::create(TargetLocation, 2166 MCSymbolRefExpr::VK_None, 2167 *Ctx))); 2168 Inst.insert(Inst.begin(), 2169 MCOperand::createReg(X86::NoRegister)); // IndexReg 2170 Inst.insert(Inst.begin(), 2171 MCOperand::createImm(1)); // ScaleAmt 2172 Inst.insert(Inst.begin(), 2173 MCOperand::createReg(X86::RIP)); // BaseReg 2174 2175 return true; 2176 } 2177 2178 void convertIndirectCallToLoad(MCInst &Inst, MCPhysReg Reg) override { 2179 bool IsTailCall = isTailCall(Inst); 2180 if (IsTailCall) 2181 removeAnnotation(Inst, MCPlus::MCAnnotation::kTailCall); 2182 if (Inst.getOpcode() == X86::CALL64m || 2183 (Inst.getOpcode() == X86::JMP32m && IsTailCall)) { 2184 Inst.setOpcode(X86::MOV64rm); 2185 Inst.insert(Inst.begin(), MCOperand::createReg(Reg)); 2186 return; 2187 } 2188 if (Inst.getOpcode() == X86::CALL64r || 2189 (Inst.getOpcode() == X86::JMP32r && IsTailCall)) { 2190 Inst.setOpcode(X86::MOV64rr); 2191 Inst.insert(Inst.begin(), MCOperand::createReg(Reg)); 2192 return; 2193 } 2194 LLVM_DEBUG(Inst.dump()); 2195 llvm_unreachable("not implemented"); 2196 } 2197 2198 bool shortenInstruction(MCInst &Inst) const override { 2199 unsigned OldOpcode = Inst.getOpcode(); 2200 unsigned NewOpcode = OldOpcode; 2201 2202 // Check and remove EIZ/RIZ. These cases represent ambiguous cases where SIB 2203 // byte is present, but no index is used and modrm alone shoud have been 2204 // enough. Converting to NoRegister effectively removes the SIB byte. 2205 int MemOpNo = getMemoryOperandNo(Inst); 2206 if (MemOpNo >= 0) { 2207 MCOperand &IndexOp = 2208 Inst.getOperand(static_cast<unsigned>(MemOpNo) + X86::AddrIndexReg); 2209 if (IndexOp.getReg() == X86::EIZ || 2210 IndexOp.getReg() == X86::RIZ) { 2211 IndexOp = MCOperand::createReg(X86::NoRegister); 2212 } 2213 } 2214 2215 if (isBranch(Inst)) { 2216 NewOpcode = getShortBranchOpcode(OldOpcode); 2217 } else if (OldOpcode == X86::MOV64ri) { 2218 if (Inst.getOperand(MCPlus::getNumPrimeOperands(Inst) - 1).isImm()) { 2219 const int64_t Imm = 2220 Inst.getOperand(MCPlus::getNumPrimeOperands(Inst) - 1).getImm(); 2221 if (int64_t(Imm) == int64_t(int32_t(Imm))) { 2222 NewOpcode = X86::MOV64ri32; 2223 } 2224 } 2225 } else { 2226 // If it's arithmetic instruction check if signed operand fits in 1 byte. 2227 const unsigned ShortOpcode = getShortArithOpcode(OldOpcode); 2228 if (ShortOpcode != OldOpcode && 2229 Inst.getOperand(MCPlus::getNumPrimeOperands(Inst) - 1).isImm()) { 2230 int64_t Imm = 2231 Inst.getOperand(MCPlus::getNumPrimeOperands(Inst) - 1).getImm(); 2232 if (int64_t(Imm) == int64_t(int8_t(Imm))) { 2233 NewOpcode = ShortOpcode; 2234 } 2235 } 2236 } 2237 2238 if (NewOpcode == OldOpcode) 2239 return false; 2240 2241 Inst.setOpcode(NewOpcode); 2242 return true; 2243 } 2244 2245 bool lowerTailCall(MCInst &Inst) override { 2246 if (Inst.getOpcode() == X86::JMP_4 && isTailCall(Inst)) { 2247 Inst.setOpcode(X86::JMP_1); 2248 removeAnnotation(Inst, MCPlus::MCAnnotation::kTailCall); 2249 return true; 2250 } 2251 return false; 2252 } 2253 2254 const MCSymbol *getTargetSymbol(const MCInst &Inst, 2255 unsigned OpNum = 0) const override { 2256 if (OpNum >= MCPlus::getNumPrimeOperands(Inst)) 2257 return nullptr; 2258 2259 const MCOperand &Op = Inst.getOperand(OpNum); 2260 if (!Op.isExpr()) 2261 return nullptr; 2262 2263 auto *SymExpr = dyn_cast<MCSymbolRefExpr>(Op.getExpr()); 2264 if (!SymExpr || SymExpr->getKind() != MCSymbolRefExpr::VK_None) 2265 return nullptr; 2266 2267 return &SymExpr->getSymbol(); 2268 } 2269 2270 // This is the same as the base class, but since we are overriding one of 2271 // getTargetSymbol's signatures above, we need to override all of them. 2272 const MCSymbol *getTargetSymbol(const MCExpr *Expr) const override { 2273 return &cast<const MCSymbolRefExpr>(Expr)->getSymbol(); 2274 } 2275 2276 bool analyzeBranch(InstructionIterator Begin, 2277 InstructionIterator End, 2278 const MCSymbol *&TBB, 2279 const MCSymbol *&FBB, 2280 MCInst *&CondBranch, 2281 MCInst *&UncondBranch) const override { 2282 auto I = End; 2283 2284 // Bottom-up analysis 2285 while (I != Begin) { 2286 --I; 2287 2288 // Ignore nops and CFIs 2289 if (isPseudo(*I)) 2290 continue; 2291 2292 // Stop when we find the first non-terminator 2293 if (!isTerminator(*I)) 2294 break; 2295 2296 if (!isBranch(*I)) 2297 break; 2298 2299 // Handle unconditional branches. 2300 if ((I->getOpcode() == X86::JMP_1 || 2301 I->getOpcode() == X86::JMP_2 || 2302 I->getOpcode() == X86::JMP_4) && 2303 !isTailCall(*I)) { 2304 // If any code was seen after this unconditional branch, we've seen 2305 // unreachable code. Ignore them. 2306 CondBranch = nullptr; 2307 UncondBranch = &*I; 2308 const MCSymbol *Sym = getTargetSymbol(*I); 2309 assert(Sym != nullptr && 2310 "Couldn't extract BB symbol from jump operand"); 2311 TBB = Sym; 2312 continue; 2313 } 2314 2315 // Handle conditional branches and ignore indirect branches 2316 if (!isUnsupportedBranch(I->getOpcode()) && 2317 getCondCode(*I) == X86::COND_INVALID) { 2318 // Indirect branch 2319 return false; 2320 } 2321 2322 if (CondBranch == nullptr) { 2323 const MCSymbol *TargetBB = getTargetSymbol(*I); 2324 if (TargetBB == nullptr) { 2325 // Unrecognized branch target 2326 return false; 2327 } 2328 FBB = TBB; 2329 TBB = TargetBB; 2330 CondBranch = &*I; 2331 continue; 2332 } 2333 2334 llvm_unreachable("multiple conditional branches in one BB"); 2335 } 2336 return true; 2337 } 2338 2339 template <typename Itr> 2340 std::pair<IndirectBranchType, MCInst *> 2341 analyzePICJumpTable(Itr II, 2342 Itr IE, 2343 MCPhysReg R1, 2344 MCPhysReg R2) const { 2345 // Analyze PIC-style jump table code template: 2346 // 2347 // lea PIC_JUMP_TABLE(%rip), {%r1|%r2} <- MemLocInstr 2348 // mov ({%r1|%r2}, %index, 4), {%r2|%r1} 2349 // add %r2, %r1 2350 // jmp *%r1 2351 // 2352 // (with any irrelevant instructions in-between) 2353 // 2354 // When we call this helper we've already determined %r1 and %r2, and 2355 // reverse instruction iterator \p II is pointing to the ADD instruction. 2356 // 2357 // PIC jump table looks like following: 2358 // 2359 // JT: ---------- 2360 // E1:| L1 - JT | 2361 // |----------| 2362 // E2:| L2 - JT | 2363 // |----------| 2364 // | | 2365 // ...... 2366 // En:| Ln - JT | 2367 // ---------- 2368 // 2369 // Where L1, L2, ..., Ln represent labels in the function. 2370 // 2371 // The actual relocations in the table will be of the form: 2372 // 2373 // Ln - JT 2374 // = (Ln - En) + (En - JT) 2375 // = R_X86_64_PC32(Ln) + En - JT 2376 // = R_X86_64_PC32(Ln + offsetof(En)) 2377 // 2378 LLVM_DEBUG(dbgs() << "Checking for PIC jump table\n"); 2379 MCInst *MemLocInstr = nullptr; 2380 const MCInst *MovInstr = nullptr; 2381 while (++II != IE) { 2382 MCInst &Instr = *II; 2383 const MCInstrDesc &InstrDesc = Info->get(Instr.getOpcode()); 2384 if (!InstrDesc.hasDefOfPhysReg(Instr, R1, *RegInfo) && 2385 !InstrDesc.hasDefOfPhysReg(Instr, R2, *RegInfo)) { 2386 // Ignore instructions that don't affect R1, R2 registers. 2387 continue; 2388 } else if (!MovInstr) { 2389 // Expect to see MOV instruction. 2390 if (!isMOVSX64rm32(Instr)) { 2391 LLVM_DEBUG(dbgs() << "MOV instruction expected.\n"); 2392 break; 2393 } 2394 2395 // Check if it's setting %r1 or %r2. In canonical form it sets %r2. 2396 // If it sets %r1 - rename the registers so we have to only check 2397 // a single form. 2398 unsigned MovDestReg = Instr.getOperand(0).getReg(); 2399 if (MovDestReg != R2) 2400 std::swap(R1, R2); 2401 if (MovDestReg != R2) { 2402 LLVM_DEBUG(dbgs() << "MOV instruction expected to set %r2\n"); 2403 break; 2404 } 2405 2406 // Verify operands for MOV. 2407 unsigned BaseRegNum; 2408 int64_t ScaleValue; 2409 unsigned IndexRegNum; 2410 int64_t DispValue; 2411 unsigned SegRegNum; 2412 if (!evaluateX86MemoryOperand(Instr, &BaseRegNum, 2413 &ScaleValue, &IndexRegNum, 2414 &DispValue, &SegRegNum)) 2415 break; 2416 if (BaseRegNum != R1 || 2417 ScaleValue != 4 || 2418 IndexRegNum == X86::NoRegister || 2419 DispValue != 0 || 2420 SegRegNum != X86::NoRegister) 2421 break; 2422 MovInstr = &Instr; 2423 } else { 2424 if (!InstrDesc.hasDefOfPhysReg(Instr, R1, *RegInfo)) 2425 continue; 2426 if (!isLEA64r(Instr)) { 2427 LLVM_DEBUG(dbgs() << "LEA instruction expected\n"); 2428 break; 2429 } 2430 if (Instr.getOperand(0).getReg() != R1) { 2431 LLVM_DEBUG(dbgs() << "LEA instruction expected to set %r1\n"); 2432 break; 2433 } 2434 2435 // Verify operands for LEA. 2436 unsigned BaseRegNum; 2437 int64_t ScaleValue; 2438 unsigned IndexRegNum; 2439 const MCExpr *DispExpr = nullptr; 2440 int64_t DispValue; 2441 unsigned SegRegNum; 2442 if (!evaluateX86MemoryOperand(Instr, &BaseRegNum, 2443 &ScaleValue, &IndexRegNum, 2444 &DispValue, &SegRegNum, &DispExpr)) 2445 break; 2446 if (BaseRegNum != RegInfo->getProgramCounter() || 2447 IndexRegNum != X86::NoRegister || 2448 SegRegNum != X86::NoRegister || 2449 DispExpr == nullptr) 2450 break; 2451 MemLocInstr = &Instr; 2452 break; 2453 } 2454 } 2455 2456 if (!MemLocInstr) 2457 return std::make_pair(IndirectBranchType::UNKNOWN, nullptr); 2458 2459 LLVM_DEBUG(dbgs() << "checking potential PIC jump table\n"); 2460 return std::make_pair(IndirectBranchType::POSSIBLE_PIC_JUMP_TABLE, 2461 MemLocInstr); 2462 } 2463 2464 IndirectBranchType analyzeIndirectBranch( 2465 MCInst &Instruction, 2466 InstructionIterator Begin, 2467 InstructionIterator End, 2468 const unsigned PtrSize, 2469 MCInst *&MemLocInstrOut, 2470 unsigned &BaseRegNumOut, 2471 unsigned &IndexRegNumOut, 2472 int64_t &DispValueOut, 2473 const MCExpr *&DispExprOut, 2474 MCInst *&PCRelBaseOut 2475 ) const override { 2476 // Try to find a (base) memory location from where the address for 2477 // the indirect branch is loaded. For X86-64 the memory will be specified 2478 // in the following format: 2479 // 2480 // {%rip}/{%basereg} + Imm + IndexReg * Scale 2481 // 2482 // We are interested in the cases where Scale == sizeof(uintptr_t) and 2483 // the contents of the memory are presumably an array of pointers to code. 2484 // 2485 // Normal jump table: 2486 // 2487 // jmp *(JUMP_TABLE, %index, Scale) <- MemLocInstr 2488 // 2489 // or 2490 // 2491 // mov (JUMP_TABLE, %index, Scale), %r1 <- MemLocInstr 2492 // ... 2493 // jmp %r1 2494 // 2495 // We handle PIC-style jump tables separately. 2496 // 2497 MemLocInstrOut = nullptr; 2498 BaseRegNumOut = X86::NoRegister; 2499 IndexRegNumOut = X86::NoRegister; 2500 DispValueOut = 0; 2501 DispExprOut = nullptr; 2502 2503 std::reverse_iterator<InstructionIterator> II(End); 2504 std::reverse_iterator<InstructionIterator> IE(Begin); 2505 2506 IndirectBranchType Type = IndirectBranchType::UNKNOWN; 2507 2508 // An instruction referencing memory used by jump instruction (directly or 2509 // via register). This location could be an array of function pointers 2510 // in case of indirect tail call, or a jump table. 2511 MCInst *MemLocInstr = nullptr; 2512 2513 if (MCPlus::getNumPrimeOperands(Instruction) == 1) { 2514 // If the indirect jump is on register - try to detect if the 2515 // register value is loaded from a memory location. 2516 assert(Instruction.getOperand(0).isReg() && "register operand expected"); 2517 const unsigned R1 = Instruction.getOperand(0).getReg(); 2518 // Check if one of the previous instructions defines the jump-on register. 2519 for (auto PrevII = II; PrevII != IE; ++PrevII) { 2520 MCInst &PrevInstr = *PrevII; 2521 const MCInstrDesc &PrevInstrDesc = Info->get(PrevInstr.getOpcode()); 2522 2523 if (!PrevInstrDesc.hasDefOfPhysReg(PrevInstr, R1, *RegInfo)) 2524 continue; 2525 2526 if (isMoveMem2Reg(PrevInstr)) { 2527 MemLocInstr = &PrevInstr; 2528 break; 2529 } else if (isADD64rr(PrevInstr)) { 2530 unsigned R2 = PrevInstr.getOperand(2).getReg(); 2531 if (R1 == R2) 2532 return IndirectBranchType::UNKNOWN; 2533 std::tie(Type, MemLocInstr) = analyzePICJumpTable(PrevII, IE, R1, R2); 2534 break; 2535 } else { 2536 return IndirectBranchType::UNKNOWN; 2537 } 2538 } 2539 if (!MemLocInstr) { 2540 // No definition seen for the register in this function so far. Could be 2541 // an input parameter - which means it is an external code reference. 2542 // It also could be that the definition happens to be in the code that 2543 // we haven't processed yet. Since we have to be conservative, return 2544 // as UNKNOWN case. 2545 return IndirectBranchType::UNKNOWN; 2546 } 2547 } else { 2548 MemLocInstr = &Instruction; 2549 } 2550 2551 const MCRegister RIPRegister = RegInfo->getProgramCounter(); 2552 2553 // Analyze the memory location. 2554 unsigned BaseRegNum, IndexRegNum, SegRegNum; 2555 int64_t ScaleValue, DispValue; 2556 const MCExpr *DispExpr; 2557 2558 if (!evaluateX86MemoryOperand(*MemLocInstr, &BaseRegNum, 2559 &ScaleValue, &IndexRegNum, 2560 &DispValue, &SegRegNum, 2561 &DispExpr)) 2562 return IndirectBranchType::UNKNOWN; 2563 2564 BaseRegNumOut = BaseRegNum; 2565 IndexRegNumOut = IndexRegNum; 2566 DispValueOut = DispValue; 2567 DispExprOut = DispExpr; 2568 2569 if ((BaseRegNum != X86::NoRegister && BaseRegNum != RIPRegister) || 2570 SegRegNum != X86::NoRegister) 2571 return IndirectBranchType::UNKNOWN; 2572 2573 if (MemLocInstr == &Instruction && 2574 (!ScaleValue || IndexRegNum == X86::NoRegister)) { 2575 MemLocInstrOut = MemLocInstr; 2576 return IndirectBranchType::POSSIBLE_FIXED_BRANCH; 2577 } 2578 2579 if (Type == IndirectBranchType::POSSIBLE_PIC_JUMP_TABLE && 2580 (ScaleValue != 1 || BaseRegNum != RIPRegister)) 2581 return IndirectBranchType::UNKNOWN; 2582 2583 if (Type != IndirectBranchType::POSSIBLE_PIC_JUMP_TABLE && 2584 ScaleValue != PtrSize) 2585 return IndirectBranchType::UNKNOWN; 2586 2587 MemLocInstrOut = MemLocInstr; 2588 2589 return Type; 2590 } 2591 2592 /// Analyze a callsite to see if it could be a virtual method call. This only 2593 /// checks to see if the overall pattern is satisfied, it does not guarantee 2594 /// that the callsite is a true virtual method call. 2595 /// The format of virtual method calls that are recognized is one of the 2596 /// following: 2597 /// 2598 /// Form 1: (found in debug code) 2599 /// add METHOD_OFFSET, %VtableReg 2600 /// mov (%VtableReg), %MethodReg 2601 /// ... 2602 /// call or jmp *%MethodReg 2603 /// 2604 /// Form 2: 2605 /// mov METHOD_OFFSET(%VtableReg), %MethodReg 2606 /// ... 2607 /// call or jmp *%MethodReg 2608 /// 2609 /// Form 3: 2610 /// ... 2611 /// call or jmp *METHOD_OFFSET(%VtableReg) 2612 /// 2613 bool analyzeVirtualMethodCall(InstructionIterator ForwardBegin, 2614 InstructionIterator ForwardEnd, 2615 std::vector<MCInst *> &MethodFetchInsns, 2616 unsigned &VtableRegNum, 2617 unsigned &MethodRegNum, 2618 uint64_t &MethodOffset) const override { 2619 VtableRegNum = X86::NoRegister; 2620 MethodRegNum = X86::NoRegister; 2621 MethodOffset = 0; 2622 2623 std::reverse_iterator<InstructionIterator> Itr(ForwardEnd); 2624 std::reverse_iterator<InstructionIterator> End(ForwardBegin); 2625 2626 MCInst &CallInst = *Itr++; 2627 assert(isIndirectBranch(CallInst) || isCall(CallInst)); 2628 2629 unsigned BaseReg, IndexReg, SegmentReg; 2630 int64_t Scale, Disp; 2631 const MCExpr *DispExpr; 2632 2633 // The call can just be jmp offset(reg) 2634 if (evaluateX86MemoryOperand(CallInst, 2635 &BaseReg, 2636 &Scale, 2637 &IndexReg, 2638 &Disp, 2639 &SegmentReg, 2640 &DispExpr)) { 2641 if (!DispExpr && 2642 BaseReg != X86::RIP && 2643 BaseReg != X86::RBP && 2644 BaseReg != X86::NoRegister) { 2645 MethodRegNum = BaseReg; 2646 if (Scale == 1 && 2647 IndexReg == X86::NoRegister && 2648 SegmentReg == X86::NoRegister) { 2649 VtableRegNum = MethodRegNum; 2650 MethodOffset = Disp; 2651 MethodFetchInsns.push_back(&CallInst); 2652 return true; 2653 } 2654 } 2655 return false; 2656 } else if (CallInst.getOperand(0).isReg()) { 2657 MethodRegNum = CallInst.getOperand(0).getReg(); 2658 } else { 2659 return false; 2660 } 2661 2662 if (MethodRegNum == X86::RIP || MethodRegNum == X86::RBP) { 2663 VtableRegNum = X86::NoRegister; 2664 MethodRegNum = X86::NoRegister; 2665 return false; 2666 } 2667 2668 // find load from vtable, this may or may not include the method offset 2669 while (Itr != End) { 2670 MCInst &CurInst = *Itr++; 2671 const MCInstrDesc &Desc = Info->get(CurInst.getOpcode()); 2672 if (Desc.hasDefOfPhysReg(CurInst, MethodRegNum, *RegInfo)) { 2673 if (isLoad(CurInst) && 2674 evaluateX86MemoryOperand(CurInst, 2675 &BaseReg, 2676 &Scale, 2677 &IndexReg, 2678 &Disp, 2679 &SegmentReg, 2680 &DispExpr)) { 2681 if (!DispExpr && 2682 Scale == 1 && 2683 BaseReg != X86::RIP && 2684 BaseReg != X86::RBP && 2685 BaseReg != X86::NoRegister && 2686 IndexReg == X86::NoRegister && 2687 SegmentReg == X86::NoRegister && 2688 BaseReg != X86::RIP) { 2689 VtableRegNum = BaseReg; 2690 MethodOffset = Disp; 2691 MethodFetchInsns.push_back(&CurInst); 2692 if (MethodOffset != 0) 2693 return true; 2694 break; 2695 } 2696 } 2697 return false; 2698 } 2699 } 2700 2701 if (!VtableRegNum) 2702 return false; 2703 2704 // look for any adds affecting the method register. 2705 while (Itr != End) { 2706 MCInst &CurInst = *Itr++; 2707 const MCInstrDesc &Desc = Info->get(CurInst.getOpcode()); 2708 if (Desc.hasDefOfPhysReg(CurInst, VtableRegNum, *RegInfo)) { 2709 if (isADDri(CurInst)) { 2710 assert(!MethodOffset); 2711 MethodOffset = CurInst.getOperand(2).getImm(); 2712 MethodFetchInsns.insert(MethodFetchInsns.begin(), &CurInst); 2713 break; 2714 } 2715 } 2716 } 2717 2718 return true; 2719 } 2720 2721 bool createStackPointerIncrement(MCInst &Inst, int Size, 2722 bool NoFlagsClobber) const override { 2723 if (NoFlagsClobber) { 2724 Inst.setOpcode(X86::LEA64r); 2725 Inst.clear(); 2726 Inst.addOperand(MCOperand::createReg(X86::RSP)); 2727 Inst.addOperand(MCOperand::createReg(X86::RSP)); // BaseReg 2728 Inst.addOperand(MCOperand::createImm(1)); // ScaleAmt 2729 Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // IndexReg 2730 Inst.addOperand(MCOperand::createImm(-Size)); // Displacement 2731 Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // AddrSegmentReg 2732 return true; 2733 } 2734 Inst.setOpcode(X86::SUB64ri8); 2735 Inst.clear(); 2736 Inst.addOperand(MCOperand::createReg(X86::RSP)); 2737 Inst.addOperand(MCOperand::createReg(X86::RSP)); 2738 Inst.addOperand(MCOperand::createImm(Size)); 2739 return true; 2740 } 2741 2742 bool createStackPointerDecrement(MCInst &Inst, int Size, 2743 bool NoFlagsClobber) const override { 2744 if (NoFlagsClobber) { 2745 Inst.setOpcode(X86::LEA64r); 2746 Inst.clear(); 2747 Inst.addOperand(MCOperand::createReg(X86::RSP)); 2748 Inst.addOperand(MCOperand::createReg(X86::RSP)); // BaseReg 2749 Inst.addOperand(MCOperand::createImm(1)); // ScaleAmt 2750 Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // IndexReg 2751 Inst.addOperand(MCOperand::createImm(Size)); // Displacement 2752 Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // AddrSegmentReg 2753 return true; 2754 } 2755 Inst.setOpcode(X86::ADD64ri8); 2756 Inst.clear(); 2757 Inst.addOperand(MCOperand::createReg(X86::RSP)); 2758 Inst.addOperand(MCOperand::createReg(X86::RSP)); 2759 Inst.addOperand(MCOperand::createImm(Size)); 2760 return true; 2761 } 2762 2763 bool createSaveToStack(MCInst &Inst, const MCPhysReg &StackReg, int Offset, 2764 const MCPhysReg &SrcReg, int Size) const override { 2765 unsigned NewOpcode; 2766 switch (Size) { 2767 default: 2768 return false; 2769 case 2: NewOpcode = X86::MOV16mr; break; 2770 case 4: NewOpcode = X86::MOV32mr; break; 2771 case 8: NewOpcode = X86::MOV64mr; break; 2772 } 2773 Inst.setOpcode(NewOpcode); 2774 Inst.clear(); 2775 Inst.addOperand(MCOperand::createReg(StackReg)); // BaseReg 2776 Inst.addOperand(MCOperand::createImm(1)); // ScaleAmt 2777 Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // IndexReg 2778 Inst.addOperand(MCOperand::createImm(Offset)); // Displacement 2779 Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // AddrSegmentReg 2780 Inst.addOperand(MCOperand::createReg(SrcReg)); 2781 return true; 2782 } 2783 2784 bool createRestoreFromStack(MCInst &Inst, const MCPhysReg &StackReg, 2785 int Offset, const MCPhysReg &DstReg, 2786 int Size) const override { 2787 return createLoad(Inst, StackReg, /*Scale=*/1, /*IndexReg=*/X86::NoRegister, 2788 Offset, nullptr, /*AddrSegmentReg=*/X86::NoRegister, 2789 DstReg, Size); 2790 } 2791 2792 bool createLoad(MCInst &Inst, const MCPhysReg &BaseReg, int64_t Scale, 2793 const MCPhysReg &IndexReg, int64_t Offset, 2794 const MCExpr *OffsetExpr, const MCPhysReg &AddrSegmentReg, 2795 const MCPhysReg &DstReg, int Size) const override { 2796 unsigned NewOpcode; 2797 switch (Size) { 2798 default: 2799 return false; 2800 case 2: NewOpcode = X86::MOV16rm; break; 2801 case 4: NewOpcode = X86::MOV32rm; break; 2802 case 8: NewOpcode = X86::MOV64rm; break; 2803 } 2804 Inst.setOpcode(NewOpcode); 2805 Inst.clear(); 2806 Inst.addOperand(MCOperand::createReg(DstReg)); 2807 Inst.addOperand(MCOperand::createReg(BaseReg)); 2808 Inst.addOperand(MCOperand::createImm(Scale)); 2809 Inst.addOperand(MCOperand::createReg(IndexReg)); 2810 if (OffsetExpr) 2811 Inst.addOperand(MCOperand::createExpr(OffsetExpr)); // Displacement 2812 else 2813 Inst.addOperand(MCOperand::createImm(Offset)); // Displacement 2814 Inst.addOperand(MCOperand::createReg(AddrSegmentReg)); // AddrSegmentReg 2815 return true; 2816 } 2817 2818 void createLoadImmediate(MCInst &Inst, const MCPhysReg Dest, 2819 uint32_t Imm) const override { 2820 Inst.setOpcode(X86::MOV64ri32); 2821 Inst.clear(); 2822 Inst.addOperand(MCOperand::createReg(Dest)); 2823 Inst.addOperand(MCOperand::createImm(Imm)); 2824 } 2825 2826 bool createIncMemory(MCInst &Inst, const MCSymbol *Target, 2827 MCContext *Ctx) const override { 2828 2829 Inst.setOpcode(X86::LOCK_INC64m); 2830 Inst.clear(); 2831 Inst.addOperand(MCOperand::createReg(X86::RIP)); // BaseReg 2832 Inst.addOperand(MCOperand::createImm(1)); // ScaleAmt 2833 Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // IndexReg 2834 2835 Inst.addOperand(MCOperand::createExpr( 2836 MCSymbolRefExpr::create(Target, MCSymbolRefExpr::VK_None, 2837 *Ctx))); // Displacement 2838 Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // AddrSegmentReg 2839 return true; 2840 } 2841 2842 bool createIJmp32Frag(SmallVectorImpl<MCInst> &Insts, 2843 const MCOperand &BaseReg, const MCOperand &Scale, 2844 const MCOperand &IndexReg, const MCOperand &Offset, 2845 const MCOperand &TmpReg) const override { 2846 // The code fragment we emit here is: 2847 // 2848 // mov32 (%base, %index, scale), %tmpreg 2849 // ijmp *(%tmpreg) 2850 // 2851 MCInst IJmp; 2852 IJmp.setOpcode(X86::JMP64r); 2853 IJmp.addOperand(TmpReg); 2854 2855 MCInst Load; 2856 Load.setOpcode(X86::MOV32rm); 2857 Load.addOperand(TmpReg); 2858 Load.addOperand(BaseReg); 2859 Load.addOperand(Scale); 2860 Load.addOperand(IndexReg); 2861 Load.addOperand(Offset); 2862 Load.addOperand(MCOperand::createReg(X86::NoRegister)); 2863 2864 Insts.push_back(Load); 2865 Insts.push_back(IJmp); 2866 return true; 2867 } 2868 2869 bool createNoop(MCInst &Inst) const override { 2870 Inst.setOpcode(X86::NOOP); 2871 return true; 2872 } 2873 2874 bool createReturn(MCInst &Inst) const override { 2875 Inst.setOpcode(X86::RET64); 2876 return true; 2877 } 2878 2879 InstructionListType createInlineMemcpy(bool ReturnEnd) const override { 2880 InstructionListType Code; 2881 if (ReturnEnd) { 2882 Code.emplace_back(MCInstBuilder(X86::LEA64r) 2883 .addReg(X86::RAX) 2884 .addReg(X86::RDI) 2885 .addImm(1) 2886 .addReg(X86::RDX) 2887 .addImm(0) 2888 .addReg(X86::NoRegister)); 2889 } else { 2890 Code.emplace_back(MCInstBuilder(X86::MOV64rr) 2891 .addReg(X86::RAX) 2892 .addReg(X86::RDI)); 2893 } 2894 Code.emplace_back(MCInstBuilder(X86::MOV32rr) 2895 .addReg(X86::ECX) 2896 .addReg(X86::EDX)); 2897 Code.emplace_back(MCInstBuilder(X86::REP_MOVSB_64)); 2898 2899 return Code; 2900 } 2901 2902 InstructionListType createOneByteMemcpy() const override { 2903 InstructionListType Code; 2904 Code.emplace_back(MCInstBuilder(X86::MOV8rm) 2905 .addReg(X86::CL) 2906 .addReg(X86::RSI) 2907 .addImm(0) 2908 .addReg(X86::NoRegister) 2909 .addImm(0) 2910 .addReg(X86::NoRegister)); 2911 Code.emplace_back(MCInstBuilder(X86::MOV8mr) 2912 .addReg(X86::RDI) 2913 .addImm(0) 2914 .addReg(X86::NoRegister) 2915 .addImm(0) 2916 .addReg(X86::NoRegister) 2917 .addReg(X86::CL)); 2918 Code.emplace_back(MCInstBuilder(X86::MOV64rr) 2919 .addReg(X86::RAX) 2920 .addReg(X86::RDI)); 2921 return Code; 2922 } 2923 2924 InstructionListType createCmpJE(MCPhysReg RegNo, int64_t Imm, 2925 const MCSymbol *Target, 2926 MCContext *Ctx) const override { 2927 InstructionListType Code; 2928 Code.emplace_back(MCInstBuilder(X86::CMP64ri8) 2929 .addReg(RegNo) 2930 .addImm(Imm)); 2931 Code.emplace_back(MCInstBuilder(X86::JCC_1) 2932 .addExpr(MCSymbolRefExpr::create( 2933 Target, MCSymbolRefExpr::VK_None, *Ctx)) 2934 .addImm(X86::COND_E)); 2935 return Code; 2936 } 2937 2938 Optional<Relocation> 2939 createRelocation(const MCFixup &Fixup, 2940 const MCAsmBackend &MAB) const override { 2941 const MCFixupKindInfo &FKI = MAB.getFixupKindInfo(Fixup.getKind()); 2942 2943 assert(FKI.TargetOffset == 0 && "0-bit relocation offset expected"); 2944 const uint64_t RelOffset = Fixup.getOffset(); 2945 2946 uint64_t RelType; 2947 if (FKI.Flags & MCFixupKindInfo::FKF_IsPCRel) { 2948 switch (FKI.TargetSize) { 2949 default: 2950 return NoneType(); 2951 case 8: RelType = ELF::R_X86_64_PC8; break; 2952 case 16: RelType = ELF::R_X86_64_PC16; break; 2953 case 32: RelType = ELF::R_X86_64_PC32; break; 2954 case 64: RelType = ELF::R_X86_64_PC64; break; 2955 } 2956 } else { 2957 switch (FKI.TargetSize) { 2958 default: 2959 return NoneType(); 2960 case 8: RelType = ELF::R_X86_64_8; break; 2961 case 16: RelType = ELF::R_X86_64_16; break; 2962 case 32: RelType = ELF::R_X86_64_32; break; 2963 case 64: RelType = ELF::R_X86_64_64; break; 2964 } 2965 } 2966 2967 // Extract a symbol and an addend out of the fixup value expression. 2968 // 2969 // Only the following limited expression types are supported: 2970 // Symbol + Addend 2971 // Symbol 2972 uint64_t Addend = 0; 2973 MCSymbol *Symbol = nullptr; 2974 const MCExpr *ValueExpr = Fixup.getValue(); 2975 if (ValueExpr->getKind() == MCExpr::Binary) { 2976 const auto *BinaryExpr = cast<MCBinaryExpr>(ValueExpr); 2977 assert(BinaryExpr->getOpcode() == MCBinaryExpr::Add && 2978 "unexpected binary expression"); 2979 const MCExpr *LHS = BinaryExpr->getLHS(); 2980 assert(LHS->getKind() == MCExpr::SymbolRef && "unexpected LHS"); 2981 Symbol = const_cast<MCSymbol *>(this->getTargetSymbol(LHS)); 2982 const MCExpr *RHS = BinaryExpr->getRHS(); 2983 assert(RHS->getKind() == MCExpr::Constant && "unexpected RHS"); 2984 Addend = cast<MCConstantExpr>(RHS)->getValue(); 2985 } else { 2986 assert(ValueExpr->getKind() == MCExpr::SymbolRef && "unexpected value"); 2987 Symbol = const_cast<MCSymbol *>(this->getTargetSymbol(ValueExpr)); 2988 } 2989 2990 return Relocation({RelOffset, Symbol, RelType, Addend, 0}); 2991 } 2992 2993 bool replaceImmWithSymbolRef(MCInst &Inst, const MCSymbol *Symbol, 2994 int64_t Addend, MCContext *Ctx, int64_t &Value, 2995 uint64_t RelType) const override { 2996 unsigned ImmOpNo = -1U; 2997 2998 for (unsigned Index = 0; 2999 Index < MCPlus::getNumPrimeOperands(Inst); ++Index) { 3000 if (Inst.getOperand(Index).isImm()) { 3001 ImmOpNo = Index; 3002 // TODO: this is a bit hacky. It finds the correct operand by 3003 // searching for a specific immediate value. If no value is 3004 // provided it defaults to the last immediate operand found. 3005 // This could lead to unexpected results if the instruction 3006 // has more than one immediate with the same value. 3007 if (Inst.getOperand(ImmOpNo).getImm() == Value) 3008 break; 3009 } 3010 } 3011 3012 if (ImmOpNo == -1U) 3013 return false; 3014 3015 Value = Inst.getOperand(ImmOpNo).getImm(); 3016 3017 setOperandToSymbolRef(Inst, ImmOpNo, Symbol, Addend, Ctx, RelType); 3018 3019 return true; 3020 } 3021 3022 bool replaceRegWithImm(MCInst &Inst, unsigned Register, 3023 int64_t Imm) const override { 3024 3025 enum CheckSignExt : uint8_t { 3026 NOCHECK = 0, 3027 CHECK8, 3028 CHECK32, 3029 }; 3030 3031 using CheckList = std::vector<std::pair<CheckSignExt, unsigned>>; 3032 struct InstInfo { 3033 // Size in bytes that Inst loads from memory. 3034 uint8_t DataSize; 3035 3036 // True when the target operand has to be duplicated because the opcode 3037 // expects a LHS operand. 3038 bool HasLHS; 3039 3040 // List of checks and corresponding opcodes to be used. We try to use the 3041 // smallest possible immediate value when various sizes are available, 3042 // hence we may need to check whether a larger constant fits in a smaller 3043 // immediate. 3044 CheckList Checks; 3045 }; 3046 3047 InstInfo I; 3048 3049 switch (Inst.getOpcode()) { 3050 default: { 3051 switch (getPushSize(Inst)) { 3052 3053 case 2: I = {2, false, {{CHECK8, X86::PUSH16i8}, {NOCHECK, X86::PUSHi16}}}; break; 3054 case 4: I = {4, false, {{CHECK8, X86::PUSH32i8}, {NOCHECK, X86::PUSHi32}}}; break; 3055 case 8: I = {8, false, {{CHECK8, X86::PUSH64i8}, 3056 {CHECK32, X86::PUSH64i32}, 3057 {NOCHECK, Inst.getOpcode()}}}; break; 3058 default: return false; 3059 } 3060 break; 3061 } 3062 3063 // MOV 3064 case X86::MOV8rr: I = {1, false, {{NOCHECK, X86::MOV8ri}}}; break; 3065 case X86::MOV16rr: I = {2, false, {{NOCHECK, X86::MOV16ri}}}; break; 3066 case X86::MOV32rr: I = {4, false, {{NOCHECK, X86::MOV32ri}}}; break; 3067 case X86::MOV64rr: I = {8, false, {{CHECK32, X86::MOV64ri32}, 3068 {NOCHECK, X86::MOV64ri}}}; break; 3069 3070 case X86::MOV8mr: I = {1, false, {{NOCHECK, X86::MOV8mi}}}; break; 3071 case X86::MOV16mr: I = {2, false, {{NOCHECK, X86::MOV16mi}}}; break; 3072 case X86::MOV32mr: I = {4, false, {{NOCHECK, X86::MOV32mi}}}; break; 3073 case X86::MOV64mr: I = {8, false, {{CHECK32, X86::MOV64mi32}, 3074 {NOCHECK, X86::MOV64mr}}}; break; 3075 3076 // MOVZX 3077 case X86::MOVZX16rr8: I = {1, false, {{NOCHECK, X86::MOV16ri}}}; break; 3078 case X86::MOVZX32rr8: I = {1, false, {{NOCHECK, X86::MOV32ri}}}; break; 3079 case X86::MOVZX32rr16: I = {2, false, {{NOCHECK, X86::MOV32ri}}}; break; 3080 3081 // CMP 3082 case X86::CMP8rr: I = {1, false, {{NOCHECK, X86::CMP8ri}}}; break; 3083 case X86::CMP16rr: I = {2, false, {{CHECK8, X86::CMP16ri8}, 3084 {NOCHECK, X86::CMP16ri}}}; break; 3085 case X86::CMP32rr: I = {4, false, {{CHECK8, X86::CMP32ri8}, 3086 {NOCHECK, X86::CMP32ri}}}; break; 3087 case X86::CMP64rr: I = {8, false, {{CHECK8, X86::CMP64ri8}, 3088 {CHECK32, X86::CMP64ri32}, 3089 {NOCHECK, X86::CMP64rr}}}; break; 3090 3091 // TEST 3092 case X86::TEST8rr: I = {1, false, {{NOCHECK, X86::TEST8ri}}}; break; 3093 case X86::TEST16rr: I = {2, false, {{NOCHECK, X86::TEST16ri}}}; break; 3094 case X86::TEST32rr: I = {4, false, {{NOCHECK, X86::TEST32ri}}}; break; 3095 case X86::TEST64rr: I = {8, false, {{CHECK32, X86::TEST64ri32}, 3096 {NOCHECK, X86::TEST64rr}}}; break; 3097 3098 // ADD 3099 case X86::ADD8rr: I = {1, true, {{NOCHECK, X86::ADD8ri}}}; break; 3100 case X86::ADD16rr: I = {2, true, {{CHECK8, X86::ADD16ri8}, 3101 {NOCHECK, X86::ADD16ri}}}; break; 3102 case X86::ADD32rr: I = {4, true, {{CHECK8, X86::ADD32ri8}, 3103 {NOCHECK, X86::ADD32ri}}}; break; 3104 case X86::ADD64rr: I = {8, true, {{CHECK8, X86::ADD64ri8}, 3105 {CHECK32, X86::ADD64ri32}, 3106 {NOCHECK, X86::ADD64rr}}}; break; 3107 3108 // SUB 3109 case X86::SUB8rr: I = {1, true, {{NOCHECK, X86::SUB8ri}}}; break; 3110 case X86::SUB16rr: I = {2, true, {{CHECK8, X86::SUB16ri8}, 3111 {NOCHECK, X86::SUB16ri}}}; break; 3112 case X86::SUB32rr: I = {4, true, {{CHECK8, X86::SUB32ri8}, 3113 {NOCHECK, X86::SUB32ri}}}; break; 3114 case X86::SUB64rr: I = {8, true, {{CHECK8, X86::SUB64ri8}, 3115 {CHECK32, X86::SUB64ri32}, 3116 {NOCHECK, X86::SUB64rr}}}; break; 3117 3118 // AND 3119 case X86::AND8rr: I = {1, true, {{NOCHECK, X86::AND8ri}}}; break; 3120 case X86::AND16rr: I = {2, true, {{CHECK8, X86::AND16ri8}, 3121 {NOCHECK, X86::AND16ri}}}; break; 3122 case X86::AND32rr: I = {4, true, {{CHECK8, X86::AND32ri8}, 3123 {NOCHECK, X86::AND32ri}}}; break; 3124 case X86::AND64rr: I = {8, true, {{CHECK8, X86::AND64ri8}, 3125 {CHECK32, X86::AND64ri32}, 3126 {NOCHECK, X86::AND64rr}}}; break; 3127 3128 // OR 3129 case X86::OR8rr: I = {1, true, {{NOCHECK, X86::OR8ri}}}; break; 3130 case X86::OR16rr: I = {2, true, {{CHECK8, X86::OR16ri8}, 3131 {NOCHECK, X86::OR16ri}}}; break; 3132 case X86::OR32rr: I = {4, true, {{CHECK8, X86::OR32ri8}, 3133 {NOCHECK, X86::OR32ri}}}; break; 3134 case X86::OR64rr: I = {8, true, {{CHECK8, X86::OR64ri8}, 3135 {CHECK32, X86::OR64ri32}, 3136 {NOCHECK, X86::OR64rr}}}; break; 3137 3138 // XOR 3139 case X86::XOR8rr: I = {1, true, {{NOCHECK, X86::XOR8ri}}}; break; 3140 case X86::XOR16rr: I = {2, true, {{CHECK8, X86::XOR16ri8}, 3141 {NOCHECK, X86::XOR16ri}}}; break; 3142 case X86::XOR32rr: I = {4, true, {{CHECK8, X86::XOR32ri8}, 3143 {NOCHECK, X86::XOR32ri}}}; break; 3144 case X86::XOR64rr: I = {8, true, {{CHECK8, X86::XOR64ri8}, 3145 {CHECK32, X86::XOR64ri32}, 3146 {NOCHECK, X86::XOR64rr}}}; break; 3147 } 3148 3149 // Compute the new opcode. 3150 unsigned NewOpcode = 0; 3151 for (const std::pair<CheckSignExt, unsigned> &Check : I.Checks) { 3152 NewOpcode = Check.second; 3153 if (Check.first == NOCHECK) 3154 break; 3155 if (Check.first == CHECK8 && Imm >= std::numeric_limits<int8_t>::min() && 3156 Imm <= std::numeric_limits<int8_t>::max()) 3157 break; 3158 if (Check.first == CHECK32 && 3159 Imm >= std::numeric_limits<int32_t>::min() && 3160 Imm <= std::numeric_limits<int32_t>::max()) 3161 break; 3162 } 3163 if (NewOpcode == Inst.getOpcode()) 3164 return false; 3165 3166 const MCInstrDesc &InstDesc = Info->get(Inst.getOpcode()); 3167 3168 unsigned NumFound = 0; 3169 for (unsigned Index = InstDesc.getNumDefs() + (I.HasLHS ? 1 : 0), 3170 E = InstDesc.getNumOperands(); Index != E; ++Index) { 3171 if (Inst.getOperand(Index).isReg() && 3172 Inst.getOperand(Index).getReg() == Register) 3173 NumFound++; 3174 } 3175 3176 if (NumFound != 1) 3177 return false; 3178 3179 // Iterate backwards to replace the src register before the src/dest 3180 // register as in AND, ADD, and SUB Only iterate through src operands that 3181 // arent also dest operands 3182 for (unsigned Index = InstDesc.getNumOperands() - 1, 3183 E = InstDesc.getNumDefs() + (I.HasLHS ? 0 : -1); 3184 Index != E; --Index) { 3185 if (!Inst.getOperand(Index).isReg() || 3186 Inst.getOperand(Index).getReg() != Register) 3187 continue; 3188 MCOperand NewOperand = MCOperand::createImm(Imm); 3189 Inst.getOperand(Index) = NewOperand; 3190 break; 3191 } 3192 3193 Inst.setOpcode(NewOpcode); 3194 3195 return true; 3196 } 3197 3198 bool replaceRegWithReg(MCInst &Inst, unsigned ToReplace, 3199 unsigned ReplaceWith) const override { 3200 3201 // Get the HasLHS value so that iteration can be done 3202 bool HasLHS; 3203 if (isAND(Inst.getOpcode()) || isADD(Inst.getOpcode()) || isSUB(Inst)) { 3204 HasLHS = true; 3205 } else if (isPop(Inst) || isPush(Inst) || isCMP(Inst.getOpcode()) || 3206 isTEST(Inst.getOpcode())) { 3207 HasLHS = false; 3208 } else { 3209 switch (Inst.getOpcode()) { 3210 case X86::MOV8rr: 3211 case X86::MOV8rm: 3212 case X86::MOV8mr: 3213 case X86::MOV8ri: 3214 case X86::MOV16rr: 3215 case X86::MOV16rm: 3216 case X86::MOV16mr: 3217 case X86::MOV16ri: 3218 case X86::MOV32rr: 3219 case X86::MOV32rm: 3220 case X86::MOV32mr: 3221 case X86::MOV32ri: 3222 case X86::MOV64rr: 3223 case X86::MOV64rm: 3224 case X86::MOV64mr: 3225 case X86::MOV64ri: 3226 case X86::MOVZX16rr8: 3227 case X86::MOVZX32rr8: 3228 case X86::MOVZX32rr16: 3229 case X86::MOVSX32rm8: 3230 case X86::MOVSX32rr8: 3231 case X86::MOVSX64rm32: 3232 case X86::LEA64r: 3233 HasLHS = false; 3234 break; 3235 default: 3236 return false; 3237 } 3238 } 3239 3240 const MCInstrDesc &InstDesc = Info->get(Inst.getOpcode()); 3241 3242 bool FoundOne = false; 3243 3244 // Iterate only through src operands that arent also dest operands 3245 for (unsigned Index = InstDesc.getNumDefs() + (HasLHS ? 1 : 0), 3246 E = InstDesc.getNumOperands(); 3247 Index != E; ++Index) { 3248 BitVector RegAliases = getAliases(ToReplace, true); 3249 if (!Inst.getOperand(Index).isReg() || 3250 !RegAliases.test(Inst.getOperand(Index).getReg())) 3251 continue; 3252 // Resize register if needed 3253 unsigned SizedReplaceWith = getAliasSized( 3254 ReplaceWith, getRegSize(Inst.getOperand(Index).getReg())); 3255 MCOperand NewOperand = MCOperand::createReg(SizedReplaceWith); 3256 Inst.getOperand(Index) = NewOperand; 3257 FoundOne = true; 3258 } 3259 3260 // Return true if at least one operand was replaced 3261 return FoundOne; 3262 } 3263 3264 bool createUncondBranch(MCInst &Inst, const MCSymbol *TBB, 3265 MCContext *Ctx) const override { 3266 Inst.setOpcode(X86::JMP_1); 3267 Inst.addOperand(MCOperand::createExpr( 3268 MCSymbolRefExpr::create(TBB, MCSymbolRefExpr::VK_None, *Ctx))); 3269 return true; 3270 } 3271 3272 bool createCall(MCInst &Inst, const MCSymbol *Target, 3273 MCContext *Ctx) override { 3274 Inst.setOpcode(X86::CALL64pcrel32); 3275 Inst.addOperand(MCOperand::createExpr( 3276 MCSymbolRefExpr::create(Target, MCSymbolRefExpr::VK_None, *Ctx))); 3277 return true; 3278 } 3279 3280 bool createTailCall(MCInst &Inst, const MCSymbol *Target, 3281 MCContext *Ctx) override { 3282 return createDirectCall(Inst, Target, Ctx, /*IsTailCall*/ true); 3283 } 3284 3285 void createLongTailCall(InstructionListType &Seq, const MCSymbol *Target, 3286 MCContext *Ctx) override { 3287 Seq.clear(); 3288 Seq.emplace_back(); 3289 createDirectCall(Seq.back(), Target, Ctx, /*IsTailCall*/ true); 3290 } 3291 3292 bool createTrap(MCInst &Inst) const override { 3293 Inst.clear(); 3294 Inst.setOpcode(X86::TRAP); 3295 return true; 3296 } 3297 3298 bool reverseBranchCondition(MCInst &Inst, const MCSymbol *TBB, 3299 MCContext *Ctx) const override { 3300 unsigned InvCC = getInvertedCondCode(getCondCode(Inst)); 3301 assert(InvCC != X86::COND_INVALID && "invalid branch instruction"); 3302 Inst.getOperand(Info->get(Inst.getOpcode()).NumOperands - 1).setImm(InvCC); 3303 Inst.getOperand(0) = MCOperand::createExpr( 3304 MCSymbolRefExpr::create(TBB, MCSymbolRefExpr::VK_None, *Ctx)); 3305 return true; 3306 } 3307 3308 bool replaceBranchCondition(MCInst &Inst, const MCSymbol *TBB, MCContext *Ctx, 3309 unsigned CC) const override { 3310 if (CC == X86::COND_INVALID) 3311 return false; 3312 Inst.getOperand(Info->get(Inst.getOpcode()).NumOperands - 1).setImm(CC); 3313 Inst.getOperand(0) = MCOperand::createExpr( 3314 MCSymbolRefExpr::create(TBB, MCSymbolRefExpr::VK_None, *Ctx)); 3315 return true; 3316 } 3317 3318 unsigned getCanonicalBranchCondCode(unsigned CC) const override { 3319 switch (CC) { 3320 default: return X86::COND_INVALID; 3321 3322 case X86::COND_E: return X86::COND_E; 3323 case X86::COND_NE: return X86::COND_E; 3324 3325 case X86::COND_L: return X86::COND_L; 3326 case X86::COND_GE: return X86::COND_L; 3327 3328 case X86::COND_LE: return X86::COND_G; 3329 case X86::COND_G: return X86::COND_G; 3330 3331 case X86::COND_B: return X86::COND_B; 3332 case X86::COND_AE: return X86::COND_B; 3333 3334 case X86::COND_BE: return X86::COND_A; 3335 case X86::COND_A: return X86::COND_A; 3336 3337 case X86::COND_S: return X86::COND_S; 3338 case X86::COND_NS: return X86::COND_S; 3339 3340 case X86::COND_P: return X86::COND_P; 3341 case X86::COND_NP: return X86::COND_P; 3342 3343 case X86::COND_O: return X86::COND_O; 3344 case X86::COND_NO: return X86::COND_O; 3345 } 3346 } 3347 3348 bool replaceBranchTarget(MCInst &Inst, const MCSymbol *TBB, 3349 MCContext *Ctx) const override { 3350 assert((isCall(Inst) || isBranch(Inst)) && !isIndirectBranch(Inst) && 3351 "Invalid instruction"); 3352 Inst.getOperand(0) = MCOperand::createExpr( 3353 MCSymbolRefExpr::create(TBB, MCSymbolRefExpr::VK_None, *Ctx)); 3354 return true; 3355 } 3356 3357 MCPhysReg getX86R11() const override { 3358 return X86::R11; 3359 } 3360 3361 MCPhysReg getNoRegister() const override { 3362 return X86::NoRegister; 3363 } 3364 3365 MCPhysReg getIntArgRegister(unsigned ArgNo) const override { 3366 // FIXME: this should depend on the calling convention. 3367 switch (ArgNo) { 3368 case 0: return X86::RDI; 3369 case 1: return X86::RSI; 3370 case 2: return X86::RDX; 3371 case 3: return X86::RCX; 3372 case 4: return X86::R8; 3373 case 5: return X86::R9; 3374 default: return getNoRegister(); 3375 } 3376 } 3377 3378 void createPause(MCInst &Inst) const override { 3379 Inst.clear(); 3380 Inst.setOpcode(X86::PAUSE); 3381 } 3382 3383 void createLfence(MCInst &Inst) const override { 3384 Inst.clear(); 3385 Inst.setOpcode(X86::LFENCE); 3386 } 3387 3388 bool createDirectCall(MCInst &Inst, const MCSymbol *Target, MCContext *Ctx, 3389 bool IsTailCall) override { 3390 Inst.clear(); 3391 Inst.setOpcode(IsTailCall ? X86::JMP_4 : X86::CALL64pcrel32); 3392 Inst.addOperand(MCOperand::createExpr( 3393 MCSymbolRefExpr::create(Target, MCSymbolRefExpr::VK_None, *Ctx))); 3394 if (IsTailCall) 3395 setTailCall(Inst); 3396 return true; 3397 } 3398 3399 void createShortJmp(InstructionListType &Seq, const MCSymbol *Target, 3400 MCContext *Ctx, bool IsTailCall) override { 3401 Seq.clear(); 3402 MCInst Inst; 3403 Inst.setOpcode(X86::JMP_1); 3404 Inst.addOperand(MCOperand::createExpr( 3405 MCSymbolRefExpr::create(Target, MCSymbolRefExpr::VK_None, *Ctx))); 3406 if (IsTailCall) 3407 setTailCall(Inst); 3408 Seq.emplace_back(Inst); 3409 } 3410 3411 bool isConditionalMove(const MCInst &Inst) const override { 3412 unsigned OpCode = Inst.getOpcode(); 3413 return (OpCode == X86::CMOV16rr || OpCode == X86::CMOV32rr || 3414 OpCode == X86::CMOV64rr); 3415 } 3416 3417 bool isBranchOnMem(const MCInst &Inst) const override { 3418 unsigned OpCode = Inst.getOpcode(); 3419 if (OpCode == X86::CALL64m || (OpCode == X86::JMP32m && isTailCall(Inst)) || 3420 OpCode == X86::JMP64m) 3421 return true; 3422 3423 return false; 3424 } 3425 3426 bool isBranchOnReg(const MCInst &Inst) const override { 3427 unsigned OpCode = Inst.getOpcode(); 3428 if (OpCode == X86::CALL64r || (OpCode == X86::JMP32r && isTailCall(Inst)) || 3429 OpCode == X86::JMP64r) 3430 return true; 3431 3432 return false; 3433 } 3434 3435 void createPushRegister(MCInst &Inst, MCPhysReg Reg, 3436 unsigned Size) const override { 3437 Inst.clear(); 3438 unsigned NewOpcode = 0; 3439 if (Reg == X86::EFLAGS) { 3440 switch (Size) { 3441 case 2: NewOpcode = X86::PUSHF16; break; 3442 case 4: NewOpcode = X86::PUSHF32; break; 3443 case 8: NewOpcode = X86::PUSHF64; break; 3444 default: 3445 assert(false); 3446 } 3447 Inst.setOpcode(NewOpcode); 3448 return; 3449 } 3450 switch (Size) { 3451 case 2: NewOpcode = X86::PUSH16r; break; 3452 case 4: NewOpcode = X86::PUSH32r; break; 3453 case 8: NewOpcode = X86::PUSH64r; break; 3454 default: 3455 assert(false); 3456 } 3457 Inst.setOpcode(NewOpcode); 3458 Inst.addOperand(MCOperand::createReg(Reg)); 3459 } 3460 3461 void createPopRegister(MCInst &Inst, MCPhysReg Reg, 3462 unsigned Size) const override { 3463 Inst.clear(); 3464 unsigned NewOpcode = 0; 3465 if (Reg == X86::EFLAGS) { 3466 switch (Size) { 3467 case 2: NewOpcode = X86::POPF16; break; 3468 case 4: NewOpcode = X86::POPF32; break; 3469 case 8: NewOpcode = X86::POPF64; break; 3470 default: 3471 assert(false); 3472 } 3473 Inst.setOpcode(NewOpcode); 3474 return; 3475 } 3476 switch (Size) { 3477 case 2: NewOpcode = X86::POP16r; break; 3478 case 4: NewOpcode = X86::POP32r; break; 3479 case 8: NewOpcode = X86::POP64r; break; 3480 default: 3481 assert(false); 3482 } 3483 Inst.setOpcode(NewOpcode); 3484 Inst.addOperand(MCOperand::createReg(Reg)); 3485 } 3486 3487 void createPushFlags(MCInst &Inst, unsigned Size) const override { 3488 return createPushRegister(Inst, X86::EFLAGS, Size); 3489 } 3490 3491 void createPopFlags(MCInst &Inst, unsigned Size) const override { 3492 return createPopRegister(Inst, X86::EFLAGS, Size); 3493 } 3494 3495 void createAddRegImm(MCInst &Inst, MCPhysReg Reg, int64_t Value, 3496 unsigned Size) const { 3497 unsigned int Opcode; 3498 switch (Size) { 3499 case 1: Opcode = X86::ADD8ri; break; 3500 case 2: Opcode = X86::ADD16ri; break; 3501 case 4: Opcode = X86::ADD32ri; break; 3502 default: 3503 llvm_unreachable("Unexpected size"); 3504 } 3505 Inst.setOpcode(Opcode); 3506 Inst.clear(); 3507 Inst.addOperand(MCOperand::createReg(Reg)); 3508 Inst.addOperand(MCOperand::createReg(Reg)); 3509 Inst.addOperand(MCOperand::createImm(Value)); 3510 } 3511 3512 void createClearRegWithNoEFlagsUpdate(MCInst &Inst, MCPhysReg Reg, 3513 unsigned Size) const { 3514 unsigned int Opcode; 3515 switch (Size) { 3516 case 1: Opcode = X86::MOV8ri; break; 3517 case 2: Opcode = X86::MOV16ri; break; 3518 case 4: Opcode = X86::MOV32ri; break; 3519 case 8: Opcode = X86::MOV64ri; break; 3520 default: 3521 llvm_unreachable("Unexpected size"); 3522 } 3523 Inst.setOpcode(Opcode); 3524 Inst.clear(); 3525 Inst.addOperand(MCOperand::createReg(Reg)); 3526 Inst.addOperand(MCOperand::createImm(0)); 3527 } 3528 3529 void createX86SaveOVFlagToRegister(MCInst &Inst, MCPhysReg Reg) const { 3530 Inst.setOpcode(X86::SETCCr); 3531 Inst.clear(); 3532 Inst.addOperand(MCOperand::createReg(Reg)); 3533 Inst.addOperand(MCOperand::createImm(X86::COND_O)); 3534 } 3535 3536 void createX86Lahf(MCInst &Inst) const { 3537 Inst.setOpcode(X86::LAHF); 3538 Inst.clear(); 3539 } 3540 3541 void createX86Sahf(MCInst &Inst) const { 3542 Inst.setOpcode(X86::SAHF); 3543 Inst.clear(); 3544 } 3545 3546 void createInstrIncMemory(InstructionListType &Instrs, const MCSymbol *Target, 3547 MCContext *Ctx, bool IsLeaf) const override { 3548 unsigned int I = 0; 3549 3550 Instrs.resize(IsLeaf ? 13 : 11); 3551 // Don't clobber application red zone (ABI dependent) 3552 if (IsLeaf) 3553 createStackPointerIncrement(Instrs[I++], 128, 3554 /*NoFlagsClobber=*/true); 3555 3556 // Performance improvements based on the optimization discussed at 3557 // https://reviews.llvm.org/D6629 3558 // LAHF/SAHF are used instead of PUSHF/POPF 3559 // PUSHF 3560 createPushRegister(Instrs[I++], X86::RAX, 8); 3561 createClearRegWithNoEFlagsUpdate(Instrs[I++], X86::RAX, 8); 3562 createX86Lahf(Instrs[I++]); 3563 createPushRegister(Instrs[I++], X86::RAX, 8); 3564 createClearRegWithNoEFlagsUpdate(Instrs[I++], X86::RAX, 8); 3565 createX86SaveOVFlagToRegister(Instrs[I++], X86::AL); 3566 // LOCK INC 3567 createIncMemory(Instrs[I++], Target, Ctx); 3568 // POPF 3569 createAddRegImm(Instrs[I++], X86::AL, 127, 1); 3570 createPopRegister(Instrs[I++], X86::RAX, 8); 3571 createX86Sahf(Instrs[I++]); 3572 createPopRegister(Instrs[I++], X86::RAX, 8); 3573 3574 if (IsLeaf) 3575 createStackPointerDecrement(Instrs[I], 128, 3576 /*NoFlagsClobber=*/true); 3577 } 3578 3579 void createSwap(MCInst &Inst, MCPhysReg Source, MCPhysReg MemBaseReg, 3580 int64_t Disp) const { 3581 Inst.setOpcode(X86::XCHG64rm); 3582 Inst.addOperand(MCOperand::createReg(Source)); 3583 Inst.addOperand(MCOperand::createReg(Source)); 3584 Inst.addOperand(MCOperand::createReg(MemBaseReg)); // BaseReg 3585 Inst.addOperand(MCOperand::createImm(1)); // ScaleAmt 3586 Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // IndexReg 3587 Inst.addOperand(MCOperand::createImm(Disp)); // Displacement 3588 Inst.addOperand(MCOperand::createReg(X86::NoRegister));//AddrSegmentReg 3589 } 3590 3591 void createIndirectBranch(MCInst &Inst, MCPhysReg MemBaseReg, 3592 int64_t Disp) const { 3593 Inst.setOpcode(X86::JMP64m); 3594 Inst.addOperand(MCOperand::createReg(MemBaseReg)); // BaseReg 3595 Inst.addOperand(MCOperand::createImm(1)); // ScaleAmt 3596 Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // IndexReg 3597 Inst.addOperand(MCOperand::createImm(Disp)); // Displacement 3598 Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // AddrSegmentReg 3599 } 3600 3601 InstructionListType createInstrumentedIndirectCall(const MCInst &CallInst, 3602 bool TailCall, 3603 MCSymbol *HandlerFuncAddr, 3604 int CallSiteID, 3605 MCContext *Ctx) override { 3606 // Check if the target address expression used in the original indirect call 3607 // uses the stack pointer, which we are going to clobber. 3608 static BitVector SPAliases(getAliases(X86::RSP)); 3609 bool UsesSP = false; 3610 // Skip defs. 3611 for (unsigned I = Info->get(CallInst.getOpcode()).getNumDefs(), 3612 E = MCPlus::getNumPrimeOperands(CallInst); I != E; ++I) { 3613 const MCOperand &Operand = CallInst.getOperand(I); 3614 if (Operand.isReg() && SPAliases[Operand.getReg()]) { 3615 UsesSP = true; 3616 break; 3617 } 3618 } 3619 3620 InstructionListType Insts; 3621 MCPhysReg TempReg = getIntArgRegister(0); 3622 // Code sequence used to enter indirect call instrumentation helper: 3623 // push %rdi 3624 // add $8, %rsp ;; $rsp may be used in target, so fix it to prev val 3625 // movq target, %rdi ;; via convertIndirectCallTargetToLoad 3626 // sub $8, %rsp ;; restore correct stack value 3627 // push %rdi 3628 // movq $CallSiteID, %rdi 3629 // push %rdi 3630 // callq/jmp HandlerFuncAddr 3631 Insts.emplace_back(); 3632 createPushRegister(Insts.back(), TempReg, 8); 3633 if (UsesSP) { // Only adjust SP if we really need to 3634 Insts.emplace_back(); 3635 createStackPointerDecrement(Insts.back(), 8, /*NoFlagsClobber=*/false); 3636 } 3637 Insts.emplace_back(CallInst); 3638 // Insts.back() and CallInst now share the same annotation instruction. 3639 // Strip it from Insts.back(), only preserving tail call annotation. 3640 stripAnnotations(Insts.back(), /*KeepTC=*/true); 3641 convertIndirectCallToLoad(Insts.back(), TempReg); 3642 if (UsesSP) { 3643 Insts.emplace_back(); 3644 createStackPointerIncrement(Insts.back(), 8, /*NoFlagsClobber=*/false); 3645 } 3646 Insts.emplace_back(); 3647 createPushRegister(Insts.back(), TempReg, 8); 3648 Insts.emplace_back(); 3649 createLoadImmediate(Insts.back(), TempReg, CallSiteID); 3650 Insts.emplace_back(); 3651 createPushRegister(Insts.back(), TempReg, 8); 3652 Insts.emplace_back(); 3653 createDirectCall(Insts.back(), HandlerFuncAddr, Ctx, 3654 /*TailCall=*/TailCall); 3655 // Carry over metadata 3656 for (int I = MCPlus::getNumPrimeOperands(CallInst), 3657 E = CallInst.getNumOperands(); 3658 I != E; ++I) { 3659 Insts.back().addOperand(CallInst.getOperand(I)); 3660 } 3661 return Insts; 3662 } 3663 3664 InstructionListType createInstrumentedIndCallHandlerExitBB() const override { 3665 const MCPhysReg TempReg = getIntArgRegister(0); 3666 // We just need to undo the sequence created for every ind call in 3667 // instrumentIndirectTarget(), which can be accomplished minimally with: 3668 // popfq 3669 // pop %rdi 3670 // add $16, %rsp 3671 // xchg (%rsp), %rdi 3672 // jmp *-8(%rsp) 3673 InstructionListType Insts(5); 3674 createPopFlags(Insts[0], 8); 3675 createPopRegister(Insts[1], TempReg, 8); 3676 createStackPointerDecrement(Insts[2], 16, /*NoFlagsClobber=*/false); 3677 createSwap(Insts[3], TempReg, X86::RSP, 0); 3678 createIndirectBranch(Insts[4], X86::RSP, -8); 3679 return Insts; 3680 } 3681 3682 InstructionListType 3683 createInstrumentedIndTailCallHandlerExitBB() const override { 3684 const MCPhysReg TempReg = getIntArgRegister(0); 3685 // Same thing as above, but for tail calls 3686 // popfq 3687 // add $16, %rsp 3688 // pop %rdi 3689 // jmp *-16(%rsp) 3690 InstructionListType Insts(4); 3691 createPopFlags(Insts[0], 8); 3692 createStackPointerDecrement(Insts[1], 16, /*NoFlagsClobber=*/false); 3693 createPopRegister(Insts[2], TempReg, 8); 3694 createIndirectBranch(Insts[3], X86::RSP, -16); 3695 return Insts; 3696 } 3697 3698 InstructionListType 3699 createInstrumentedIndCallHandlerEntryBB(const MCSymbol *InstrTrampoline, 3700 const MCSymbol *IndCallHandler, 3701 MCContext *Ctx) override { 3702 const MCPhysReg TempReg = getIntArgRegister(0); 3703 // Code sequence used to check whether InstrTampoline was initialized 3704 // and call it if so, returns via IndCallHandler. 3705 // pushfq 3706 // mov InstrTrampoline,%rdi 3707 // cmp $0x0,%rdi 3708 // je IndCallHandler 3709 // callq *%rdi 3710 // jmpq IndCallHandler 3711 InstructionListType Insts; 3712 Insts.emplace_back(); 3713 createPushFlags(Insts.back(), 8); 3714 Insts.emplace_back(); 3715 createMove(Insts.back(), InstrTrampoline, TempReg, Ctx); 3716 InstructionListType cmpJmp = createCmpJE(TempReg, 0, IndCallHandler, Ctx); 3717 Insts.insert(Insts.end(), cmpJmp.begin(), cmpJmp.end()); 3718 Insts.emplace_back(); 3719 Insts.back().setOpcode(X86::CALL64r); 3720 Insts.back().addOperand(MCOperand::createReg(TempReg)); 3721 Insts.emplace_back(); 3722 createDirectCall(Insts.back(), IndCallHandler, Ctx, /*IsTailCall*/ true); 3723 return Insts; 3724 } 3725 3726 InstructionListType createNumCountersGetter(MCContext *Ctx) const override { 3727 InstructionListType Insts(2); 3728 MCSymbol *NumLocs = Ctx->getOrCreateSymbol("__bolt_num_counters"); 3729 createMove(Insts[0], NumLocs, X86::EAX, Ctx); 3730 createReturn(Insts[1]); 3731 return Insts; 3732 } 3733 3734 InstructionListType 3735 createInstrLocationsGetter(MCContext *Ctx) const override { 3736 InstructionListType Insts(2); 3737 MCSymbol *Locs = Ctx->getOrCreateSymbol("__bolt_instr_locations"); 3738 createLea(Insts[0], Locs, X86::EAX, Ctx); 3739 createReturn(Insts[1]); 3740 return Insts; 3741 } 3742 3743 InstructionListType createInstrTablesGetter(MCContext *Ctx) const override { 3744 InstructionListType Insts(2); 3745 MCSymbol *Locs = Ctx->getOrCreateSymbol("__bolt_instr_tables"); 3746 createLea(Insts[0], Locs, X86::EAX, Ctx); 3747 createReturn(Insts[1]); 3748 return Insts; 3749 } 3750 3751 InstructionListType createInstrNumFuncsGetter(MCContext *Ctx) const override { 3752 InstructionListType Insts(2); 3753 MCSymbol *NumFuncs = Ctx->getOrCreateSymbol("__bolt_instr_num_funcs"); 3754 createMove(Insts[0], NumFuncs, X86::EAX, Ctx); 3755 createReturn(Insts[1]); 3756 return Insts; 3757 } 3758 3759 InstructionListType createSymbolTrampoline(const MCSymbol *TgtSym, 3760 MCContext *Ctx) const override { 3761 InstructionListType Insts(1); 3762 createUncondBranch(Insts[0], TgtSym, Ctx); 3763 return Insts; 3764 } 3765 3766 InstructionListType createDummyReturnFunction(MCContext *Ctx) const override { 3767 InstructionListType Insts(1); 3768 createReturn(Insts[0]); 3769 return Insts; 3770 } 3771 3772 BlocksVectorTy indirectCallPromotion( 3773 const MCInst &CallInst, 3774 const std::vector<std::pair<MCSymbol *, uint64_t>> &Targets, 3775 const std::vector<std::pair<MCSymbol *, uint64_t>> &VtableSyms, 3776 const std::vector<MCInst *> &MethodFetchInsns, 3777 const bool MinimizeCodeSize, 3778 MCContext *Ctx 3779 ) override { 3780 const bool IsTailCall = isTailCall(CallInst); 3781 const bool IsJumpTable = getJumpTable(CallInst) != 0; 3782 BlocksVectorTy Results; 3783 3784 // Label for the current code block. 3785 MCSymbol *NextTarget = nullptr; 3786 3787 // The join block which contains all the instructions following CallInst. 3788 // MergeBlock remains null if CallInst is a tail call. 3789 MCSymbol *MergeBlock = nullptr; 3790 3791 unsigned FuncAddrReg = X86::R10; 3792 3793 const bool LoadElim = !VtableSyms.empty(); 3794 assert((!LoadElim || VtableSyms.size() == Targets.size()) && 3795 "There must be a vtable entry for every method " 3796 "in the targets vector."); 3797 3798 if (MinimizeCodeSize && !LoadElim) { 3799 std::set<unsigned> UsedRegs; 3800 3801 for (unsigned int I = 0; I < MCPlus::getNumPrimeOperands(CallInst); ++I) { 3802 const MCOperand &Op = CallInst.getOperand(I); 3803 if (Op.isReg()) { 3804 UsedRegs.insert(Op.getReg()); 3805 } 3806 } 3807 3808 if (UsedRegs.count(X86::R10) == 0) 3809 FuncAddrReg = X86::R10; 3810 else if (UsedRegs.count(X86::R11) == 0) 3811 FuncAddrReg = X86::R11; 3812 else 3813 return Results; 3814 } 3815 3816 const auto jumpToMergeBlock = [&](InstructionListType &NewCall) { 3817 assert(MergeBlock); 3818 NewCall.push_back(CallInst); 3819 MCInst &Merge = NewCall.back(); 3820 Merge.clear(); 3821 createUncondBranch(Merge, MergeBlock, Ctx); 3822 }; 3823 3824 for (unsigned int i = 0; i < Targets.size(); ++i) { 3825 Results.emplace_back(NextTarget, InstructionListType()); 3826 InstructionListType *NewCall = &Results.back().second; 3827 3828 if (MinimizeCodeSize && !LoadElim) { 3829 // Load the call target into FuncAddrReg. 3830 NewCall->push_back(CallInst); // Copy CallInst in order to get SMLoc 3831 MCInst &Target = NewCall->back(); 3832 Target.clear(); 3833 Target.setOpcode(X86::MOV64ri32); 3834 Target.addOperand(MCOperand::createReg(FuncAddrReg)); 3835 if (Targets[i].first) { 3836 // Is this OK? 3837 Target.addOperand( 3838 MCOperand::createExpr( 3839 MCSymbolRefExpr::create(Targets[i].first, 3840 MCSymbolRefExpr::VK_None, 3841 *Ctx))); 3842 } else { 3843 const uint64_t Addr = Targets[i].second; 3844 // Immediate address is out of sign extended 32 bit range. 3845 if (int64_t(Addr) != int64_t(int32_t(Addr))) { 3846 return BlocksVectorTy(); 3847 } 3848 Target.addOperand(MCOperand::createImm(Addr)); 3849 } 3850 3851 // Compare current call target to a specific address. 3852 NewCall->push_back(CallInst); 3853 MCInst &Compare = NewCall->back(); 3854 Compare.clear(); 3855 if (isBranchOnReg(CallInst)) { 3856 Compare.setOpcode(X86::CMP64rr); 3857 } else if (CallInst.getOpcode() == X86::CALL64pcrel32) { 3858 Compare.setOpcode(X86::CMP64ri32); 3859 } else { 3860 Compare.setOpcode(X86::CMP64rm); 3861 } 3862 Compare.addOperand(MCOperand::createReg(FuncAddrReg)); 3863 3864 // TODO: Would be preferable to only load this value once. 3865 for (unsigned i = 0; 3866 i < Info->get(CallInst.getOpcode()).getNumOperands(); 3867 ++i) { 3868 if (!CallInst.getOperand(i).isInst()) 3869 Compare.addOperand(CallInst.getOperand(i)); 3870 } 3871 } else { 3872 // Compare current call target to a specific address. 3873 NewCall->push_back(CallInst); 3874 MCInst &Compare = NewCall->back(); 3875 Compare.clear(); 3876 if (isBranchOnReg(CallInst)) { 3877 Compare.setOpcode(X86::CMP64ri32); 3878 } else { 3879 Compare.setOpcode(X86::CMP64mi32); 3880 } 3881 3882 // Original call address. 3883 for (unsigned i = 0; 3884 i < Info->get(CallInst.getOpcode()).getNumOperands(); 3885 ++i) { 3886 if (!CallInst.getOperand(i).isInst()) 3887 Compare.addOperand(CallInst.getOperand(i)); 3888 } 3889 3890 // Target address. 3891 if (Targets[i].first || LoadElim) { 3892 const MCSymbol *Sym = 3893 LoadElim ? VtableSyms[i].first : Targets[i].first; 3894 const uint64_t Addend = LoadElim ? VtableSyms[i].second : 0; 3895 3896 const MCExpr *Expr = MCSymbolRefExpr::create(Sym, *Ctx); 3897 3898 if (Addend) { 3899 Expr = MCBinaryExpr::createAdd(Expr, 3900 MCConstantExpr::create(Addend, *Ctx), 3901 *Ctx); 3902 } 3903 3904 Compare.addOperand(MCOperand::createExpr(Expr)); 3905 } else { 3906 const uint64_t Addr = Targets[i].second; 3907 // Immediate address is out of sign extended 32 bit range. 3908 if (int64_t(Addr) != int64_t(int32_t(Addr))) { 3909 return BlocksVectorTy(); 3910 } 3911 Compare.addOperand(MCOperand::createImm(Addr)); 3912 } 3913 } 3914 3915 // jump to next target compare. 3916 NextTarget = 3917 Ctx->createNamedTempSymbol(); // generate label for the next block 3918 NewCall->push_back(CallInst); 3919 3920 if (IsJumpTable) { 3921 MCInst &Je = NewCall->back(); 3922 3923 // Jump to next compare if target addresses don't match. 3924 Je.clear(); 3925 Je.setOpcode(X86::JCC_1); 3926 if (Targets[i].first) { 3927 Je.addOperand(MCOperand::createExpr( 3928 MCSymbolRefExpr::create(Targets[i].first, 3929 MCSymbolRefExpr::VK_None, 3930 *Ctx))); 3931 } else { 3932 Je.addOperand(MCOperand::createImm(Targets[i].second)); 3933 } 3934 Je.addOperand(MCOperand::createImm(X86::COND_E)); 3935 assert(!isInvoke(CallInst)); 3936 } else { 3937 MCInst &Jne = NewCall->back(); 3938 3939 // Jump to next compare if target addresses don't match. 3940 Jne.clear(); 3941 Jne.setOpcode(X86::JCC_1); 3942 Jne.addOperand(MCOperand::createExpr(MCSymbolRefExpr::create( 3943 NextTarget, MCSymbolRefExpr::VK_None, *Ctx))); 3944 Jne.addOperand(MCOperand::createImm(X86::COND_NE)); 3945 3946 // Call specific target directly. 3947 Results.emplace_back(Ctx->createNamedTempSymbol(), 3948 InstructionListType()); 3949 NewCall = &Results.back().second; 3950 NewCall->push_back(CallInst); 3951 MCInst &CallOrJmp = NewCall->back(); 3952 3953 CallOrJmp.clear(); 3954 3955 if (MinimizeCodeSize && !LoadElim) { 3956 CallOrJmp.setOpcode(IsTailCall ? X86::JMP32r : X86::CALL64r); 3957 CallOrJmp.addOperand(MCOperand::createReg(FuncAddrReg)); 3958 } else { 3959 CallOrJmp.setOpcode(IsTailCall ? X86::JMP_4 : X86::CALL64pcrel32); 3960 3961 if (Targets[i].first) { 3962 CallOrJmp.addOperand(MCOperand::createExpr(MCSymbolRefExpr::create( 3963 Targets[i].first, MCSymbolRefExpr::VK_None, *Ctx))); 3964 } else { 3965 CallOrJmp.addOperand(MCOperand::createImm(Targets[i].second)); 3966 } 3967 } 3968 if (IsTailCall) 3969 setTailCall(CallOrJmp); 3970 3971 if (CallOrJmp.getOpcode() == X86::CALL64r || 3972 CallOrJmp.getOpcode() == X86::CALL64pcrel32) { 3973 if (hasAnnotation(CallInst, "Offset")) 3974 // Annotated as duplicated call 3975 addAnnotation(CallOrJmp, "Offset", 3976 getAnnotationAs<uint32_t>(CallInst, "Offset")); 3977 } 3978 3979 if (isInvoke(CallInst) && !isInvoke(CallOrJmp)) { 3980 // Copy over any EH or GNU args size information from the original 3981 // call. 3982 Optional<MCPlus::MCLandingPad> EHInfo = getEHInfo(CallInst); 3983 if (EHInfo) 3984 addEHInfo(CallOrJmp, *EHInfo); 3985 int64_t GnuArgsSize = getGnuArgsSize(CallInst); 3986 if (GnuArgsSize >= 0) 3987 addGnuArgsSize(CallOrJmp, GnuArgsSize); 3988 } 3989 3990 if (!IsTailCall) { 3991 // The fallthrough block for the most common target should be 3992 // the merge block. 3993 if (i == 0) { 3994 // Fallthrough to merge block. 3995 MergeBlock = Ctx->createNamedTempSymbol(); 3996 } else { 3997 // Insert jump to the merge block if we are not doing a fallthrough. 3998 jumpToMergeBlock(*NewCall); 3999 } 4000 } 4001 } 4002 } 4003 4004 // Cold call block. 4005 Results.emplace_back(NextTarget, InstructionListType()); 4006 InstructionListType &NewCall = Results.back().second; 4007 for (const MCInst *Inst : MethodFetchInsns) { 4008 if (Inst != &CallInst) 4009 NewCall.push_back(*Inst); 4010 } 4011 NewCall.push_back(CallInst); 4012 4013 // Jump to merge block from cold call block 4014 if (!IsTailCall && !IsJumpTable) { 4015 jumpToMergeBlock(NewCall); 4016 4017 // Record merge block 4018 Results.emplace_back(MergeBlock, InstructionListType()); 4019 } 4020 4021 return Results; 4022 } 4023 4024 BlocksVectorTy jumpTablePromotion( 4025 const MCInst &IJmpInst, 4026 const std::vector<std::pair<MCSymbol *,uint64_t>> &Targets, 4027 const std::vector<MCInst *> &TargetFetchInsns, 4028 MCContext *Ctx 4029 ) const override { 4030 assert(getJumpTable(IJmpInst) != 0); 4031 uint16_t IndexReg = getAnnotationAs<uint16_t>(IJmpInst, "JTIndexReg"); 4032 if (IndexReg == 0) 4033 return BlocksVectorTy(); 4034 4035 BlocksVectorTy Results; 4036 4037 // Label for the current code block. 4038 MCSymbol *NextTarget = nullptr; 4039 4040 for (unsigned int i = 0; i < Targets.size(); ++i) { 4041 Results.emplace_back(NextTarget, InstructionListType()); 4042 InstructionListType *CurBB = &Results.back().second; 4043 4044 // Compare current index to a specific index. 4045 CurBB->emplace_back(MCInst()); 4046 MCInst &CompareInst = CurBB->back(); 4047 CompareInst.setLoc(IJmpInst.getLoc()); 4048 CompareInst.setOpcode(X86::CMP64ri32); 4049 CompareInst.addOperand(MCOperand::createReg(IndexReg)); 4050 4051 const uint64_t CaseIdx = Targets[i].second; 4052 // Immediate address is out of sign extended 32 bit range. 4053 if (int64_t(CaseIdx) != int64_t(int32_t(CaseIdx))) { 4054 return BlocksVectorTy(); 4055 } 4056 CompareInst.addOperand(MCOperand::createImm(CaseIdx)); 4057 shortenInstruction(CompareInst); 4058 4059 // jump to next target compare. 4060 NextTarget = 4061 Ctx->createNamedTempSymbol(); // generate label for the next block 4062 CurBB->push_back(MCInst()); 4063 4064 MCInst &JEInst = CurBB->back(); 4065 JEInst.setLoc(IJmpInst.getLoc()); 4066 4067 // Jump to target if indices match 4068 JEInst.setOpcode(X86::JCC_1); 4069 JEInst.addOperand(MCOperand::createExpr(MCSymbolRefExpr::create( 4070 Targets[i].first, MCSymbolRefExpr::VK_None, *Ctx))); 4071 JEInst.addOperand(MCOperand::createImm(X86::COND_E)); 4072 } 4073 4074 // Cold call block. 4075 Results.emplace_back(NextTarget, InstructionListType()); 4076 InstructionListType &CurBB = Results.back().second; 4077 for (const MCInst *Inst : TargetFetchInsns) { 4078 if (Inst != &IJmpInst) 4079 CurBB.push_back(*Inst); 4080 } 4081 CurBB.push_back(IJmpInst); 4082 4083 return Results; 4084 } 4085 4086 private: 4087 4088 bool createMove(MCInst &Inst, const MCSymbol *Src, unsigned Reg, 4089 MCContext *Ctx) const { 4090 Inst.setOpcode(X86::MOV64rm); 4091 Inst.addOperand(MCOperand::createReg(Reg)); 4092 Inst.addOperand(MCOperand::createReg(X86::RIP)); // BaseReg 4093 Inst.addOperand(MCOperand::createImm(1)); // ScaleAmt 4094 Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // IndexReg 4095 Inst.addOperand(MCOperand::createExpr( 4096 MCSymbolRefExpr::create(Src, MCSymbolRefExpr::VK_None, 4097 *Ctx))); // Displacement 4098 Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // AddrSegmentReg 4099 4100 return true; 4101 } 4102 4103 bool createLea(MCInst &Inst, const MCSymbol *Src, unsigned Reg, 4104 MCContext *Ctx) const { 4105 Inst.setOpcode(X86::LEA64r); 4106 Inst.addOperand(MCOperand::createReg(Reg)); 4107 Inst.addOperand(MCOperand::createReg(X86::RIP)); // BaseReg 4108 Inst.addOperand(MCOperand::createImm(1)); // ScaleAmt 4109 Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // IndexReg 4110 Inst.addOperand(MCOperand::createExpr( 4111 MCSymbolRefExpr::create(Src, MCSymbolRefExpr::VK_None, 4112 *Ctx))); // Displacement 4113 Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // AddrSegmentReg 4114 return true; 4115 } 4116 }; 4117 4118 } 4119 4120 namespace llvm { 4121 namespace bolt { 4122 4123 MCPlusBuilder *createX86MCPlusBuilder(const MCInstrAnalysis *Analysis, 4124 const MCInstrInfo *Info, 4125 const MCRegisterInfo *RegInfo) { 4126 return new X86MCPlusBuilder(Analysis, Info, RegInfo); 4127 } 4128 4129 } 4130 } 4131