1 //===- bolt/Target/X86/X86MCPlusBuilder.cpp -------------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file provides X86-specific MCPlus builder. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "MCTargetDesc/X86BaseInfo.h" 14 #include "MCTargetDesc/X86MCTargetDesc.h" 15 #include "bolt/Core/MCPlusBuilder.h" 16 #include "llvm/MC/MCContext.h" 17 #include "llvm/MC/MCFixupKindInfo.h" 18 #include "llvm/MC/MCInstBuilder.h" 19 #include "llvm/MC/MCInstrInfo.h" 20 #include "llvm/MC/MCRegisterInfo.h" 21 #include "llvm/Support/DataExtractor.h" 22 #include "llvm/Support/Debug.h" 23 #include "llvm/Support/Errc.h" 24 #include "llvm/Support/ErrorHandling.h" 25 #include "llvm/Support/ErrorOr.h" 26 #include <set> 27 28 #define DEBUG_TYPE "mcplus" 29 30 using namespace llvm; 31 using namespace bolt; 32 33 namespace { 34 35 unsigned getShortBranchOpcode(unsigned Opcode) { 36 switch (Opcode) { 37 default: 38 return Opcode; 39 case X86::JMP_2: return X86::JMP_1; 40 case X86::JMP_4: return X86::JMP_1; 41 case X86::JCC_2: return X86::JCC_1; 42 case X86::JCC_4: return X86::JCC_1; 43 } 44 } 45 46 unsigned getShortArithOpcode(unsigned Opcode) { 47 switch (Opcode) { 48 default: 49 return Opcode; 50 51 // IMUL 52 case X86::IMUL16rri: return X86::IMUL16rri8; 53 case X86::IMUL16rmi: return X86::IMUL16rmi8; 54 case X86::IMUL32rri: return X86::IMUL32rri8; 55 case X86::IMUL32rmi: return X86::IMUL32rmi8; 56 case X86::IMUL64rri32: return X86::IMUL64rri8; 57 case X86::IMUL64rmi32: return X86::IMUL64rmi8; 58 59 // OR 60 case X86::OR16ri: return X86::OR16ri8; 61 case X86::OR16mi: return X86::OR16mi8; 62 case X86::OR32ri: return X86::OR32ri8; 63 case X86::OR32mi: return X86::OR32mi8; 64 case X86::OR64ri32: return X86::OR64ri8; 65 case X86::OR64mi32: return X86::OR64mi8; 66 67 // AND 68 case X86::AND16ri: return X86::AND16ri8; 69 case X86::AND16mi: return X86::AND16mi8; 70 case X86::AND32ri: return X86::AND32ri8; 71 case X86::AND32mi: return X86::AND32mi8; 72 case X86::AND64ri32: return X86::AND64ri8; 73 case X86::AND64mi32: return X86::AND64mi8; 74 75 // XOR 76 case X86::XOR16ri: return X86::XOR16ri8; 77 case X86::XOR16mi: return X86::XOR16mi8; 78 case X86::XOR32ri: return X86::XOR32ri8; 79 case X86::XOR32mi: return X86::XOR32mi8; 80 case X86::XOR64ri32: return X86::XOR64ri8; 81 case X86::XOR64mi32: return X86::XOR64mi8; 82 83 // ADD 84 case X86::ADD16ri: return X86::ADD16ri8; 85 case X86::ADD16mi: return X86::ADD16mi8; 86 case X86::ADD32ri: return X86::ADD32ri8; 87 case X86::ADD32mi: return X86::ADD32mi8; 88 case X86::ADD64ri32: return X86::ADD64ri8; 89 case X86::ADD64mi32: return X86::ADD64mi8; 90 91 // SUB 92 case X86::SUB16ri: return X86::SUB16ri8; 93 case X86::SUB16mi: return X86::SUB16mi8; 94 case X86::SUB32ri: return X86::SUB32ri8; 95 case X86::SUB32mi: return X86::SUB32mi8; 96 case X86::SUB64ri32: return X86::SUB64ri8; 97 case X86::SUB64mi32: return X86::SUB64mi8; 98 99 // CMP 100 case X86::CMP16ri: return X86::CMP16ri8; 101 case X86::CMP16mi: return X86::CMP16mi8; 102 case X86::CMP32ri: return X86::CMP32ri8; 103 case X86::CMP32mi: return X86::CMP32mi8; 104 case X86::CMP64ri32: return X86::CMP64ri8; 105 case X86::CMP64mi32: return X86::CMP64mi8; 106 107 // PUSH 108 case X86::PUSHi32: return X86::PUSH32i8; 109 case X86::PUSHi16: return X86::PUSH16i8; 110 case X86::PUSH64i32: return X86::PUSH64i8; 111 } 112 } 113 114 bool isADD(unsigned Opcode) { 115 switch (Opcode) { 116 default: 117 return false; 118 case X86::ADD16i16: 119 case X86::ADD16mi: 120 case X86::ADD16mi8: 121 case X86::ADD16mr: 122 case X86::ADD16ri: 123 case X86::ADD16ri8: 124 case X86::ADD16ri8_DB: 125 case X86::ADD16ri_DB: 126 case X86::ADD16rm: 127 case X86::ADD16rr: 128 case X86::ADD16rr_DB: 129 case X86::ADD16rr_REV: 130 case X86::ADD32i32: 131 case X86::ADD32mi: 132 case X86::ADD32mi8: 133 case X86::ADD32mr: 134 case X86::ADD32ri: 135 case X86::ADD32ri8: 136 case X86::ADD32ri8_DB: 137 case X86::ADD32ri_DB: 138 case X86::ADD32rm: 139 case X86::ADD32rr: 140 case X86::ADD32rr_DB: 141 case X86::ADD32rr_REV: 142 case X86::ADD64i32: 143 case X86::ADD64mi32: 144 case X86::ADD64mi8: 145 case X86::ADD64mr: 146 case X86::ADD64ri32: 147 case X86::ADD64ri32_DB: 148 case X86::ADD64ri8: 149 case X86::ADD64ri8_DB: 150 case X86::ADD64rm: 151 case X86::ADD64rr: 152 case X86::ADD64rr_DB: 153 case X86::ADD64rr_REV: 154 case X86::ADD8i8: 155 case X86::ADD8mi: 156 case X86::ADD8mi8: 157 case X86::ADD8mr: 158 case X86::ADD8ri: 159 case X86::ADD8ri8: 160 case X86::ADD8rm: 161 case X86::ADD8rr: 162 case X86::ADD8rr_REV: 163 return true; 164 } 165 } 166 167 bool isAND(unsigned Opcode) { 168 switch (Opcode) { 169 default: 170 return false; 171 case X86::AND16i16: 172 case X86::AND16mi: 173 case X86::AND16mi8: 174 case X86::AND16mr: 175 case X86::AND16ri: 176 case X86::AND16ri8: 177 case X86::AND16rm: 178 case X86::AND16rr: 179 case X86::AND16rr_REV: 180 case X86::AND32i32: 181 case X86::AND32mi: 182 case X86::AND32mi8: 183 case X86::AND32mr: 184 case X86::AND32ri: 185 case X86::AND32ri8: 186 case X86::AND32rm: 187 case X86::AND32rr: 188 case X86::AND32rr_REV: 189 case X86::AND64i32: 190 case X86::AND64mi32: 191 case X86::AND64mi8: 192 case X86::AND64mr: 193 case X86::AND64ri32: 194 case X86::AND64ri8: 195 case X86::AND64rm: 196 case X86::AND64rr: 197 case X86::AND64rr_REV: 198 case X86::AND8i8: 199 case X86::AND8mi: 200 case X86::AND8mi8: 201 case X86::AND8mr: 202 case X86::AND8ri: 203 case X86::AND8ri8: 204 case X86::AND8rm: 205 case X86::AND8rr: 206 case X86::AND8rr_REV: 207 return true; 208 } 209 } 210 211 bool isCMP(unsigned Opcode) { 212 switch (Opcode) { 213 default: 214 return false; 215 case X86::CMP16i16: 216 case X86::CMP16mi: 217 case X86::CMP16mi8: 218 case X86::CMP16mr: 219 case X86::CMP16ri: 220 case X86::CMP16ri8: 221 case X86::CMP16rm: 222 case X86::CMP16rr: 223 case X86::CMP16rr_REV: 224 case X86::CMP32i32: 225 case X86::CMP32mi: 226 case X86::CMP32mi8: 227 case X86::CMP32mr: 228 case X86::CMP32ri: 229 case X86::CMP32ri8: 230 case X86::CMP32rm: 231 case X86::CMP32rr: 232 case X86::CMP32rr_REV: 233 case X86::CMP64i32: 234 case X86::CMP64mi32: 235 case X86::CMP64mi8: 236 case X86::CMP64mr: 237 case X86::CMP64ri32: 238 case X86::CMP64ri8: 239 case X86::CMP64rm: 240 case X86::CMP64rr: 241 case X86::CMP64rr_REV: 242 case X86::CMP8i8: 243 case X86::CMP8mi: 244 case X86::CMP8mi8: 245 case X86::CMP8mr: 246 case X86::CMP8ri: 247 case X86::CMP8ri8: 248 case X86::CMP8rm: 249 case X86::CMP8rr: 250 case X86::CMP8rr_REV: 251 return true; 252 } 253 } 254 255 bool isDEC(unsigned Opcode) { 256 switch (Opcode) { 257 default: 258 return false; 259 case X86::DEC16m: 260 case X86::DEC16r: 261 case X86::DEC16r_alt: 262 case X86::DEC32m: 263 case X86::DEC32r: 264 case X86::DEC32r_alt: 265 case X86::DEC64r: 266 case X86::DEC64m: 267 case X86::DEC8m: 268 case X86::DEC8r: 269 return true; 270 } 271 } 272 273 bool isINC(unsigned Opcode) { 274 switch (Opcode) { 275 default: 276 return false; 277 case X86::INC16m: 278 case X86::INC16r: 279 case X86::INC16r_alt: 280 case X86::INC32m: 281 case X86::INC32r: 282 case X86::INC32r_alt: 283 case X86::INC64r: 284 case X86::INC64m: 285 case X86::INC8m: 286 case X86::INC8r: 287 return true; 288 } 289 } 290 291 bool isSUB(unsigned Opcode) { 292 switch (Opcode) { 293 default: 294 return false; 295 case X86::SUB16i16: 296 case X86::SUB16mi: 297 case X86::SUB16mi8: 298 case X86::SUB16mr: 299 case X86::SUB16ri: 300 case X86::SUB16ri8: 301 case X86::SUB16rm: 302 case X86::SUB16rr: 303 case X86::SUB16rr_REV: 304 case X86::SUB32i32: 305 case X86::SUB32mi: 306 case X86::SUB32mi8: 307 case X86::SUB32mr: 308 case X86::SUB32ri: 309 case X86::SUB32ri8: 310 case X86::SUB32rm: 311 case X86::SUB32rr: 312 case X86::SUB32rr_REV: 313 case X86::SUB64i32: 314 case X86::SUB64mi32: 315 case X86::SUB64mi8: 316 case X86::SUB64mr: 317 case X86::SUB64ri32: 318 case X86::SUB64ri8: 319 case X86::SUB64rm: 320 case X86::SUB64rr: 321 case X86::SUB64rr_REV: 322 case X86::SUB8i8: 323 case X86::SUB8mi: 324 case X86::SUB8mi8: 325 case X86::SUB8mr: 326 case X86::SUB8ri: 327 case X86::SUB8ri8: 328 case X86::SUB8rm: 329 case X86::SUB8rr: 330 case X86::SUB8rr_REV: 331 return true; 332 } 333 } 334 335 bool isTEST(unsigned Opcode) { 336 switch (Opcode) { 337 default: 338 return false; 339 case X86::TEST16i16: 340 case X86::TEST16mi: 341 case X86::TEST16mr: 342 case X86::TEST16ri: 343 case X86::TEST16rr: 344 case X86::TEST32i32: 345 case X86::TEST32mi: 346 case X86::TEST32mr: 347 case X86::TEST32ri: 348 case X86::TEST32rr: 349 case X86::TEST64i32: 350 case X86::TEST64mi32: 351 case X86::TEST64mr: 352 case X86::TEST64ri32: 353 case X86::TEST64rr: 354 case X86::TEST8i8: 355 case X86::TEST8mi: 356 case X86::TEST8mr: 357 case X86::TEST8ri: 358 case X86::TEST8rr: 359 return true; 360 } 361 } 362 363 class X86MCPlusBuilder : public MCPlusBuilder { 364 public: 365 X86MCPlusBuilder(const MCInstrAnalysis *Analysis, const MCInstrInfo *Info, 366 const MCRegisterInfo *RegInfo) 367 : MCPlusBuilder(Analysis, Info, RegInfo) {} 368 369 bool isBranch(const MCInst &Inst) const override { 370 return Analysis->isBranch(Inst) && !isTailCall(Inst); 371 } 372 373 bool isUnconditionalBranch(const MCInst &Inst) const override { 374 return Analysis->isUnconditionalBranch(Inst) && !isTailCall(Inst); 375 } 376 377 bool isNoop(const MCInst &Inst) const override { 378 switch (Inst.getOpcode()) { 379 case X86::NOOP: 380 case X86::NOOPL: 381 case X86::NOOPLr: 382 case X86::NOOPQ: 383 case X86::NOOPQr: 384 case X86::NOOPW: 385 case X86::NOOPWr: 386 return true; 387 } 388 return false; 389 } 390 391 unsigned getCondCode(const MCInst &Inst) const override { 392 switch (Inst.getOpcode()) { 393 default: 394 return X86::COND_INVALID; 395 case X86::JCC_1: 396 case X86::JCC_2: 397 case X86::JCC_4: 398 return Inst.getOperand(Info->get(Inst.getOpcode()).NumOperands - 1) 399 .getImm(); 400 } 401 } 402 403 unsigned getInvertedCondCode(unsigned CC) const override { 404 switch (CC) { 405 default: return X86::COND_INVALID; 406 case X86::COND_E: return X86::COND_NE; 407 case X86::COND_NE: return X86::COND_E; 408 case X86::COND_L: return X86::COND_GE; 409 case X86::COND_LE: return X86::COND_G; 410 case X86::COND_G: return X86::COND_LE; 411 case X86::COND_GE: return X86::COND_L; 412 case X86::COND_B: return X86::COND_AE; 413 case X86::COND_BE: return X86::COND_A; 414 case X86::COND_A: return X86::COND_BE; 415 case X86::COND_AE: return X86::COND_B; 416 case X86::COND_S: return X86::COND_NS; 417 case X86::COND_NS: return X86::COND_S; 418 case X86::COND_P: return X86::COND_NP; 419 case X86::COND_NP: return X86::COND_P; 420 case X86::COND_O: return X86::COND_NO; 421 case X86::COND_NO: return X86::COND_O; 422 } 423 } 424 425 unsigned getCondCodesLogicalOr(unsigned CC1, unsigned CC2) const override { 426 enum DecodedCondCode : uint8_t { 427 DCC_EQUAL = 0x1, 428 DCC_GREATER = 0x2, 429 DCC_LESSER = 0x4, 430 DCC_GREATER_OR_LESSER = 0x6, 431 DCC_UNSIGNED = 0x8, 432 DCC_SIGNED = 0x10, 433 DCC_INVALID = 0x20, 434 }; 435 436 auto decodeCondCode = [&](unsigned CC) -> uint8_t { 437 switch (CC) { 438 default: return DCC_INVALID; 439 case X86::COND_E: return DCC_EQUAL; 440 case X86::COND_NE: return DCC_GREATER | DCC_LESSER; 441 case X86::COND_L: return DCC_LESSER | DCC_SIGNED; 442 case X86::COND_LE: return DCC_EQUAL | DCC_LESSER | DCC_SIGNED; 443 case X86::COND_G: return DCC_GREATER | DCC_SIGNED; 444 case X86::COND_GE: return DCC_GREATER | DCC_EQUAL | DCC_SIGNED; 445 case X86::COND_B: return DCC_LESSER | DCC_UNSIGNED; 446 case X86::COND_BE: return DCC_EQUAL | DCC_LESSER | DCC_UNSIGNED; 447 case X86::COND_A: return DCC_GREATER | DCC_UNSIGNED; 448 case X86::COND_AE: return DCC_GREATER | DCC_EQUAL | DCC_UNSIGNED; 449 } 450 }; 451 452 uint8_t DCC = decodeCondCode(CC1) | decodeCondCode(CC2); 453 454 if (DCC & DCC_INVALID) 455 return X86::COND_INVALID; 456 457 if (DCC & DCC_SIGNED && DCC & DCC_UNSIGNED) 458 return X86::COND_INVALID; 459 460 switch (DCC) { 461 default: return X86::COND_INVALID; 462 case DCC_EQUAL | DCC_LESSER | DCC_SIGNED: return X86::COND_LE; 463 case DCC_EQUAL | DCC_LESSER | DCC_UNSIGNED: return X86::COND_BE; 464 case DCC_EQUAL | DCC_GREATER | DCC_SIGNED: return X86::COND_GE; 465 case DCC_EQUAL | DCC_GREATER | DCC_UNSIGNED: return X86::COND_AE; 466 case DCC_GREATER | DCC_LESSER | DCC_SIGNED: return X86::COND_NE; 467 case DCC_GREATER | DCC_LESSER | DCC_UNSIGNED: return X86::COND_NE; 468 case DCC_GREATER | DCC_LESSER: return X86::COND_NE; 469 case DCC_EQUAL | DCC_SIGNED: return X86::COND_E; 470 case DCC_EQUAL | DCC_UNSIGNED: return X86::COND_E; 471 case DCC_EQUAL: return X86::COND_E; 472 case DCC_LESSER | DCC_SIGNED: return X86::COND_L; 473 case DCC_LESSER | DCC_UNSIGNED: return X86::COND_B; 474 case DCC_GREATER | DCC_SIGNED: return X86::COND_G; 475 case DCC_GREATER | DCC_UNSIGNED: return X86::COND_A; 476 } 477 } 478 479 bool isValidCondCode(unsigned CC) const override { 480 return (CC != X86::COND_INVALID); 481 } 482 483 bool isBreakpoint(const MCInst &Inst) const override { 484 return Inst.getOpcode() == X86::INT3; 485 } 486 487 bool isPrefix(const MCInst &Inst) const override { 488 switch (Inst.getOpcode()) { 489 case X86::LOCK_PREFIX: 490 case X86::REPNE_PREFIX: 491 case X86::REP_PREFIX: 492 return true; 493 } 494 return false; 495 } 496 497 bool isRep(const MCInst &Inst) const override { 498 return Inst.getFlags() == X86::IP_HAS_REPEAT; 499 } 500 501 bool deleteREPPrefix(MCInst &Inst) const override { 502 if (Inst.getFlags() == X86::IP_HAS_REPEAT) { 503 Inst.setFlags(0); 504 return true; 505 } 506 return false; 507 } 508 509 // FIXME: For compatibility with old LLVM only! 510 bool isTerminator(const MCInst &Inst) const override { 511 if (Info->get(Inst.getOpcode()).isTerminator()) 512 return true; 513 switch (Inst.getOpcode()) { 514 default: 515 return false; 516 case X86::TRAP: 517 // Opcodes previously known as X86::UD2B 518 case X86::UD1Wm: 519 case X86::UD1Lm: 520 case X86::UD1Qm: 521 case X86::UD1Wr: 522 case X86::UD1Lr: 523 case X86::UD1Qr: 524 return true; 525 } 526 } 527 528 bool isIndirectCall(const MCInst &Inst) const override { 529 return isCall(Inst) && 530 ((getMemoryOperandNo(Inst) != -1) || Inst.getOperand(0).isReg()); 531 } 532 533 bool isPop(const MCInst &Inst) const override { 534 return getPopSize(Inst) == 0 ? false : true; 535 } 536 537 bool isTerminateBranch(const MCInst &Inst) const override { 538 return Inst.getOpcode() == X86::ENDBR32 || Inst.getOpcode() == X86::ENDBR64; 539 } 540 541 int getPopSize(const MCInst &Inst) const override { 542 switch (Inst.getOpcode()) { 543 case X86::POP16r: 544 case X86::POP16rmm: 545 case X86::POP16rmr: 546 case X86::POPF16: 547 case X86::POPA16: 548 case X86::POPDS16: 549 case X86::POPES16: 550 case X86::POPFS16: 551 case X86::POPGS16: 552 case X86::POPSS16: 553 return 2; 554 case X86::POP32r: 555 case X86::POP32rmm: 556 case X86::POP32rmr: 557 case X86::POPA32: 558 case X86::POPDS32: 559 case X86::POPES32: 560 case X86::POPF32: 561 case X86::POPFS32: 562 case X86::POPGS32: 563 case X86::POPSS32: 564 return 4; 565 case X86::POP64r: 566 case X86::POP64rmm: 567 case X86::POP64rmr: 568 case X86::POPF64: 569 case X86::POPFS64: 570 case X86::POPGS64: 571 return 8; 572 } 573 return 0; 574 } 575 576 bool isPush(const MCInst &Inst) const override { 577 return getPushSize(Inst) == 0 ? false : true; 578 } 579 580 int getPushSize(const MCInst &Inst) const override { 581 switch (Inst.getOpcode()) { 582 case X86::PUSH16i8: 583 case X86::PUSH16r: 584 case X86::PUSH16rmm: 585 case X86::PUSH16rmr: 586 case X86::PUSHA16: 587 case X86::PUSHCS16: 588 case X86::PUSHDS16: 589 case X86::PUSHES16: 590 case X86::PUSHF16: 591 case X86::PUSHFS16: 592 case X86::PUSHGS16: 593 case X86::PUSHSS16: 594 case X86::PUSHi16: 595 return 2; 596 case X86::PUSH32i8: 597 case X86::PUSH32r: 598 case X86::PUSH32rmm: 599 case X86::PUSH32rmr: 600 case X86::PUSHA32: 601 case X86::PUSHCS32: 602 case X86::PUSHDS32: 603 case X86::PUSHES32: 604 case X86::PUSHF32: 605 case X86::PUSHFS32: 606 case X86::PUSHGS32: 607 case X86::PUSHSS32: 608 case X86::PUSHi32: 609 return 4; 610 case X86::PUSH64i32: 611 case X86::PUSH64i8: 612 case X86::PUSH64r: 613 case X86::PUSH64rmm: 614 case X86::PUSH64rmr: 615 case X86::PUSHF64: 616 case X86::PUSHFS64: 617 case X86::PUSHGS64: 618 return 8; 619 } 620 return 0; 621 } 622 623 bool isADD64rr(const MCInst &Inst) const override { 624 return Inst.getOpcode() == X86::ADD64rr; 625 } 626 627 bool isSUB(const MCInst &Inst) const override { 628 return ::isSUB(Inst.getOpcode()); 629 } 630 631 bool isADDri(const MCInst &Inst) const { 632 return Inst.getOpcode() == X86::ADD64ri32 || 633 Inst.getOpcode() == X86::ADD64ri8; 634 } 635 636 bool isLEA64r(const MCInst &Inst) const override { 637 return Inst.getOpcode() == X86::LEA64r; 638 } 639 640 bool isMOVSX64rm32(const MCInst &Inst) const override { 641 return Inst.getOpcode() == X86::MOVSX64rm32; 642 } 643 644 bool isLeave(const MCInst &Inst) const override { 645 return Inst.getOpcode() == X86::LEAVE || 646 Inst.getOpcode() == X86::LEAVE64; 647 } 648 649 bool isMoveMem2Reg(const MCInst &Inst) const override { 650 switch (Inst.getOpcode()) { 651 case X86::MOV16rm: 652 case X86::MOV32rm: 653 case X86::MOV64rm: 654 return true; 655 } 656 return false; 657 } 658 659 bool isUnsupportedBranch(unsigned Opcode) const override { 660 switch (Opcode) { 661 default: 662 return false; 663 case X86::LOOP: 664 case X86::LOOPE: 665 case X86::LOOPNE: 666 case X86::JECXZ: 667 case X86::JRCXZ: 668 return true; 669 } 670 } 671 672 bool isLoad(const MCInst &Inst) const override { 673 if (isPop(Inst)) 674 return true; 675 676 int MemOpNo = getMemoryOperandNo(Inst); 677 const MCInstrDesc &MCII = Info->get(Inst.getOpcode()); 678 679 if (MemOpNo == -1) 680 return false; 681 682 return MCII.mayLoad(); 683 } 684 685 bool isStore(const MCInst &Inst) const override { 686 if (isPush(Inst)) 687 return true; 688 689 int MemOpNo = getMemoryOperandNo(Inst); 690 const MCInstrDesc &MCII = Info->get(Inst.getOpcode()); 691 692 if (MemOpNo == -1) 693 return false; 694 695 return MCII.mayStore(); 696 } 697 698 bool isCleanRegXOR(const MCInst &Inst) const override { 699 switch (Inst.getOpcode()) { 700 case X86::XOR16rr: 701 case X86::XOR32rr: 702 case X86::XOR64rr: 703 break; 704 default: 705 return false; 706 } 707 return (Inst.getOperand(0).getReg() == 708 Inst.getOperand(2).getReg()); 709 } 710 711 bool isPacked(const MCInst &Inst) const override { 712 const MCInstrDesc &Desc = Info->get(Inst.getOpcode()); 713 return (Desc.TSFlags & X86II::OpPrefixMask) == X86II::PD; 714 } 715 716 unsigned getTrapFillValue() const override { return 0xCC; } 717 718 struct IndJmpMatcherFrag1 : MCInstMatcher { 719 std::unique_ptr<MCInstMatcher> Base; 720 std::unique_ptr<MCInstMatcher> Scale; 721 std::unique_ptr<MCInstMatcher> Index; 722 std::unique_ptr<MCInstMatcher> Offset; 723 724 IndJmpMatcherFrag1(std::unique_ptr<MCInstMatcher> Base, 725 std::unique_ptr<MCInstMatcher> Scale, 726 std::unique_ptr<MCInstMatcher> Index, 727 std::unique_ptr<MCInstMatcher> Offset) 728 : Base(std::move(Base)), Scale(std::move(Scale)), 729 Index(std::move(Index)), Offset(std::move(Offset)) {} 730 731 bool match(const MCRegisterInfo &MRI, MCPlusBuilder &MIB, 732 MutableArrayRef<MCInst> InInstrWindow, int OpNum) override { 733 if (!MCInstMatcher::match(MRI, MIB, InInstrWindow, OpNum)) 734 return false; 735 736 if (CurInst->getOpcode() != X86::JMP64m) 737 return false; 738 739 int MemOpNo = MIB.getMemoryOperandNo(*CurInst); 740 if (MemOpNo == -1) 741 return false; 742 743 if (!Base->match(MRI, MIB, this->InstrWindow, MemOpNo + X86::AddrBaseReg)) 744 return false; 745 if (!Scale->match(MRI, MIB, this->InstrWindow, 746 MemOpNo + X86::AddrScaleAmt)) 747 return false; 748 if (!Index->match(MRI, MIB, this->InstrWindow, 749 MemOpNo + X86::AddrIndexReg)) 750 return false; 751 if (!Offset->match(MRI, MIB, this->InstrWindow, MemOpNo + X86::AddrDisp)) 752 return false; 753 return true; 754 } 755 756 void annotate(MCPlusBuilder &MIB, StringRef Annotation) override { 757 MIB.addAnnotation(*CurInst, Annotation, true); 758 Base->annotate(MIB, Annotation); 759 Scale->annotate(MIB, Annotation); 760 Index->annotate(MIB, Annotation); 761 Offset->annotate(MIB, Annotation); 762 } 763 }; 764 765 std::unique_ptr<MCInstMatcher> 766 matchIndJmp(std::unique_ptr<MCInstMatcher> Base, 767 std::unique_ptr<MCInstMatcher> Scale, 768 std::unique_ptr<MCInstMatcher> Index, 769 std::unique_ptr<MCInstMatcher> Offset) const override { 770 return std::unique_ptr<MCInstMatcher>( 771 new IndJmpMatcherFrag1(std::move(Base), std::move(Scale), 772 std::move(Index), std::move(Offset))); 773 } 774 775 struct IndJmpMatcherFrag2 : MCInstMatcher { 776 std::unique_ptr<MCInstMatcher> Reg; 777 778 IndJmpMatcherFrag2(std::unique_ptr<MCInstMatcher> Reg) 779 : Reg(std::move(Reg)) {} 780 781 bool match(const MCRegisterInfo &MRI, MCPlusBuilder &MIB, 782 MutableArrayRef<MCInst> InInstrWindow, int OpNum) override { 783 if (!MCInstMatcher::match(MRI, MIB, InInstrWindow, OpNum)) 784 return false; 785 786 if (CurInst->getOpcode() != X86::JMP64r) 787 return false; 788 789 return Reg->match(MRI, MIB, this->InstrWindow, 0); 790 } 791 792 void annotate(MCPlusBuilder &MIB, StringRef Annotation) override { 793 MIB.addAnnotation(*CurInst, Annotation, true); 794 Reg->annotate(MIB, Annotation); 795 } 796 }; 797 798 std::unique_ptr<MCInstMatcher> 799 matchIndJmp(std::unique_ptr<MCInstMatcher> Target) const override { 800 return std::unique_ptr<MCInstMatcher>( 801 new IndJmpMatcherFrag2(std::move(Target))); 802 } 803 804 struct LoadMatcherFrag1 : MCInstMatcher { 805 std::unique_ptr<MCInstMatcher> Base; 806 std::unique_ptr<MCInstMatcher> Scale; 807 std::unique_ptr<MCInstMatcher> Index; 808 std::unique_ptr<MCInstMatcher> Offset; 809 810 LoadMatcherFrag1(std::unique_ptr<MCInstMatcher> Base, 811 std::unique_ptr<MCInstMatcher> Scale, 812 std::unique_ptr<MCInstMatcher> Index, 813 std::unique_ptr<MCInstMatcher> Offset) 814 : Base(std::move(Base)), Scale(std::move(Scale)), 815 Index(std::move(Index)), Offset(std::move(Offset)) {} 816 817 bool match(const MCRegisterInfo &MRI, MCPlusBuilder &MIB, 818 MutableArrayRef<MCInst> InInstrWindow, int OpNum) override { 819 if (!MCInstMatcher::match(MRI, MIB, InInstrWindow, OpNum)) 820 return false; 821 822 if (CurInst->getOpcode() != X86::MOV64rm && 823 CurInst->getOpcode() != X86::MOVSX64rm32) 824 return false; 825 826 int MemOpNo = MIB.getMemoryOperandNo(*CurInst); 827 if (MemOpNo == -1) 828 return false; 829 830 if (!Base->match(MRI, MIB, this->InstrWindow, MemOpNo + X86::AddrBaseReg)) 831 return false; 832 if (!Scale->match(MRI, MIB, this->InstrWindow, 833 MemOpNo + X86::AddrScaleAmt)) 834 return false; 835 if (!Index->match(MRI, MIB, this->InstrWindow, 836 MemOpNo + X86::AddrIndexReg)) 837 return false; 838 if (!Offset->match(MRI, MIB, this->InstrWindow, MemOpNo + X86::AddrDisp)) 839 return false; 840 return true; 841 } 842 843 void annotate(MCPlusBuilder &MIB, StringRef Annotation) override { 844 MIB.addAnnotation(*CurInst, Annotation, true); 845 Base->annotate(MIB, Annotation); 846 Scale->annotate(MIB, Annotation); 847 Index->annotate(MIB, Annotation); 848 Offset->annotate(MIB, Annotation); 849 } 850 }; 851 852 std::unique_ptr<MCInstMatcher> 853 matchLoad(std::unique_ptr<MCInstMatcher> Base, 854 std::unique_ptr<MCInstMatcher> Scale, 855 std::unique_ptr<MCInstMatcher> Index, 856 std::unique_ptr<MCInstMatcher> Offset) const override { 857 return std::unique_ptr<MCInstMatcher>( 858 new LoadMatcherFrag1(std::move(Base), std::move(Scale), 859 std::move(Index), std::move(Offset))); 860 } 861 862 struct AddMatcher : MCInstMatcher { 863 std::unique_ptr<MCInstMatcher> A; 864 std::unique_ptr<MCInstMatcher> B; 865 866 AddMatcher(std::unique_ptr<MCInstMatcher> A, 867 std::unique_ptr<MCInstMatcher> B) 868 : A(std::move(A)), B(std::move(B)) {} 869 870 bool match(const MCRegisterInfo &MRI, MCPlusBuilder &MIB, 871 MutableArrayRef<MCInst> InInstrWindow, int OpNum) override { 872 if (!MCInstMatcher::match(MRI, MIB, InInstrWindow, OpNum)) 873 return false; 874 875 if (CurInst->getOpcode() == X86::ADD64rr || 876 CurInst->getOpcode() == X86::ADD64rr_DB || 877 CurInst->getOpcode() == X86::ADD64rr_REV) { 878 if (!A->match(MRI, MIB, this->InstrWindow, 1)) { 879 if (!B->match(MRI, MIB, this->InstrWindow, 1)) 880 return false; 881 return A->match(MRI, MIB, this->InstrWindow, 2); 882 } 883 884 if (B->match(MRI, MIB, this->InstrWindow, 2)) 885 return true; 886 887 if (!B->match(MRI, MIB, this->InstrWindow, 1)) 888 return false; 889 return A->match(MRI, MIB, this->InstrWindow, 2); 890 } 891 892 return false; 893 } 894 895 void annotate(MCPlusBuilder &MIB, StringRef Annotation) override { 896 MIB.addAnnotation(*CurInst, Annotation, true); 897 A->annotate(MIB, Annotation); 898 B->annotate(MIB, Annotation); 899 } 900 }; 901 902 virtual std::unique_ptr<MCInstMatcher> 903 matchAdd(std::unique_ptr<MCInstMatcher> A, 904 std::unique_ptr<MCInstMatcher> B) const override { 905 return std::unique_ptr<MCInstMatcher>( 906 new AddMatcher(std::move(A), std::move(B))); 907 } 908 909 struct LEAMatcher : MCInstMatcher { 910 std::unique_ptr<MCInstMatcher> Target; 911 912 LEAMatcher(std::unique_ptr<MCInstMatcher> Target) 913 : Target(std::move(Target)) {} 914 915 bool match(const MCRegisterInfo &MRI, MCPlusBuilder &MIB, 916 MutableArrayRef<MCInst> InInstrWindow, int OpNum) override { 917 if (!MCInstMatcher::match(MRI, MIB, InInstrWindow, OpNum)) 918 return false; 919 920 if (CurInst->getOpcode() != X86::LEA64r) 921 return false; 922 923 if (CurInst->getOperand(1 + X86::AddrScaleAmt).getImm() != 1 || 924 CurInst->getOperand(1 + X86::AddrIndexReg).getReg() != 925 X86::NoRegister || 926 (CurInst->getOperand(1 + X86::AddrBaseReg).getReg() != 927 X86::NoRegister && 928 CurInst->getOperand(1 + X86::AddrBaseReg).getReg() != X86::RIP)) 929 return false; 930 931 return Target->match(MRI, MIB, this->InstrWindow, 1 + X86::AddrDisp); 932 } 933 934 void annotate(MCPlusBuilder &MIB, StringRef Annotation) override { 935 MIB.addAnnotation(*CurInst, Annotation, true); 936 Target->annotate(MIB, Annotation); 937 } 938 }; 939 940 virtual std::unique_ptr<MCInstMatcher> 941 matchLoadAddr(std::unique_ptr<MCInstMatcher> Target) const override { 942 return std::unique_ptr<MCInstMatcher>(new LEAMatcher(std::move(Target))); 943 } 944 945 bool hasPCRelOperand(const MCInst &Inst) const override { 946 for (const MCOperand &Operand : Inst) 947 if (Operand.isReg() && Operand.getReg() == X86::RIP) 948 return true; 949 return false; 950 } 951 952 int getMemoryOperandNo(const MCInst &Inst) const override { 953 unsigned Opcode = Inst.getOpcode(); 954 const MCInstrDesc &Desc = Info->get(Opcode); 955 int MemOpNo = X86II::getMemoryOperandNo(Desc.TSFlags); 956 if (MemOpNo >= 0) 957 MemOpNo += X86II::getOperandBias(Desc); 958 return MemOpNo; 959 } 960 961 bool hasEVEXEncoding(const MCInst &Inst) const override { 962 const MCInstrDesc &Desc = Info->get(Inst.getOpcode()); 963 return (Desc.TSFlags & X86II::EncodingMask) == X86II::EVEX; 964 } 965 966 bool isMacroOpFusionPair(ArrayRef<MCInst> Insts) const override { 967 // FIXME: the macro-op fusion is triggered under different conditions 968 // on different cores. This implementation is for sandy-bridge+. 969 const auto *I = Insts.begin(); 970 while (I != Insts.end() && isPrefix(*I)) 971 ++I; 972 if (I == Insts.end()) 973 return false; 974 975 const MCInst &FirstInst = *I; 976 ++I; 977 while (I != Insts.end() && isPrefix(*I)) 978 ++I; 979 if (I == Insts.end()) 980 return false; 981 const MCInst &SecondInst = *I; 982 983 if (!isConditionalBranch(SecondInst)) 984 return false; 985 // J?CXZ and LOOP cannot be fused 986 if (SecondInst.getOpcode() == X86::LOOP || 987 SecondInst.getOpcode() == X86::LOOPE || 988 SecondInst.getOpcode() == X86::LOOPNE || 989 SecondInst.getOpcode() == X86::JECXZ || 990 SecondInst.getOpcode() == X86::JRCXZ) 991 return false; 992 993 const MCInstrDesc &Desc = Info->get(FirstInst.getOpcode()); 994 int MemOpNo = X86II::getMemoryOperandNo(Desc.TSFlags); 995 if (MemOpNo != -1) { 996 // Cannot fuse if first instruction operands are MEM-IMM. 997 if (X86II::hasImm(Desc.TSFlags)) 998 return false; 999 // Cannot fuse if first instruction may store. 1000 if (Desc.mayStore()) 1001 return false; 1002 } 1003 1004 // Cannot fuse if the first instruction uses RIP-relative memory. 1005 // FIXME: verify that this is true. 1006 if (hasPCRelOperand(FirstInst)) 1007 return false; 1008 1009 // Check instructions against table 3-1 in Intel's Optimization Guide. 1010 unsigned FirstInstGroup = 0; 1011 if (isTEST(FirstInst.getOpcode()) || isAND(FirstInst.getOpcode())) 1012 FirstInstGroup = 1; 1013 else if (isCMP(FirstInst.getOpcode()) || isADD(FirstInst.getOpcode()) || 1014 ::isSUB(FirstInst.getOpcode())) 1015 FirstInstGroup = 2; 1016 else if (isINC(FirstInst.getOpcode()) || isDEC(FirstInst.getOpcode())) 1017 FirstInstGroup = 3; 1018 1019 if (FirstInstGroup == 0) 1020 return false; 1021 1022 const unsigned CondCode = 1023 getCanonicalBranchCondCode(getCondCode(SecondInst)); 1024 switch (CondCode) { 1025 default: 1026 llvm_unreachable("unexpected conditional code"); 1027 return false; 1028 case X86::COND_E: 1029 case X86::COND_L: 1030 case X86::COND_G: 1031 return true; 1032 case X86::COND_O: 1033 case X86::COND_P: 1034 case X86::COND_S: 1035 if (FirstInstGroup == 1) 1036 return true; 1037 return false; 1038 case X86::COND_A: 1039 case X86::COND_B: 1040 if (FirstInstGroup != 3) 1041 return true; 1042 return false; 1043 } 1044 } 1045 1046 bool evaluateX86MemoryOperand(const MCInst &Inst, 1047 unsigned *BaseRegNum, 1048 int64_t *ScaleImm, 1049 unsigned *IndexRegNum, 1050 int64_t *DispImm, 1051 unsigned *SegmentRegNum, 1052 const MCExpr **DispExpr = nullptr) 1053 const override { 1054 assert(BaseRegNum && ScaleImm && IndexRegNum && SegmentRegNum && 1055 "one of the input pointers is null"); 1056 int MemOpNo = getMemoryOperandNo(Inst); 1057 if (MemOpNo < 0) 1058 return false; 1059 unsigned MemOpOffset = static_cast<unsigned>(MemOpNo); 1060 1061 if (MemOpOffset + X86::AddrSegmentReg >= MCPlus::getNumPrimeOperands(Inst)) 1062 return false; 1063 1064 const MCOperand &Base = Inst.getOperand(MemOpOffset + X86::AddrBaseReg); 1065 const MCOperand &Scale = Inst.getOperand(MemOpOffset + X86::AddrScaleAmt); 1066 const MCOperand &Index = Inst.getOperand(MemOpOffset + X86::AddrIndexReg); 1067 const MCOperand &Disp = Inst.getOperand(MemOpOffset + X86::AddrDisp); 1068 const MCOperand &Segment = 1069 Inst.getOperand(MemOpOffset + X86::AddrSegmentReg); 1070 1071 // Make sure it is a well-formed memory operand. 1072 if (!Base.isReg() || !Scale.isImm() || !Index.isReg() || 1073 (!Disp.isImm() && !Disp.isExpr()) || !Segment.isReg()) 1074 return false; 1075 1076 *BaseRegNum = Base.getReg(); 1077 *ScaleImm = Scale.getImm(); 1078 *IndexRegNum = Index.getReg(); 1079 if (Disp.isImm()) { 1080 assert(DispImm && "DispImm needs to be set"); 1081 *DispImm = Disp.getImm(); 1082 if (DispExpr) 1083 *DispExpr = nullptr; 1084 } else { 1085 assert(DispExpr && "DispExpr needs to be set"); 1086 *DispExpr = Disp.getExpr(); 1087 if (DispImm) 1088 *DispImm = 0; 1089 } 1090 *SegmentRegNum = Segment.getReg(); 1091 return true; 1092 } 1093 1094 bool evaluateMemOperandTarget(const MCInst &Inst, 1095 uint64_t &Target, 1096 uint64_t Address, 1097 uint64_t Size) const override { 1098 unsigned BaseRegNum; 1099 int64_t ScaleValue; 1100 unsigned IndexRegNum; 1101 int64_t DispValue; 1102 unsigned SegRegNum; 1103 const MCExpr *DispExpr = nullptr; 1104 if (!evaluateX86MemoryOperand(Inst, &BaseRegNum, &ScaleValue, &IndexRegNum, 1105 &DispValue, &SegRegNum, &DispExpr)) 1106 return false; 1107 1108 // Make sure it's a well-formed addressing we can statically evaluate. 1109 if ((BaseRegNum != X86::RIP && BaseRegNum != X86::NoRegister) || 1110 IndexRegNum != X86::NoRegister || SegRegNum != X86::NoRegister || 1111 DispExpr) 1112 return false; 1113 1114 Target = DispValue; 1115 if (BaseRegNum == X86::RIP) { 1116 assert(Size != 0 && "instruction size required in order to statically " 1117 "evaluate RIP-relative address"); 1118 Target += Address + Size; 1119 } 1120 return true; 1121 } 1122 1123 MCInst::iterator getMemOperandDisp(MCInst &Inst) const override { 1124 int MemOpNo = getMemoryOperandNo(Inst); 1125 if (MemOpNo < 0) 1126 return Inst.end(); 1127 return Inst.begin() + (MemOpNo + X86::AddrDisp); 1128 } 1129 1130 bool replaceMemOperandDisp(MCInst &Inst, MCOperand Operand) const override { 1131 MCOperand *OI = getMemOperandDisp(Inst); 1132 if (OI == Inst.end()) 1133 return false; 1134 *OI = Operand; 1135 return true; 1136 } 1137 1138 /// Get the registers used as function parameters. 1139 /// This function is specific to the x86_64 abi on Linux. 1140 BitVector getRegsUsedAsParams() const override { 1141 BitVector Regs = BitVector(RegInfo->getNumRegs(), false); 1142 Regs |= getAliases(X86::RSI); 1143 Regs |= getAliases(X86::RDI); 1144 Regs |= getAliases(X86::RDX); 1145 Regs |= getAliases(X86::RCX); 1146 Regs |= getAliases(X86::R8); 1147 Regs |= getAliases(X86::R9); 1148 return Regs; 1149 } 1150 1151 void getCalleeSavedRegs(BitVector &Regs) const override { 1152 Regs |= getAliases(X86::RBX); 1153 Regs |= getAliases(X86::RBP); 1154 Regs |= getAliases(X86::R12); 1155 Regs |= getAliases(X86::R13); 1156 Regs |= getAliases(X86::R14); 1157 Regs |= getAliases(X86::R15); 1158 } 1159 1160 void getDefaultDefIn(BitVector &Regs) const override { 1161 assert(Regs.size() >= RegInfo->getNumRegs() && 1162 "The size of BitVector is less than RegInfo->getNumRegs()."); 1163 Regs.set(X86::RAX); 1164 Regs.set(X86::RCX); 1165 Regs.set(X86::RDX); 1166 Regs.set(X86::RSI); 1167 Regs.set(X86::RDI); 1168 Regs.set(X86::R8); 1169 Regs.set(X86::R9); 1170 Regs.set(X86::XMM0); 1171 Regs.set(X86::XMM1); 1172 Regs.set(X86::XMM2); 1173 Regs.set(X86::XMM3); 1174 Regs.set(X86::XMM4); 1175 Regs.set(X86::XMM5); 1176 Regs.set(X86::XMM6); 1177 Regs.set(X86::XMM7); 1178 } 1179 1180 void getDefaultLiveOut(BitVector &Regs) const override { 1181 assert(Regs.size() >= RegInfo->getNumRegs() && 1182 "The size of BitVector is less than RegInfo->getNumRegs()."); 1183 Regs |= getAliases(X86::RAX); 1184 Regs |= getAliases(X86::RDX); 1185 Regs |= getAliases(X86::RCX); 1186 Regs |= getAliases(X86::XMM0); 1187 Regs |= getAliases(X86::XMM1); 1188 } 1189 1190 void getGPRegs(BitVector &Regs, bool IncludeAlias) const override { 1191 if (IncludeAlias) { 1192 Regs |= getAliases(X86::RAX); 1193 Regs |= getAliases(X86::RBX); 1194 Regs |= getAliases(X86::RBP); 1195 Regs |= getAliases(X86::RSI); 1196 Regs |= getAliases(X86::RDI); 1197 Regs |= getAliases(X86::RDX); 1198 Regs |= getAliases(X86::RCX); 1199 Regs |= getAliases(X86::R8); 1200 Regs |= getAliases(X86::R9); 1201 Regs |= getAliases(X86::R10); 1202 Regs |= getAliases(X86::R11); 1203 Regs |= getAliases(X86::R12); 1204 Regs |= getAliases(X86::R13); 1205 Regs |= getAliases(X86::R14); 1206 Regs |= getAliases(X86::R15); 1207 return; 1208 } 1209 Regs.set(X86::RAX); 1210 Regs.set(X86::RBX); 1211 Regs.set(X86::RBP); 1212 Regs.set(X86::RSI); 1213 Regs.set(X86::RDI); 1214 Regs.set(X86::RDX); 1215 Regs.set(X86::RCX); 1216 Regs.set(X86::R8); 1217 Regs.set(X86::R9); 1218 Regs.set(X86::R10); 1219 Regs.set(X86::R11); 1220 Regs.set(X86::R12); 1221 Regs.set(X86::R13); 1222 Regs.set(X86::R14); 1223 Regs.set(X86::R15); 1224 } 1225 1226 void getClassicGPRegs(BitVector &Regs) const override { 1227 Regs |= getAliases(X86::RAX); 1228 Regs |= getAliases(X86::RBX); 1229 Regs |= getAliases(X86::RBP); 1230 Regs |= getAliases(X86::RSI); 1231 Regs |= getAliases(X86::RDI); 1232 Regs |= getAliases(X86::RDX); 1233 Regs |= getAliases(X86::RCX); 1234 } 1235 1236 void getRepRegs(BitVector &Regs) const override { 1237 Regs |= getAliases(X86::RCX); 1238 } 1239 1240 MCPhysReg getAliasSized(MCPhysReg Reg, uint8_t Size) const override { 1241 switch (Reg) { 1242 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: case X86::AH: 1243 switch (Size) { 1244 case 8: return X86::RAX; case 4: return X86::EAX; 1245 case 2: return X86::AX; case 1: return X86::AL; 1246 default: llvm_unreachable("Unexpected size"); 1247 } 1248 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: case X86::BH: 1249 switch (Size) { 1250 case 8: return X86::RBX; case 4: return X86::EBX; 1251 case 2: return X86::BX; case 1: return X86::BL; 1252 default: llvm_unreachable("Unexpected size"); 1253 } 1254 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: case X86::DH: 1255 switch (Size) { 1256 case 8: return X86::RDX; case 4: return X86::EDX; 1257 case 2: return X86::DX; case 1: return X86::DL; 1258 default: llvm_unreachable("Unexpected size"); 1259 } 1260 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: 1261 switch (Size) { 1262 case 8: return X86::RDI; case 4: return X86::EDI; 1263 case 2: return X86::DI; case 1: return X86::DIL; 1264 default: llvm_unreachable("Unexpected size"); 1265 } 1266 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: 1267 switch (Size) { 1268 case 8: return X86::RSI; case 4: return X86::ESI; 1269 case 2: return X86::SI; case 1: return X86::SIL; 1270 default: llvm_unreachable("Unexpected size"); 1271 } 1272 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: case X86::CH: 1273 switch (Size) { 1274 case 8: return X86::RCX; case 4: return X86::ECX; 1275 case 2: return X86::CX; case 1: return X86::CL; 1276 default: llvm_unreachable("Unexpected size"); 1277 } 1278 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: 1279 switch (Size) { 1280 case 8: return X86::RSP; case 4: return X86::ESP; 1281 case 2: return X86::SP; case 1: return X86::SPL; 1282 default: llvm_unreachable("Unexpected size"); 1283 } 1284 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: 1285 switch (Size) { 1286 case 8: return X86::RBP; case 4: return X86::EBP; 1287 case 2: return X86::BP; case 1: return X86::BPL; 1288 default: llvm_unreachable("Unexpected size"); 1289 } 1290 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B: 1291 switch (Size) { 1292 case 8: return X86::R8; case 4: return X86::R8D; 1293 case 2: return X86::R8W; case 1: return X86::R8B; 1294 default: llvm_unreachable("Unexpected size"); 1295 } 1296 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B: 1297 switch (Size) { 1298 case 8: return X86::R9; case 4: return X86::R9D; 1299 case 2: return X86::R9W; case 1: return X86::R9B; 1300 default: llvm_unreachable("Unexpected size"); 1301 } 1302 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B: 1303 switch (Size) { 1304 case 8: return X86::R10; case 4: return X86::R10D; 1305 case 2: return X86::R10W; case 1: return X86::R10B; 1306 default: llvm_unreachable("Unexpected size"); 1307 } 1308 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B: 1309 switch (Size) { 1310 case 8: return X86::R11; case 4: return X86::R11D; 1311 case 2: return X86::R11W; case 1: return X86::R11B; 1312 default: llvm_unreachable("Unexpected size"); 1313 } 1314 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B: 1315 switch (Size) { 1316 case 8: return X86::R12; case 4: return X86::R12D; 1317 case 2: return X86::R12W; case 1: return X86::R12B; 1318 default: llvm_unreachable("Unexpected size"); 1319 } 1320 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B: 1321 switch (Size) { 1322 case 8: return X86::R13; case 4: return X86::R13D; 1323 case 2: return X86::R13W; case 1: return X86::R13B; 1324 default: llvm_unreachable("Unexpected size"); 1325 } 1326 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B: 1327 switch (Size) { 1328 case 8: return X86::R14; case 4: return X86::R14D; 1329 case 2: return X86::R14W; case 1: return X86::R14B; 1330 default: llvm_unreachable("Unexpected size"); 1331 } 1332 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B: 1333 switch (Size) { 1334 case 8: return X86::R15; case 4: return X86::R15D; 1335 case 2: return X86::R15W; case 1: return X86::R15B; 1336 default: llvm_unreachable("Unexpected size"); 1337 } 1338 default: 1339 dbgs() << Reg << " (get alias sized)\n"; 1340 llvm_unreachable("Unexpected reg number"); 1341 break; 1342 } 1343 } 1344 1345 bool isUpper8BitReg(MCPhysReg Reg) const override { 1346 switch (Reg) { 1347 case X86::AH: case X86::BH: case X86::CH: case X86::DH: 1348 return true; 1349 default: 1350 return false; 1351 } 1352 } 1353 1354 bool cannotUseREX(const MCInst &Inst) const override { 1355 switch(Inst.getOpcode()) { 1356 case X86::MOV8mr_NOREX: 1357 case X86::MOV8rm_NOREX: 1358 case X86::MOV8rr_NOREX: 1359 case X86::MOVSX32rm8_NOREX: 1360 case X86::MOVSX32rr8_NOREX: 1361 case X86::MOVZX32rm8_NOREX: 1362 case X86::MOVZX32rr8_NOREX: 1363 case X86::MOV8mr: 1364 case X86::MOV8rm: 1365 case X86::MOV8rr: 1366 case X86::MOVSX32rm8: 1367 case X86::MOVSX32rr8: 1368 case X86::MOVZX32rm8: 1369 case X86::MOVZX32rr8: 1370 case X86::TEST8ri: 1371 for (int I = 0, E = MCPlus::getNumPrimeOperands(Inst); I != E; ++I) { 1372 const MCOperand &Operand = Inst.getOperand(I); 1373 if (!Operand.isReg()) 1374 continue; 1375 if (isUpper8BitReg(Operand.getReg())) 1376 return true; 1377 } 1378 LLVM_FALLTHROUGH; 1379 default: 1380 return false; 1381 } 1382 } 1383 1384 bool isStackAccess(const MCInst &Inst, bool &IsLoad, bool &IsStore, 1385 bool &IsStoreFromReg, MCPhysReg &Reg, int32_t &SrcImm, 1386 uint16_t &StackPtrReg, int64_t &StackOffset, 1387 uint8_t &Size, bool &IsSimple, 1388 bool &IsIndexed) const override { 1389 // Detect simple push/pop cases first 1390 if (int Sz = getPushSize(Inst)) { 1391 IsLoad = false; 1392 IsStore = true; 1393 IsStoreFromReg = true; 1394 StackPtrReg = X86::RSP; 1395 StackOffset = -Sz; 1396 Size = Sz; 1397 IsSimple = true; 1398 if (Inst.getOperand(0).isImm()) 1399 SrcImm = Inst.getOperand(0).getImm(); 1400 else if (Inst.getOperand(0).isReg()) 1401 Reg = Inst.getOperand(0).getReg(); 1402 else 1403 IsSimple = false; 1404 1405 return true; 1406 } 1407 if (int Sz = getPopSize(Inst)) { 1408 IsLoad = true; 1409 IsStore = false; 1410 if (Inst.getNumOperands() == 0 || !Inst.getOperand(0).isReg()) { 1411 IsSimple = false; 1412 } else { 1413 Reg = Inst.getOperand(0).getReg(); 1414 IsSimple = true; 1415 } 1416 StackPtrReg = X86::RSP; 1417 StackOffset = 0; 1418 Size = Sz; 1419 return true; 1420 } 1421 1422 struct InstInfo { 1423 // Size in bytes that Inst loads from memory. 1424 uint8_t DataSize; 1425 bool IsLoad; 1426 bool IsStore; 1427 bool StoreFromReg; 1428 bool Simple; 1429 }; 1430 1431 InstInfo I; 1432 int MemOpNo = getMemoryOperandNo(Inst); 1433 const MCInstrDesc &MCII = Info->get(Inst.getOpcode()); 1434 // If it is not dealing with a memory operand, we discard it 1435 if (MemOpNo == -1 || MCII.isCall()) 1436 return false; 1437 1438 switch (Inst.getOpcode()) { 1439 default: { 1440 uint8_t Sz = 0; 1441 bool IsLoad = MCII.mayLoad(); 1442 bool IsStore = MCII.mayStore(); 1443 // Is it LEA? (deals with memory but is not loading nor storing) 1444 if (!IsLoad && !IsStore) 1445 return false; 1446 1447 // Try to guess data size involved in the load/store by looking at the 1448 // register size. If there's no reg involved, return 0 as size, meaning 1449 // we don't know. 1450 for (unsigned I = 0, E = MCII.getNumOperands(); I != E; ++I) { 1451 if (MCII.OpInfo[I].OperandType != MCOI::OPERAND_REGISTER) 1452 continue; 1453 if (static_cast<int>(I) >= MemOpNo && I < X86::AddrNumOperands) 1454 continue; 1455 Sz = RegInfo->getRegClass(MCII.OpInfo[I].RegClass).getSizeInBits() / 8; 1456 break; 1457 } 1458 I = {Sz, IsLoad, IsStore, false, false}; 1459 break; 1460 } 1461 case X86::MOV16rm: I = {2, true, false, false, true}; break; 1462 case X86::MOV32rm: I = {4, true, false, false, true}; break; 1463 case X86::MOV64rm: I = {8, true, false, false, true}; break; 1464 case X86::MOV16mr: I = {2, false, true, true, true}; break; 1465 case X86::MOV32mr: I = {4, false, true, true, true}; break; 1466 case X86::MOV64mr: I = {8, false, true, true, true}; break; 1467 case X86::MOV16mi: I = {2, false, true, false, true}; break; 1468 case X86::MOV32mi: I = {4, false, true, false, true}; break; 1469 } // end switch (Inst.getOpcode()) 1470 1471 unsigned BaseRegNum; 1472 int64_t ScaleValue; 1473 unsigned IndexRegNum; 1474 int64_t DispValue; 1475 unsigned SegRegNum; 1476 const MCExpr *DispExpr; 1477 if (!evaluateX86MemoryOperand(Inst, &BaseRegNum, &ScaleValue, &IndexRegNum, 1478 &DispValue, &SegRegNum, &DispExpr)) { 1479 LLVM_DEBUG(dbgs() << "Evaluate failed on "); 1480 LLVM_DEBUG(Inst.dump()); 1481 return false; 1482 } 1483 1484 // Make sure it's a stack access 1485 if (BaseRegNum != X86::RBP && BaseRegNum != X86::RSP) 1486 return false; 1487 1488 IsLoad = I.IsLoad; 1489 IsStore = I.IsStore; 1490 IsStoreFromReg = I.StoreFromReg; 1491 Size = I.DataSize; 1492 IsSimple = I.Simple; 1493 StackPtrReg = BaseRegNum; 1494 StackOffset = DispValue; 1495 IsIndexed = IndexRegNum != X86::NoRegister || SegRegNum != X86::NoRegister; 1496 1497 if (!I.Simple) 1498 return true; 1499 1500 // Retrieve related register in simple MOV from/to stack operations. 1501 unsigned MemOpOffset = static_cast<unsigned>(MemOpNo); 1502 if (I.IsLoad) { 1503 MCOperand RegOpnd = Inst.getOperand(0); 1504 assert(RegOpnd.isReg() && "unexpected destination operand"); 1505 Reg = RegOpnd.getReg(); 1506 } else if (I.IsStore) { 1507 MCOperand SrcOpnd = 1508 Inst.getOperand(MemOpOffset + X86::AddrSegmentReg + 1); 1509 if (I.StoreFromReg) { 1510 assert(SrcOpnd.isReg() && "unexpected source operand"); 1511 Reg = SrcOpnd.getReg(); 1512 } else { 1513 assert(SrcOpnd.isImm() && "unexpected source operand"); 1514 SrcImm = SrcOpnd.getImm(); 1515 } 1516 } 1517 1518 return true; 1519 } 1520 1521 void changeToPushOrPop(MCInst &Inst) const override { 1522 assert(!isPush(Inst) && !isPop(Inst)); 1523 1524 struct InstInfo { 1525 // Size in bytes that Inst loads from memory. 1526 uint8_t DataSize; 1527 bool IsLoad; 1528 bool StoreFromReg; 1529 }; 1530 1531 InstInfo I; 1532 switch (Inst.getOpcode()) { 1533 default: { 1534 llvm_unreachable("Unhandled opcode"); 1535 return; 1536 } 1537 case X86::MOV16rm: I = {2, true, false}; break; 1538 case X86::MOV32rm: I = {4, true, false}; break; 1539 case X86::MOV64rm: I = {8, true, false}; break; 1540 case X86::MOV16mr: I = {2, false, true}; break; 1541 case X86::MOV32mr: I = {4, false, true}; break; 1542 case X86::MOV64mr: I = {8, false, true}; break; 1543 case X86::MOV16mi: I = {2, false, false}; break; 1544 case X86::MOV32mi: I = {4, false, false}; break; 1545 } // end switch (Inst.getOpcode()) 1546 1547 unsigned BaseRegNum; 1548 int64_t ScaleValue; 1549 unsigned IndexRegNum; 1550 int64_t DispValue; 1551 unsigned SegRegNum; 1552 const MCExpr *DispExpr; 1553 if (!evaluateX86MemoryOperand(Inst, &BaseRegNum, &ScaleValue, &IndexRegNum, 1554 &DispValue, &SegRegNum, &DispExpr)) { 1555 llvm_unreachable("Evaluate failed"); 1556 return; 1557 } 1558 // Make sure it's a stack access 1559 if (BaseRegNum != X86::RBP && BaseRegNum != X86::RSP) { 1560 llvm_unreachable("Not a stack access"); 1561 return; 1562 } 1563 1564 unsigned MemOpOffset = getMemoryOperandNo(Inst); 1565 unsigned NewOpcode = 0; 1566 if (I.IsLoad) { 1567 switch (I.DataSize) { 1568 case 2: NewOpcode = X86::POP16r; break; 1569 case 4: NewOpcode = X86::POP32r; break; 1570 case 8: NewOpcode = X86::POP64r; break; 1571 default: 1572 assert(false); 1573 } 1574 unsigned RegOpndNum = Inst.getOperand(0).getReg(); 1575 Inst.clear(); 1576 Inst.setOpcode(NewOpcode); 1577 Inst.addOperand(MCOperand::createReg(RegOpndNum)); 1578 } else { 1579 MCOperand SrcOpnd = 1580 Inst.getOperand(MemOpOffset + X86::AddrSegmentReg + 1); 1581 if (I.StoreFromReg) { 1582 switch (I.DataSize) { 1583 case 2: NewOpcode = X86::PUSH16r; break; 1584 case 4: NewOpcode = X86::PUSH32r; break; 1585 case 8: NewOpcode = X86::PUSH64r; break; 1586 default: 1587 assert(false); 1588 } 1589 assert(SrcOpnd.isReg() && "unexpected source operand"); 1590 unsigned RegOpndNum = SrcOpnd.getReg(); 1591 Inst.clear(); 1592 Inst.setOpcode(NewOpcode); 1593 Inst.addOperand(MCOperand::createReg(RegOpndNum)); 1594 } else { 1595 switch (I.DataSize) { 1596 case 2: NewOpcode = X86::PUSH16i8; break; 1597 case 4: NewOpcode = X86::PUSH32i8; break; 1598 case 8: NewOpcode = X86::PUSH64i32; break; 1599 default: 1600 assert(false); 1601 } 1602 assert(SrcOpnd.isImm() && "unexpected source operand"); 1603 int64_t SrcImm = SrcOpnd.getImm(); 1604 Inst.clear(); 1605 Inst.setOpcode(NewOpcode); 1606 Inst.addOperand(MCOperand::createImm(SrcImm)); 1607 } 1608 } 1609 } 1610 1611 bool isStackAdjustment(const MCInst &Inst) const override { 1612 switch (Inst.getOpcode()) { 1613 default: 1614 return false; 1615 case X86::SUB64ri32: 1616 case X86::SUB64ri8: 1617 case X86::ADD64ri32: 1618 case X86::ADD64ri8: 1619 case X86::LEA64r: 1620 break; 1621 } 1622 1623 const MCInstrDesc &MCII = Info->get(Inst.getOpcode()); 1624 for (int I = 0, E = MCII.getNumDefs(); I != E; ++I) { 1625 const MCOperand &Operand = Inst.getOperand(I); 1626 if (Operand.isReg() && Operand.getReg() == X86::RSP) 1627 return true; 1628 } 1629 return false; 1630 } 1631 1632 bool evaluateSimple(const MCInst &Inst, int64_t &Output, 1633 std::pair<MCPhysReg, int64_t> Input1, 1634 std::pair<MCPhysReg, int64_t> Input2) const override { 1635 1636 auto getOperandVal = [&](MCPhysReg Reg) -> ErrorOr<int64_t> { 1637 if (Reg == Input1.first) 1638 return Input1.second; 1639 if (Reg == Input2.first) 1640 return Input2.second; 1641 return make_error_code(errc::result_out_of_range); 1642 }; 1643 1644 switch (Inst.getOpcode()) { 1645 default: 1646 return false; 1647 1648 case X86::AND64ri32: 1649 case X86::AND64ri8: 1650 if (!Inst.getOperand(2).isImm()) 1651 return false; 1652 if (ErrorOr<int64_t> InputVal = 1653 getOperandVal(Inst.getOperand(1).getReg())) 1654 Output = *InputVal & Inst.getOperand(2).getImm(); 1655 else 1656 return false; 1657 break; 1658 case X86::SUB64ri32: 1659 case X86::SUB64ri8: 1660 if (!Inst.getOperand(2).isImm()) 1661 return false; 1662 if (ErrorOr<int64_t> InputVal = 1663 getOperandVal(Inst.getOperand(1).getReg())) 1664 Output = *InputVal - Inst.getOperand(2).getImm(); 1665 else 1666 return false; 1667 break; 1668 case X86::ADD64ri32: 1669 case X86::ADD64ri8: 1670 if (!Inst.getOperand(2).isImm()) 1671 return false; 1672 if (ErrorOr<int64_t> InputVal = 1673 getOperandVal(Inst.getOperand(1).getReg())) 1674 Output = *InputVal + Inst.getOperand(2).getImm(); 1675 else 1676 return false; 1677 break; 1678 case X86::ADD64i32: 1679 if (!Inst.getOperand(0).isImm()) 1680 return false; 1681 if (ErrorOr<int64_t> InputVal = getOperandVal(X86::RAX)) 1682 Output = *InputVal + Inst.getOperand(0).getImm(); 1683 else 1684 return false; 1685 break; 1686 1687 case X86::LEA64r: { 1688 unsigned BaseRegNum; 1689 int64_t ScaleValue; 1690 unsigned IndexRegNum; 1691 int64_t DispValue; 1692 unsigned SegRegNum; 1693 const MCExpr *DispExpr = nullptr; 1694 if (!evaluateX86MemoryOperand(Inst, &BaseRegNum, &ScaleValue, 1695 &IndexRegNum, &DispValue, &SegRegNum, 1696 &DispExpr)) 1697 return false; 1698 1699 if (BaseRegNum == X86::NoRegister || IndexRegNum != X86::NoRegister || 1700 SegRegNum != X86::NoRegister || DispExpr) 1701 return false; 1702 1703 if (ErrorOr<int64_t> InputVal = getOperandVal(BaseRegNum)) 1704 Output = *InputVal + DispValue; 1705 else 1706 return false; 1707 1708 break; 1709 } 1710 } 1711 return true; 1712 } 1713 1714 bool isRegToRegMove(const MCInst &Inst, MCPhysReg &From, 1715 MCPhysReg &To) const override { 1716 switch (Inst.getOpcode()) { 1717 default: 1718 return false; 1719 case X86::LEAVE: 1720 case X86::LEAVE64: 1721 To = getStackPointer(); 1722 From = getFramePointer(); 1723 return true; 1724 case X86::MOV64rr: 1725 To = Inst.getOperand(0).getReg(); 1726 From = Inst.getOperand(1).getReg(); 1727 return true; 1728 } 1729 } 1730 1731 MCPhysReg getStackPointer() const override { return X86::RSP; } 1732 MCPhysReg getFramePointer() const override { return X86::RBP; } 1733 MCPhysReg getFlagsReg() const override { return X86::EFLAGS; } 1734 1735 bool escapesVariable(const MCInst &Inst, bool HasFramePointer) const override { 1736 int MemOpNo = getMemoryOperandNo(Inst); 1737 const MCInstrDesc &MCII = Info->get(Inst.getOpcode()); 1738 const unsigned NumDefs = MCII.getNumDefs(); 1739 static BitVector SPBPAliases(BitVector(getAliases(X86::RSP)) |= 1740 getAliases(X86::RBP)); 1741 static BitVector SPAliases(getAliases(X86::RSP)); 1742 1743 // FIXME: PUSH can be technically a leak, but let's ignore this for now 1744 // because a lot of harmless prologue code will spill SP to the stack. 1745 // Unless push is clearly pushing an object address to the stack as 1746 // demonstrated by having a MemOp. 1747 bool IsPush = isPush(Inst); 1748 if (IsPush && MemOpNo == -1) 1749 return false; 1750 1751 // We use this to detect LEA (has memop but does not access mem) 1752 bool AccessMem = MCII.mayLoad() || MCII.mayStore(); 1753 bool DoesLeak = false; 1754 for (int I = 0, E = MCPlus::getNumPrimeOperands(Inst); I != E; ++I) { 1755 // Ignore if SP/BP is used to dereference memory -- that's fine 1756 if (MemOpNo != -1 && !IsPush && AccessMem && I >= MemOpNo && 1757 I <= MemOpNo + 5) 1758 continue; 1759 // Ignore if someone is writing to SP/BP 1760 if (I < static_cast<int>(NumDefs)) 1761 continue; 1762 1763 const MCOperand &Operand = Inst.getOperand(I); 1764 if (HasFramePointer && Operand.isReg() && SPBPAliases[Operand.getReg()]) { 1765 DoesLeak = true; 1766 break; 1767 } 1768 if (!HasFramePointer && Operand.isReg() && SPAliases[Operand.getReg()]) { 1769 DoesLeak = true; 1770 break; 1771 } 1772 } 1773 1774 // If potential leak, check if it is not just writing to itself/sp/bp 1775 if (DoesLeak) { 1776 for (int I = 0, E = NumDefs; I != E; ++I) { 1777 const MCOperand &Operand = Inst.getOperand(I); 1778 if (HasFramePointer && Operand.isReg() && 1779 SPBPAliases[Operand.getReg()]) { 1780 DoesLeak = false; 1781 break; 1782 } 1783 if (!HasFramePointer && Operand.isReg() && 1784 SPAliases[Operand.getReg()]) { 1785 DoesLeak = false; 1786 break; 1787 } 1788 } 1789 } 1790 return DoesLeak; 1791 } 1792 1793 bool addToImm(MCInst &Inst, int64_t &Amt, MCContext *Ctx) const override { 1794 unsigned ImmOpNo = -1U; 1795 int MemOpNo = getMemoryOperandNo(Inst); 1796 if (MemOpNo != -1) 1797 ImmOpNo = MemOpNo + X86::AddrDisp; 1798 else 1799 for (unsigned Index = 0; 1800 Index < MCPlus::getNumPrimeOperands(Inst); ++Index) 1801 if (Inst.getOperand(Index).isImm()) 1802 ImmOpNo = Index; 1803 if (ImmOpNo == -1U) 1804 return false; 1805 1806 MCOperand &Operand = Inst.getOperand(ImmOpNo); 1807 Amt += Operand.getImm(); 1808 Operand.setImm(Amt); 1809 // Check for the need for relaxation 1810 if (int64_t(Amt) == int64_t(int8_t(Amt))) 1811 return true; 1812 1813 // Relax instruction 1814 switch (Inst.getOpcode()) { 1815 case X86::SUB64ri8: 1816 Inst.setOpcode(X86::SUB64ri32); 1817 break; 1818 case X86::ADD64ri8: 1819 Inst.setOpcode(X86::ADD64ri32); 1820 break; 1821 default: 1822 // No need for relaxation 1823 break; 1824 } 1825 return true; 1826 } 1827 1828 /// TODO: this implementation currently works for the most common opcodes that 1829 /// load from memory. It can be extended to work with memory store opcodes as 1830 /// well as more memory load opcodes. 1831 bool replaceMemOperandWithImm(MCInst &Inst, StringRef ConstantData, 1832 uint64_t Offset) const override { 1833 enum CheckSignExt : uint8_t { 1834 NOCHECK = 0, 1835 CHECK8, 1836 CHECK32, 1837 }; 1838 1839 using CheckList = std::vector<std::pair<CheckSignExt, unsigned>>; 1840 struct InstInfo { 1841 // Size in bytes that Inst loads from memory. 1842 uint8_t DataSize; 1843 1844 // True when the target operand has to be duplicated because the opcode 1845 // expects a LHS operand. 1846 bool HasLHS; 1847 1848 // List of checks and corresponding opcodes to be used. We try to use the 1849 // smallest possible immediate value when various sizes are available, 1850 // hence we may need to check whether a larger constant fits in a smaller 1851 // immediate. 1852 CheckList Checks; 1853 }; 1854 1855 InstInfo I; 1856 1857 switch (Inst.getOpcode()) { 1858 default: { 1859 switch (getPopSize(Inst)) { 1860 case 2: I = {2, false, {{NOCHECK, X86::MOV16ri}}}; break; 1861 case 4: I = {4, false, {{NOCHECK, X86::MOV32ri}}}; break; 1862 case 8: I = {8, false, {{CHECK32, X86::MOV64ri32}, 1863 {NOCHECK, X86::MOV64rm}}}; break; 1864 default: return false; 1865 } 1866 break; 1867 } 1868 1869 // MOV 1870 case X86::MOV8rm: I = {1, false, {{NOCHECK, X86::MOV8ri}}}; break; 1871 case X86::MOV16rm: I = {2, false, {{NOCHECK, X86::MOV16ri}}}; break; 1872 case X86::MOV32rm: I = {4, false, {{NOCHECK, X86::MOV32ri}}}; break; 1873 case X86::MOV64rm: I = {8, false, {{CHECK32, X86::MOV64ri32}, 1874 {NOCHECK, X86::MOV64rm}}}; break; 1875 1876 // MOVZX 1877 case X86::MOVZX16rm8: I = {1, false, {{NOCHECK, X86::MOV16ri}}}; break; 1878 case X86::MOVZX32rm8: I = {1, false, {{NOCHECK, X86::MOV32ri}}}; break; 1879 case X86::MOVZX32rm16: I = {2, false, {{NOCHECK, X86::MOV32ri}}}; break; 1880 1881 // CMP 1882 case X86::CMP8rm: I = {1, false, {{NOCHECK, X86::CMP8ri}}}; break; 1883 case X86::CMP16rm: I = {2, false, {{CHECK8, X86::CMP16ri8}, 1884 {NOCHECK, X86::CMP16ri}}}; break; 1885 case X86::CMP32rm: I = {4, false, {{CHECK8, X86::CMP32ri8}, 1886 {NOCHECK, X86::CMP32ri}}}; break; 1887 case X86::CMP64rm: I = {8, false, {{CHECK8, X86::CMP64ri8}, 1888 {CHECK32, X86::CMP64ri32}, 1889 {NOCHECK, X86::CMP64rm}}}; break; 1890 1891 // TEST 1892 case X86::TEST8mr: I = {1, false, {{NOCHECK, X86::TEST8ri}}}; break; 1893 case X86::TEST16mr: I = {2, false, {{NOCHECK, X86::TEST16ri}}}; break; 1894 case X86::TEST32mr: I = {4, false, {{NOCHECK, X86::TEST32ri}}}; break; 1895 case X86::TEST64mr: I = {8, false, {{CHECK32, X86::TEST64ri32}, 1896 {NOCHECK, X86::TEST64mr}}}; break; 1897 1898 // ADD 1899 case X86::ADD8rm: I = {1, true, {{NOCHECK, X86::ADD8ri}}}; break; 1900 case X86::ADD16rm: I = {2, true, {{CHECK8, X86::ADD16ri8}, 1901 {NOCHECK, X86::ADD16ri}}}; break; 1902 case X86::ADD32rm: I = {4, true, {{CHECK8, X86::ADD32ri8}, 1903 {NOCHECK, X86::ADD32ri}}}; break; 1904 case X86::ADD64rm: I = {8, true, {{CHECK8, X86::ADD64ri8}, 1905 {CHECK32, X86::ADD64ri32}, 1906 {NOCHECK, X86::ADD64rm}}}; break; 1907 1908 // SUB 1909 case X86::SUB8rm: I = {1, true, {{NOCHECK, X86::SUB8ri}}}; break; 1910 case X86::SUB16rm: I = {2, true, {{CHECK8, X86::SUB16ri8}, 1911 {NOCHECK, X86::SUB16ri}}}; break; 1912 case X86::SUB32rm: I = {4, true, {{CHECK8, X86::SUB32ri8}, 1913 {NOCHECK, X86::SUB32ri}}}; break; 1914 case X86::SUB64rm: I = {8, true, {{CHECK8, X86::SUB64ri8}, 1915 {CHECK32, X86::SUB64ri32}, 1916 {NOCHECK, X86::SUB64rm}}}; break; 1917 1918 // AND 1919 case X86::AND8rm: I = {1, true, {{NOCHECK, X86::AND8ri}}}; break; 1920 case X86::AND16rm: I = {2, true, {{CHECK8, X86::AND16ri8}, 1921 {NOCHECK, X86::AND16ri}}}; break; 1922 case X86::AND32rm: I = {4, true, {{CHECK8, X86::AND32ri8}, 1923 {NOCHECK, X86::AND32ri}}}; break; 1924 case X86::AND64rm: I = {8, true, {{CHECK8, X86::AND64ri8}, 1925 {CHECK32, X86::AND64ri32}, 1926 {NOCHECK, X86::AND64rm}}}; break; 1927 1928 // OR 1929 case X86::OR8rm: I = {1, true, {{NOCHECK, X86::OR8ri}}}; break; 1930 case X86::OR16rm: I = {2, true, {{CHECK8, X86::OR16ri8}, 1931 {NOCHECK, X86::OR16ri}}}; break; 1932 case X86::OR32rm: I = {4, true, {{CHECK8, X86::OR32ri8}, 1933 {NOCHECK, X86::OR32ri}}}; break; 1934 case X86::OR64rm: I = {8, true, {{CHECK8, X86::OR64ri8}, 1935 {CHECK32, X86::OR64ri32}, 1936 {NOCHECK, X86::OR64rm}}}; break; 1937 1938 // XOR 1939 case X86::XOR8rm: I = {1, true, {{NOCHECK, X86::XOR8ri}}}; break; 1940 case X86::XOR16rm: I = {2, true, {{CHECK8, X86::XOR16ri8}, 1941 {NOCHECK, X86::XOR16ri}}}; break; 1942 case X86::XOR32rm: I = {4, true, {{CHECK8, X86::XOR32ri8}, 1943 {NOCHECK, X86::XOR32ri}}}; break; 1944 case X86::XOR64rm: I = {8, true, {{CHECK8, X86::XOR64ri8}, 1945 {CHECK32, X86::XOR64ri32}, 1946 {NOCHECK, X86::XOR64rm}}}; break; 1947 } 1948 1949 // Compute the immediate value. 1950 assert(Offset + I.DataSize <= ConstantData.size() && 1951 "invalid offset for given constant data"); 1952 int64_t ImmVal = 1953 DataExtractor(ConstantData, true, 8).getSigned(&Offset, I.DataSize); 1954 1955 // Compute the new opcode. 1956 unsigned NewOpcode = 0; 1957 for (const std::pair<CheckSignExt, unsigned> &Check : I.Checks) { 1958 NewOpcode = Check.second; 1959 if (Check.first == NOCHECK) 1960 break; 1961 if (Check.first == CHECK8 && 1962 ImmVal >= std::numeric_limits<int8_t>::min() && 1963 ImmVal <= std::numeric_limits<int8_t>::max()) 1964 break; 1965 if (Check.first == CHECK32 && 1966 ImmVal >= std::numeric_limits<int32_t>::min() && 1967 ImmVal <= std::numeric_limits<int32_t>::max()) 1968 break; 1969 } 1970 if (NewOpcode == Inst.getOpcode()) 1971 return false; 1972 1973 // Modify the instruction. 1974 MCOperand ImmOp = MCOperand::createImm(ImmVal); 1975 uint32_t TargetOpNum = 0; 1976 // Test instruction does not follow the regular pattern of putting the 1977 // memory reference of a load (5 MCOperands) last in the list of operands. 1978 // Since it is not modifying the register operand, it is not treated as 1979 // a destination operand and it is not the first operand as it is in the 1980 // other instructions we treat here. 1981 if (NewOpcode == X86::TEST8ri || 1982 NewOpcode == X86::TEST16ri || 1983 NewOpcode == X86::TEST32ri || 1984 NewOpcode == X86::TEST64ri32) 1985 TargetOpNum = getMemoryOperandNo(Inst) + X86::AddrNumOperands; 1986 1987 MCOperand TargetOp = Inst.getOperand(TargetOpNum); 1988 Inst.clear(); 1989 Inst.setOpcode(NewOpcode); 1990 Inst.addOperand(TargetOp); 1991 if (I.HasLHS) 1992 Inst.addOperand(TargetOp); 1993 Inst.addOperand(ImmOp); 1994 1995 return true; 1996 } 1997 1998 /// TODO: this implementation currently works for the most common opcodes that 1999 /// load from memory. It can be extended to work with memory store opcodes as 2000 /// well as more memory load opcodes. 2001 bool replaceMemOperandWithReg(MCInst &Inst, MCPhysReg RegNum) const override { 2002 unsigned NewOpcode; 2003 2004 switch (Inst.getOpcode()) { 2005 default: { 2006 switch (getPopSize(Inst)) { 2007 case 2: NewOpcode = X86::MOV16rr; break; 2008 case 4: NewOpcode = X86::MOV32rr; break; 2009 case 8: NewOpcode = X86::MOV64rr; break; 2010 default: return false; 2011 } 2012 break; 2013 } 2014 2015 // MOV 2016 case X86::MOV8rm: NewOpcode = X86::MOV8rr; break; 2017 case X86::MOV16rm: NewOpcode = X86::MOV16rr; break; 2018 case X86::MOV32rm: NewOpcode = X86::MOV32rr; break; 2019 case X86::MOV64rm: NewOpcode = X86::MOV64rr; break; 2020 } 2021 2022 // Modify the instruction. 2023 MCOperand RegOp = MCOperand::createReg(RegNum); 2024 MCOperand TargetOp = Inst.getOperand(0); 2025 Inst.clear(); 2026 Inst.setOpcode(NewOpcode); 2027 Inst.addOperand(TargetOp); 2028 Inst.addOperand(RegOp); 2029 2030 return true; 2031 } 2032 2033 bool isRedundantMove(const MCInst &Inst) const override { 2034 switch (Inst.getOpcode()) { 2035 default: 2036 return false; 2037 2038 // MOV 2039 case X86::MOV8rr: 2040 case X86::MOV16rr: 2041 case X86::MOV32rr: 2042 case X86::MOV64rr: 2043 break; 2044 } 2045 2046 assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg()); 2047 return Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg(); 2048 } 2049 2050 bool requiresAlignedAddress(const MCInst &Inst) const override { 2051 const MCInstrDesc &Desc = Info->get(Inst.getOpcode()); 2052 for (unsigned int I = 0; I < Desc.getNumOperands(); ++I) { 2053 const MCOperandInfo &Op = Desc.OpInfo[I]; 2054 if (Op.OperandType != MCOI::OPERAND_REGISTER) 2055 continue; 2056 if (Op.RegClass == X86::VR128RegClassID) 2057 return true; 2058 } 2059 return false; 2060 } 2061 2062 bool convertJmpToTailCall(MCInst &Inst) override { 2063 if (isTailCall(Inst)) 2064 return false; 2065 2066 int NewOpcode; 2067 switch (Inst.getOpcode()) { 2068 default: 2069 return false; 2070 case X86::JMP_1: 2071 case X86::JMP_2: 2072 case X86::JMP_4: 2073 NewOpcode = X86::JMP_4; 2074 break; 2075 case X86::JMP16m: 2076 case X86::JMP32m: 2077 case X86::JMP64m: 2078 NewOpcode = X86::JMP32m; 2079 break; 2080 case X86::JMP16r: 2081 case X86::JMP32r: 2082 case X86::JMP64r: 2083 NewOpcode = X86::JMP32r; 2084 break; 2085 } 2086 2087 Inst.setOpcode(NewOpcode); 2088 setTailCall(Inst); 2089 return true; 2090 } 2091 2092 bool convertTailCallToJmp(MCInst &Inst) override { 2093 int NewOpcode; 2094 switch (Inst.getOpcode()) { 2095 default: 2096 return false; 2097 case X86::JMP_4: 2098 NewOpcode = X86::JMP_1; 2099 break; 2100 case X86::JMP32m: 2101 NewOpcode = X86::JMP64m; 2102 break; 2103 case X86::JMP32r: 2104 NewOpcode = X86::JMP64r; 2105 break; 2106 } 2107 2108 Inst.setOpcode(NewOpcode); 2109 removeAnnotation(Inst, MCPlus::MCAnnotation::kTailCall); 2110 removeAnnotation(Inst, "Offset"); 2111 return true; 2112 } 2113 2114 bool convertTailCallToCall(MCInst &Inst) override { 2115 int NewOpcode; 2116 switch (Inst.getOpcode()) { 2117 default: 2118 return false; 2119 case X86::JMP_4: 2120 NewOpcode = X86::CALL64pcrel32; 2121 break; 2122 case X86::JMP32m: 2123 NewOpcode = X86::CALL64m; 2124 break; 2125 case X86::JMP32r: 2126 NewOpcode = X86::CALL64r; 2127 break; 2128 } 2129 2130 Inst.setOpcode(NewOpcode); 2131 removeAnnotation(Inst, MCPlus::MCAnnotation::kTailCall); 2132 return true; 2133 } 2134 2135 bool convertCallToIndirectCall(MCInst &Inst, 2136 const MCSymbol *TargetLocation, 2137 MCContext *Ctx) override { 2138 bool IsTailCall = isTailCall(Inst); 2139 assert((Inst.getOpcode() == X86::CALL64pcrel32 || 2140 (Inst.getOpcode() == X86::JMP_4 && IsTailCall)) && 2141 "64-bit direct (tail) call instruction expected"); 2142 const auto NewOpcode = (Inst.getOpcode() == X86::CALL64pcrel32) 2143 ? X86::CALL64m 2144 : X86::JMP32m; 2145 Inst.setOpcode(NewOpcode); 2146 2147 // Replace the first operand and preserve auxiliary operands of 2148 // the instruction. 2149 Inst.erase(Inst.begin()); 2150 Inst.insert(Inst.begin(), 2151 MCOperand::createReg(X86::NoRegister)); // AddrSegmentReg 2152 Inst.insert(Inst.begin(), 2153 MCOperand::createExpr( // Displacement 2154 MCSymbolRefExpr::create(TargetLocation, 2155 MCSymbolRefExpr::VK_None, 2156 *Ctx))); 2157 Inst.insert(Inst.begin(), 2158 MCOperand::createReg(X86::NoRegister)); // IndexReg 2159 Inst.insert(Inst.begin(), 2160 MCOperand::createImm(1)); // ScaleAmt 2161 Inst.insert(Inst.begin(), 2162 MCOperand::createReg(X86::RIP)); // BaseReg 2163 2164 return true; 2165 } 2166 2167 void convertIndirectCallToLoad(MCInst &Inst, MCPhysReg Reg) override { 2168 bool IsTailCall = isTailCall(Inst); 2169 if (IsTailCall) 2170 removeAnnotation(Inst, MCPlus::MCAnnotation::kTailCall); 2171 if (Inst.getOpcode() == X86::CALL64m || 2172 (Inst.getOpcode() == X86::JMP32m && IsTailCall)) { 2173 Inst.setOpcode(X86::MOV64rm); 2174 Inst.insert(Inst.begin(), MCOperand::createReg(Reg)); 2175 return; 2176 } 2177 if (Inst.getOpcode() == X86::CALL64r || 2178 (Inst.getOpcode() == X86::JMP32r && IsTailCall)) { 2179 Inst.setOpcode(X86::MOV64rr); 2180 Inst.insert(Inst.begin(), MCOperand::createReg(Reg)); 2181 return; 2182 } 2183 LLVM_DEBUG(Inst.dump()); 2184 llvm_unreachable("not implemented"); 2185 } 2186 2187 bool shortenInstruction(MCInst &Inst) const override { 2188 unsigned OldOpcode = Inst.getOpcode(); 2189 unsigned NewOpcode = OldOpcode; 2190 2191 // Check and remove EIZ/RIZ. These cases represent ambiguous cases where SIB 2192 // byte is present, but no index is used and modrm alone shoud have been 2193 // enough. Converting to NoRegister effectively removes the SIB byte. 2194 int MemOpNo = getMemoryOperandNo(Inst); 2195 if (MemOpNo >= 0) { 2196 MCOperand &IndexOp = 2197 Inst.getOperand(static_cast<unsigned>(MemOpNo) + X86::AddrIndexReg); 2198 if (IndexOp.getReg() == X86::EIZ || 2199 IndexOp.getReg() == X86::RIZ) 2200 IndexOp = MCOperand::createReg(X86::NoRegister); 2201 } 2202 2203 if (isBranch(Inst)) { 2204 NewOpcode = getShortBranchOpcode(OldOpcode); 2205 } else if (OldOpcode == X86::MOV64ri) { 2206 if (Inst.getOperand(MCPlus::getNumPrimeOperands(Inst) - 1).isImm()) { 2207 const int64_t Imm = 2208 Inst.getOperand(MCPlus::getNumPrimeOperands(Inst) - 1).getImm(); 2209 if (int64_t(Imm) == int64_t(int32_t(Imm))) 2210 NewOpcode = X86::MOV64ri32; 2211 } 2212 } else { 2213 // If it's arithmetic instruction check if signed operand fits in 1 byte. 2214 const unsigned ShortOpcode = getShortArithOpcode(OldOpcode); 2215 if (ShortOpcode != OldOpcode && 2216 Inst.getOperand(MCPlus::getNumPrimeOperands(Inst) - 1).isImm()) { 2217 int64_t Imm = 2218 Inst.getOperand(MCPlus::getNumPrimeOperands(Inst) - 1).getImm(); 2219 if (int64_t(Imm) == int64_t(int8_t(Imm))) 2220 NewOpcode = ShortOpcode; 2221 } 2222 } 2223 2224 if (NewOpcode == OldOpcode) 2225 return false; 2226 2227 Inst.setOpcode(NewOpcode); 2228 return true; 2229 } 2230 2231 bool lowerTailCall(MCInst &Inst) override { 2232 if (Inst.getOpcode() == X86::JMP_4 && isTailCall(Inst)) { 2233 Inst.setOpcode(X86::JMP_1); 2234 removeAnnotation(Inst, MCPlus::MCAnnotation::kTailCall); 2235 return true; 2236 } 2237 return false; 2238 } 2239 2240 const MCSymbol *getTargetSymbol(const MCInst &Inst, 2241 unsigned OpNum = 0) const override { 2242 if (OpNum >= MCPlus::getNumPrimeOperands(Inst)) 2243 return nullptr; 2244 2245 const MCOperand &Op = Inst.getOperand(OpNum); 2246 if (!Op.isExpr()) 2247 return nullptr; 2248 2249 auto *SymExpr = dyn_cast<MCSymbolRefExpr>(Op.getExpr()); 2250 if (!SymExpr || SymExpr->getKind() != MCSymbolRefExpr::VK_None) 2251 return nullptr; 2252 2253 return &SymExpr->getSymbol(); 2254 } 2255 2256 // This is the same as the base class, but since we are overriding one of 2257 // getTargetSymbol's signatures above, we need to override all of them. 2258 const MCSymbol *getTargetSymbol(const MCExpr *Expr) const override { 2259 return &cast<const MCSymbolRefExpr>(Expr)->getSymbol(); 2260 } 2261 2262 bool analyzeBranch(InstructionIterator Begin, 2263 InstructionIterator End, 2264 const MCSymbol *&TBB, 2265 const MCSymbol *&FBB, 2266 MCInst *&CondBranch, 2267 MCInst *&UncondBranch) const override { 2268 auto I = End; 2269 2270 // Bottom-up analysis 2271 while (I != Begin) { 2272 --I; 2273 2274 // Ignore nops and CFIs 2275 if (isPseudo(*I)) 2276 continue; 2277 2278 // Stop when we find the first non-terminator 2279 if (!isTerminator(*I)) 2280 break; 2281 2282 if (!isBranch(*I)) 2283 break; 2284 2285 // Handle unconditional branches. 2286 if ((I->getOpcode() == X86::JMP_1 || 2287 I->getOpcode() == X86::JMP_2 || 2288 I->getOpcode() == X86::JMP_4) && 2289 !isTailCall(*I)) { 2290 // If any code was seen after this unconditional branch, we've seen 2291 // unreachable code. Ignore them. 2292 CondBranch = nullptr; 2293 UncondBranch = &*I; 2294 const MCSymbol *Sym = getTargetSymbol(*I); 2295 assert(Sym != nullptr && 2296 "Couldn't extract BB symbol from jump operand"); 2297 TBB = Sym; 2298 continue; 2299 } 2300 2301 // Handle conditional branches and ignore indirect branches 2302 if (!isUnsupportedBranch(I->getOpcode()) && 2303 getCondCode(*I) == X86::COND_INVALID) { 2304 // Indirect branch 2305 return false; 2306 } 2307 2308 if (CondBranch == nullptr) { 2309 const MCSymbol *TargetBB = getTargetSymbol(*I); 2310 if (TargetBB == nullptr) { 2311 // Unrecognized branch target 2312 return false; 2313 } 2314 FBB = TBB; 2315 TBB = TargetBB; 2316 CondBranch = &*I; 2317 continue; 2318 } 2319 2320 llvm_unreachable("multiple conditional branches in one BB"); 2321 } 2322 return true; 2323 } 2324 2325 template <typename Itr> 2326 std::pair<IndirectBranchType, MCInst *> 2327 analyzePICJumpTable(Itr II, 2328 Itr IE, 2329 MCPhysReg R1, 2330 MCPhysReg R2) const { 2331 // Analyze PIC-style jump table code template: 2332 // 2333 // lea PIC_JUMP_TABLE(%rip), {%r1|%r2} <- MemLocInstr 2334 // mov ({%r1|%r2}, %index, 4), {%r2|%r1} 2335 // add %r2, %r1 2336 // jmp *%r1 2337 // 2338 // (with any irrelevant instructions in-between) 2339 // 2340 // When we call this helper we've already determined %r1 and %r2, and 2341 // reverse instruction iterator \p II is pointing to the ADD instruction. 2342 // 2343 // PIC jump table looks like following: 2344 // 2345 // JT: ---------- 2346 // E1:| L1 - JT | 2347 // |----------| 2348 // E2:| L2 - JT | 2349 // |----------| 2350 // | | 2351 // ...... 2352 // En:| Ln - JT | 2353 // ---------- 2354 // 2355 // Where L1, L2, ..., Ln represent labels in the function. 2356 // 2357 // The actual relocations in the table will be of the form: 2358 // 2359 // Ln - JT 2360 // = (Ln - En) + (En - JT) 2361 // = R_X86_64_PC32(Ln) + En - JT 2362 // = R_X86_64_PC32(Ln + offsetof(En)) 2363 // 2364 LLVM_DEBUG(dbgs() << "Checking for PIC jump table\n"); 2365 MCInst *MemLocInstr = nullptr; 2366 const MCInst *MovInstr = nullptr; 2367 while (++II != IE) { 2368 MCInst &Instr = *II; 2369 const MCInstrDesc &InstrDesc = Info->get(Instr.getOpcode()); 2370 if (!InstrDesc.hasDefOfPhysReg(Instr, R1, *RegInfo) && 2371 !InstrDesc.hasDefOfPhysReg(Instr, R2, *RegInfo)) { 2372 // Ignore instructions that don't affect R1, R2 registers. 2373 continue; 2374 } 2375 if (!MovInstr) { 2376 // Expect to see MOV instruction. 2377 if (!isMOVSX64rm32(Instr)) { 2378 LLVM_DEBUG(dbgs() << "MOV instruction expected.\n"); 2379 break; 2380 } 2381 2382 // Check if it's setting %r1 or %r2. In canonical form it sets %r2. 2383 // If it sets %r1 - rename the registers so we have to only check 2384 // a single form. 2385 unsigned MovDestReg = Instr.getOperand(0).getReg(); 2386 if (MovDestReg != R2) 2387 std::swap(R1, R2); 2388 if (MovDestReg != R2) { 2389 LLVM_DEBUG(dbgs() << "MOV instruction expected to set %r2\n"); 2390 break; 2391 } 2392 2393 // Verify operands for MOV. 2394 unsigned BaseRegNum; 2395 int64_t ScaleValue; 2396 unsigned IndexRegNum; 2397 int64_t DispValue; 2398 unsigned SegRegNum; 2399 if (!evaluateX86MemoryOperand(Instr, &BaseRegNum, 2400 &ScaleValue, &IndexRegNum, 2401 &DispValue, &SegRegNum)) 2402 break; 2403 if (BaseRegNum != R1 || 2404 ScaleValue != 4 || 2405 IndexRegNum == X86::NoRegister || 2406 DispValue != 0 || 2407 SegRegNum != X86::NoRegister) 2408 break; 2409 MovInstr = &Instr; 2410 } else { 2411 if (!InstrDesc.hasDefOfPhysReg(Instr, R1, *RegInfo)) 2412 continue; 2413 if (!isLEA64r(Instr)) { 2414 LLVM_DEBUG(dbgs() << "LEA instruction expected\n"); 2415 break; 2416 } 2417 if (Instr.getOperand(0).getReg() != R1) { 2418 LLVM_DEBUG(dbgs() << "LEA instruction expected to set %r1\n"); 2419 break; 2420 } 2421 2422 // Verify operands for LEA. 2423 unsigned BaseRegNum; 2424 int64_t ScaleValue; 2425 unsigned IndexRegNum; 2426 const MCExpr *DispExpr = nullptr; 2427 int64_t DispValue; 2428 unsigned SegRegNum; 2429 if (!evaluateX86MemoryOperand(Instr, &BaseRegNum, 2430 &ScaleValue, &IndexRegNum, 2431 &DispValue, &SegRegNum, &DispExpr)) 2432 break; 2433 if (BaseRegNum != RegInfo->getProgramCounter() || 2434 IndexRegNum != X86::NoRegister || 2435 SegRegNum != X86::NoRegister || 2436 DispExpr == nullptr) 2437 break; 2438 MemLocInstr = &Instr; 2439 break; 2440 } 2441 } 2442 2443 if (!MemLocInstr) 2444 return std::make_pair(IndirectBranchType::UNKNOWN, nullptr); 2445 2446 LLVM_DEBUG(dbgs() << "checking potential PIC jump table\n"); 2447 return std::make_pair(IndirectBranchType::POSSIBLE_PIC_JUMP_TABLE, 2448 MemLocInstr); 2449 } 2450 2451 IndirectBranchType analyzeIndirectBranch( 2452 MCInst &Instruction, 2453 InstructionIterator Begin, 2454 InstructionIterator End, 2455 const unsigned PtrSize, 2456 MCInst *&MemLocInstrOut, 2457 unsigned &BaseRegNumOut, 2458 unsigned &IndexRegNumOut, 2459 int64_t &DispValueOut, 2460 const MCExpr *&DispExprOut, 2461 MCInst *&PCRelBaseOut 2462 ) const override { 2463 // Try to find a (base) memory location from where the address for 2464 // the indirect branch is loaded. For X86-64 the memory will be specified 2465 // in the following format: 2466 // 2467 // {%rip}/{%basereg} + Imm + IndexReg * Scale 2468 // 2469 // We are interested in the cases where Scale == sizeof(uintptr_t) and 2470 // the contents of the memory are presumably an array of pointers to code. 2471 // 2472 // Normal jump table: 2473 // 2474 // jmp *(JUMP_TABLE, %index, Scale) <- MemLocInstr 2475 // 2476 // or 2477 // 2478 // mov (JUMP_TABLE, %index, Scale), %r1 <- MemLocInstr 2479 // ... 2480 // jmp %r1 2481 // 2482 // We handle PIC-style jump tables separately. 2483 // 2484 MemLocInstrOut = nullptr; 2485 BaseRegNumOut = X86::NoRegister; 2486 IndexRegNumOut = X86::NoRegister; 2487 DispValueOut = 0; 2488 DispExprOut = nullptr; 2489 2490 std::reverse_iterator<InstructionIterator> II(End); 2491 std::reverse_iterator<InstructionIterator> IE(Begin); 2492 2493 IndirectBranchType Type = IndirectBranchType::UNKNOWN; 2494 2495 // An instruction referencing memory used by jump instruction (directly or 2496 // via register). This location could be an array of function pointers 2497 // in case of indirect tail call, or a jump table. 2498 MCInst *MemLocInstr = nullptr; 2499 2500 if (MCPlus::getNumPrimeOperands(Instruction) == 1) { 2501 // If the indirect jump is on register - try to detect if the 2502 // register value is loaded from a memory location. 2503 assert(Instruction.getOperand(0).isReg() && "register operand expected"); 2504 const unsigned R1 = Instruction.getOperand(0).getReg(); 2505 // Check if one of the previous instructions defines the jump-on register. 2506 for (auto PrevII = II; PrevII != IE; ++PrevII) { 2507 MCInst &PrevInstr = *PrevII; 2508 const MCInstrDesc &PrevInstrDesc = Info->get(PrevInstr.getOpcode()); 2509 2510 if (!PrevInstrDesc.hasDefOfPhysReg(PrevInstr, R1, *RegInfo)) 2511 continue; 2512 2513 if (isMoveMem2Reg(PrevInstr)) { 2514 MemLocInstr = &PrevInstr; 2515 break; 2516 } 2517 if (isADD64rr(PrevInstr)) { 2518 unsigned R2 = PrevInstr.getOperand(2).getReg(); 2519 if (R1 == R2) 2520 return IndirectBranchType::UNKNOWN; 2521 std::tie(Type, MemLocInstr) = analyzePICJumpTable(PrevII, IE, R1, R2); 2522 break; 2523 } 2524 return IndirectBranchType::UNKNOWN; 2525 } 2526 if (!MemLocInstr) { 2527 // No definition seen for the register in this function so far. Could be 2528 // an input parameter - which means it is an external code reference. 2529 // It also could be that the definition happens to be in the code that 2530 // we haven't processed yet. Since we have to be conservative, return 2531 // as UNKNOWN case. 2532 return IndirectBranchType::UNKNOWN; 2533 } 2534 } else { 2535 MemLocInstr = &Instruction; 2536 } 2537 2538 const MCRegister RIPRegister = RegInfo->getProgramCounter(); 2539 2540 // Analyze the memory location. 2541 unsigned BaseRegNum, IndexRegNum, SegRegNum; 2542 int64_t ScaleValue, DispValue; 2543 const MCExpr *DispExpr; 2544 2545 if (!evaluateX86MemoryOperand(*MemLocInstr, &BaseRegNum, 2546 &ScaleValue, &IndexRegNum, 2547 &DispValue, &SegRegNum, 2548 &DispExpr)) 2549 return IndirectBranchType::UNKNOWN; 2550 2551 BaseRegNumOut = BaseRegNum; 2552 IndexRegNumOut = IndexRegNum; 2553 DispValueOut = DispValue; 2554 DispExprOut = DispExpr; 2555 2556 if ((BaseRegNum != X86::NoRegister && BaseRegNum != RIPRegister) || 2557 SegRegNum != X86::NoRegister) 2558 return IndirectBranchType::UNKNOWN; 2559 2560 if (MemLocInstr == &Instruction && 2561 (!ScaleValue || IndexRegNum == X86::NoRegister)) { 2562 MemLocInstrOut = MemLocInstr; 2563 return IndirectBranchType::POSSIBLE_FIXED_BRANCH; 2564 } 2565 2566 if (Type == IndirectBranchType::POSSIBLE_PIC_JUMP_TABLE && 2567 (ScaleValue != 1 || BaseRegNum != RIPRegister)) 2568 return IndirectBranchType::UNKNOWN; 2569 2570 if (Type != IndirectBranchType::POSSIBLE_PIC_JUMP_TABLE && 2571 ScaleValue != PtrSize) 2572 return IndirectBranchType::UNKNOWN; 2573 2574 MemLocInstrOut = MemLocInstr; 2575 2576 return Type; 2577 } 2578 2579 /// Analyze a callsite to see if it could be a virtual method call. This only 2580 /// checks to see if the overall pattern is satisfied, it does not guarantee 2581 /// that the callsite is a true virtual method call. 2582 /// The format of virtual method calls that are recognized is one of the 2583 /// following: 2584 /// 2585 /// Form 1: (found in debug code) 2586 /// add METHOD_OFFSET, %VtableReg 2587 /// mov (%VtableReg), %MethodReg 2588 /// ... 2589 /// call or jmp *%MethodReg 2590 /// 2591 /// Form 2: 2592 /// mov METHOD_OFFSET(%VtableReg), %MethodReg 2593 /// ... 2594 /// call or jmp *%MethodReg 2595 /// 2596 /// Form 3: 2597 /// ... 2598 /// call or jmp *METHOD_OFFSET(%VtableReg) 2599 /// 2600 bool analyzeVirtualMethodCall(InstructionIterator ForwardBegin, 2601 InstructionIterator ForwardEnd, 2602 std::vector<MCInst *> &MethodFetchInsns, 2603 unsigned &VtableRegNum, 2604 unsigned &MethodRegNum, 2605 uint64_t &MethodOffset) const override { 2606 VtableRegNum = X86::NoRegister; 2607 MethodRegNum = X86::NoRegister; 2608 MethodOffset = 0; 2609 2610 std::reverse_iterator<InstructionIterator> Itr(ForwardEnd); 2611 std::reverse_iterator<InstructionIterator> End(ForwardBegin); 2612 2613 MCInst &CallInst = *Itr++; 2614 assert(isIndirectBranch(CallInst) || isCall(CallInst)); 2615 2616 unsigned BaseReg, IndexReg, SegmentReg; 2617 int64_t Scale, Disp; 2618 const MCExpr *DispExpr; 2619 2620 // The call can just be jmp offset(reg) 2621 if (evaluateX86MemoryOperand(CallInst, 2622 &BaseReg, 2623 &Scale, 2624 &IndexReg, 2625 &Disp, 2626 &SegmentReg, 2627 &DispExpr)) { 2628 if (!DispExpr && 2629 BaseReg != X86::RIP && 2630 BaseReg != X86::RBP && 2631 BaseReg != X86::NoRegister) { 2632 MethodRegNum = BaseReg; 2633 if (Scale == 1 && 2634 IndexReg == X86::NoRegister && 2635 SegmentReg == X86::NoRegister) { 2636 VtableRegNum = MethodRegNum; 2637 MethodOffset = Disp; 2638 MethodFetchInsns.push_back(&CallInst); 2639 return true; 2640 } 2641 } 2642 return false; 2643 } 2644 if (CallInst.getOperand(0).isReg()) 2645 MethodRegNum = CallInst.getOperand(0).getReg(); 2646 else 2647 return false; 2648 2649 if (MethodRegNum == X86::RIP || MethodRegNum == X86::RBP) { 2650 VtableRegNum = X86::NoRegister; 2651 MethodRegNum = X86::NoRegister; 2652 return false; 2653 } 2654 2655 // find load from vtable, this may or may not include the method offset 2656 while (Itr != End) { 2657 MCInst &CurInst = *Itr++; 2658 const MCInstrDesc &Desc = Info->get(CurInst.getOpcode()); 2659 if (Desc.hasDefOfPhysReg(CurInst, MethodRegNum, *RegInfo)) { 2660 if (isLoad(CurInst) && 2661 evaluateX86MemoryOperand(CurInst, 2662 &BaseReg, 2663 &Scale, 2664 &IndexReg, 2665 &Disp, 2666 &SegmentReg, 2667 &DispExpr)) { 2668 if (!DispExpr && 2669 Scale == 1 && 2670 BaseReg != X86::RIP && 2671 BaseReg != X86::RBP && 2672 BaseReg != X86::NoRegister && 2673 IndexReg == X86::NoRegister && 2674 SegmentReg == X86::NoRegister && 2675 BaseReg != X86::RIP) { 2676 VtableRegNum = BaseReg; 2677 MethodOffset = Disp; 2678 MethodFetchInsns.push_back(&CurInst); 2679 if (MethodOffset != 0) 2680 return true; 2681 break; 2682 } 2683 } 2684 return false; 2685 } 2686 } 2687 2688 if (!VtableRegNum) 2689 return false; 2690 2691 // look for any adds affecting the method register. 2692 while (Itr != End) { 2693 MCInst &CurInst = *Itr++; 2694 const MCInstrDesc &Desc = Info->get(CurInst.getOpcode()); 2695 if (Desc.hasDefOfPhysReg(CurInst, VtableRegNum, *RegInfo)) { 2696 if (isADDri(CurInst)) { 2697 assert(!MethodOffset); 2698 MethodOffset = CurInst.getOperand(2).getImm(); 2699 MethodFetchInsns.insert(MethodFetchInsns.begin(), &CurInst); 2700 break; 2701 } 2702 } 2703 } 2704 2705 return true; 2706 } 2707 2708 bool createStackPointerIncrement(MCInst &Inst, int Size, 2709 bool NoFlagsClobber) const override { 2710 if (NoFlagsClobber) { 2711 Inst.setOpcode(X86::LEA64r); 2712 Inst.clear(); 2713 Inst.addOperand(MCOperand::createReg(X86::RSP)); 2714 Inst.addOperand(MCOperand::createReg(X86::RSP)); // BaseReg 2715 Inst.addOperand(MCOperand::createImm(1)); // ScaleAmt 2716 Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // IndexReg 2717 Inst.addOperand(MCOperand::createImm(-Size)); // Displacement 2718 Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // AddrSegmentReg 2719 return true; 2720 } 2721 Inst.setOpcode(X86::SUB64ri8); 2722 Inst.clear(); 2723 Inst.addOperand(MCOperand::createReg(X86::RSP)); 2724 Inst.addOperand(MCOperand::createReg(X86::RSP)); 2725 Inst.addOperand(MCOperand::createImm(Size)); 2726 return true; 2727 } 2728 2729 bool createStackPointerDecrement(MCInst &Inst, int Size, 2730 bool NoFlagsClobber) const override { 2731 if (NoFlagsClobber) { 2732 Inst.setOpcode(X86::LEA64r); 2733 Inst.clear(); 2734 Inst.addOperand(MCOperand::createReg(X86::RSP)); 2735 Inst.addOperand(MCOperand::createReg(X86::RSP)); // BaseReg 2736 Inst.addOperand(MCOperand::createImm(1)); // ScaleAmt 2737 Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // IndexReg 2738 Inst.addOperand(MCOperand::createImm(Size)); // Displacement 2739 Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // AddrSegmentReg 2740 return true; 2741 } 2742 Inst.setOpcode(X86::ADD64ri8); 2743 Inst.clear(); 2744 Inst.addOperand(MCOperand::createReg(X86::RSP)); 2745 Inst.addOperand(MCOperand::createReg(X86::RSP)); 2746 Inst.addOperand(MCOperand::createImm(Size)); 2747 return true; 2748 } 2749 2750 bool createSaveToStack(MCInst &Inst, const MCPhysReg &StackReg, int Offset, 2751 const MCPhysReg &SrcReg, int Size) const override { 2752 unsigned NewOpcode; 2753 switch (Size) { 2754 default: 2755 return false; 2756 case 2: NewOpcode = X86::MOV16mr; break; 2757 case 4: NewOpcode = X86::MOV32mr; break; 2758 case 8: NewOpcode = X86::MOV64mr; break; 2759 } 2760 Inst.setOpcode(NewOpcode); 2761 Inst.clear(); 2762 Inst.addOperand(MCOperand::createReg(StackReg)); // BaseReg 2763 Inst.addOperand(MCOperand::createImm(1)); // ScaleAmt 2764 Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // IndexReg 2765 Inst.addOperand(MCOperand::createImm(Offset)); // Displacement 2766 Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // AddrSegmentReg 2767 Inst.addOperand(MCOperand::createReg(SrcReg)); 2768 return true; 2769 } 2770 2771 bool createRestoreFromStack(MCInst &Inst, const MCPhysReg &StackReg, 2772 int Offset, const MCPhysReg &DstReg, 2773 int Size) const override { 2774 return createLoad(Inst, StackReg, /*Scale=*/1, /*IndexReg=*/X86::NoRegister, 2775 Offset, nullptr, /*AddrSegmentReg=*/X86::NoRegister, 2776 DstReg, Size); 2777 } 2778 2779 bool createLoad(MCInst &Inst, const MCPhysReg &BaseReg, int64_t Scale, 2780 const MCPhysReg &IndexReg, int64_t Offset, 2781 const MCExpr *OffsetExpr, const MCPhysReg &AddrSegmentReg, 2782 const MCPhysReg &DstReg, int Size) const override { 2783 unsigned NewOpcode; 2784 switch (Size) { 2785 default: 2786 return false; 2787 case 2: NewOpcode = X86::MOV16rm; break; 2788 case 4: NewOpcode = X86::MOV32rm; break; 2789 case 8: NewOpcode = X86::MOV64rm; break; 2790 } 2791 Inst.setOpcode(NewOpcode); 2792 Inst.clear(); 2793 Inst.addOperand(MCOperand::createReg(DstReg)); 2794 Inst.addOperand(MCOperand::createReg(BaseReg)); 2795 Inst.addOperand(MCOperand::createImm(Scale)); 2796 Inst.addOperand(MCOperand::createReg(IndexReg)); 2797 if (OffsetExpr) 2798 Inst.addOperand(MCOperand::createExpr(OffsetExpr)); // Displacement 2799 else 2800 Inst.addOperand(MCOperand::createImm(Offset)); // Displacement 2801 Inst.addOperand(MCOperand::createReg(AddrSegmentReg)); // AddrSegmentReg 2802 return true; 2803 } 2804 2805 void createLoadImmediate(MCInst &Inst, const MCPhysReg Dest, 2806 uint32_t Imm) const override { 2807 Inst.setOpcode(X86::MOV64ri32); 2808 Inst.clear(); 2809 Inst.addOperand(MCOperand::createReg(Dest)); 2810 Inst.addOperand(MCOperand::createImm(Imm)); 2811 } 2812 2813 bool createIncMemory(MCInst &Inst, const MCSymbol *Target, 2814 MCContext *Ctx) const override { 2815 2816 Inst.setOpcode(X86::LOCK_INC64m); 2817 Inst.clear(); 2818 Inst.addOperand(MCOperand::createReg(X86::RIP)); // BaseReg 2819 Inst.addOperand(MCOperand::createImm(1)); // ScaleAmt 2820 Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // IndexReg 2821 2822 Inst.addOperand(MCOperand::createExpr( 2823 MCSymbolRefExpr::create(Target, MCSymbolRefExpr::VK_None, 2824 *Ctx))); // Displacement 2825 Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // AddrSegmentReg 2826 return true; 2827 } 2828 2829 bool createIJmp32Frag(SmallVectorImpl<MCInst> &Insts, 2830 const MCOperand &BaseReg, const MCOperand &Scale, 2831 const MCOperand &IndexReg, const MCOperand &Offset, 2832 const MCOperand &TmpReg) const override { 2833 // The code fragment we emit here is: 2834 // 2835 // mov32 (%base, %index, scale), %tmpreg 2836 // ijmp *(%tmpreg) 2837 // 2838 MCInst IJmp; 2839 IJmp.setOpcode(X86::JMP64r); 2840 IJmp.addOperand(TmpReg); 2841 2842 MCInst Load; 2843 Load.setOpcode(X86::MOV32rm); 2844 Load.addOperand(TmpReg); 2845 Load.addOperand(BaseReg); 2846 Load.addOperand(Scale); 2847 Load.addOperand(IndexReg); 2848 Load.addOperand(Offset); 2849 Load.addOperand(MCOperand::createReg(X86::NoRegister)); 2850 2851 Insts.push_back(Load); 2852 Insts.push_back(IJmp); 2853 return true; 2854 } 2855 2856 bool createNoop(MCInst &Inst) const override { 2857 Inst.setOpcode(X86::NOOP); 2858 return true; 2859 } 2860 2861 bool createReturn(MCInst &Inst) const override { 2862 Inst.setOpcode(X86::RET64); 2863 return true; 2864 } 2865 2866 InstructionListType createInlineMemcpy(bool ReturnEnd) const override { 2867 InstructionListType Code; 2868 if (ReturnEnd) 2869 Code.emplace_back(MCInstBuilder(X86::LEA64r) 2870 .addReg(X86::RAX) 2871 .addReg(X86::RDI) 2872 .addImm(1) 2873 .addReg(X86::RDX) 2874 .addImm(0) 2875 .addReg(X86::NoRegister)); 2876 else 2877 Code.emplace_back(MCInstBuilder(X86::MOV64rr) 2878 .addReg(X86::RAX) 2879 .addReg(X86::RDI)); 2880 2881 Code.emplace_back(MCInstBuilder(X86::MOV32rr) 2882 .addReg(X86::ECX) 2883 .addReg(X86::EDX)); 2884 Code.emplace_back(MCInstBuilder(X86::REP_MOVSB_64)); 2885 2886 return Code; 2887 } 2888 2889 InstructionListType createOneByteMemcpy() const override { 2890 InstructionListType Code; 2891 Code.emplace_back(MCInstBuilder(X86::MOV8rm) 2892 .addReg(X86::CL) 2893 .addReg(X86::RSI) 2894 .addImm(0) 2895 .addReg(X86::NoRegister) 2896 .addImm(0) 2897 .addReg(X86::NoRegister)); 2898 Code.emplace_back(MCInstBuilder(X86::MOV8mr) 2899 .addReg(X86::RDI) 2900 .addImm(0) 2901 .addReg(X86::NoRegister) 2902 .addImm(0) 2903 .addReg(X86::NoRegister) 2904 .addReg(X86::CL)); 2905 Code.emplace_back(MCInstBuilder(X86::MOV64rr) 2906 .addReg(X86::RAX) 2907 .addReg(X86::RDI)); 2908 return Code; 2909 } 2910 2911 InstructionListType createCmpJE(MCPhysReg RegNo, int64_t Imm, 2912 const MCSymbol *Target, 2913 MCContext *Ctx) const override { 2914 InstructionListType Code; 2915 Code.emplace_back(MCInstBuilder(X86::CMP64ri8) 2916 .addReg(RegNo) 2917 .addImm(Imm)); 2918 Code.emplace_back(MCInstBuilder(X86::JCC_1) 2919 .addExpr(MCSymbolRefExpr::create( 2920 Target, MCSymbolRefExpr::VK_None, *Ctx)) 2921 .addImm(X86::COND_E)); 2922 return Code; 2923 } 2924 2925 Optional<Relocation> 2926 createRelocation(const MCFixup &Fixup, 2927 const MCAsmBackend &MAB) const override { 2928 const MCFixupKindInfo &FKI = MAB.getFixupKindInfo(Fixup.getKind()); 2929 2930 assert(FKI.TargetOffset == 0 && "0-bit relocation offset expected"); 2931 const uint64_t RelOffset = Fixup.getOffset(); 2932 2933 uint64_t RelType; 2934 if (FKI.Flags & MCFixupKindInfo::FKF_IsPCRel) { 2935 switch (FKI.TargetSize) { 2936 default: 2937 return NoneType(); 2938 case 8: RelType = ELF::R_X86_64_PC8; break; 2939 case 16: RelType = ELF::R_X86_64_PC16; break; 2940 case 32: RelType = ELF::R_X86_64_PC32; break; 2941 case 64: RelType = ELF::R_X86_64_PC64; break; 2942 } 2943 } else { 2944 switch (FKI.TargetSize) { 2945 default: 2946 return NoneType(); 2947 case 8: RelType = ELF::R_X86_64_8; break; 2948 case 16: RelType = ELF::R_X86_64_16; break; 2949 case 32: RelType = ELF::R_X86_64_32; break; 2950 case 64: RelType = ELF::R_X86_64_64; break; 2951 } 2952 } 2953 2954 // Extract a symbol and an addend out of the fixup value expression. 2955 // 2956 // Only the following limited expression types are supported: 2957 // Symbol + Addend 2958 // Symbol 2959 uint64_t Addend = 0; 2960 MCSymbol *Symbol = nullptr; 2961 const MCExpr *ValueExpr = Fixup.getValue(); 2962 if (ValueExpr->getKind() == MCExpr::Binary) { 2963 const auto *BinaryExpr = cast<MCBinaryExpr>(ValueExpr); 2964 assert(BinaryExpr->getOpcode() == MCBinaryExpr::Add && 2965 "unexpected binary expression"); 2966 const MCExpr *LHS = BinaryExpr->getLHS(); 2967 assert(LHS->getKind() == MCExpr::SymbolRef && "unexpected LHS"); 2968 Symbol = const_cast<MCSymbol *>(this->getTargetSymbol(LHS)); 2969 const MCExpr *RHS = BinaryExpr->getRHS(); 2970 assert(RHS->getKind() == MCExpr::Constant && "unexpected RHS"); 2971 Addend = cast<MCConstantExpr>(RHS)->getValue(); 2972 } else { 2973 assert(ValueExpr->getKind() == MCExpr::SymbolRef && "unexpected value"); 2974 Symbol = const_cast<MCSymbol *>(this->getTargetSymbol(ValueExpr)); 2975 } 2976 2977 return Relocation({RelOffset, Symbol, RelType, Addend, 0}); 2978 } 2979 2980 bool replaceImmWithSymbolRef(MCInst &Inst, const MCSymbol *Symbol, 2981 int64_t Addend, MCContext *Ctx, int64_t &Value, 2982 uint64_t RelType) const override { 2983 unsigned ImmOpNo = -1U; 2984 2985 for (unsigned Index = 0; 2986 Index < MCPlus::getNumPrimeOperands(Inst); ++Index) { 2987 if (Inst.getOperand(Index).isImm()) { 2988 ImmOpNo = Index; 2989 // TODO: this is a bit hacky. It finds the correct operand by 2990 // searching for a specific immediate value. If no value is 2991 // provided it defaults to the last immediate operand found. 2992 // This could lead to unexpected results if the instruction 2993 // has more than one immediate with the same value. 2994 if (Inst.getOperand(ImmOpNo).getImm() == Value) 2995 break; 2996 } 2997 } 2998 2999 if (ImmOpNo == -1U) 3000 return false; 3001 3002 Value = Inst.getOperand(ImmOpNo).getImm(); 3003 3004 setOperandToSymbolRef(Inst, ImmOpNo, Symbol, Addend, Ctx, RelType); 3005 3006 return true; 3007 } 3008 3009 bool replaceRegWithImm(MCInst &Inst, unsigned Register, 3010 int64_t Imm) const override { 3011 3012 enum CheckSignExt : uint8_t { 3013 NOCHECK = 0, 3014 CHECK8, 3015 CHECK32, 3016 }; 3017 3018 using CheckList = std::vector<std::pair<CheckSignExt, unsigned>>; 3019 struct InstInfo { 3020 // Size in bytes that Inst loads from memory. 3021 uint8_t DataSize; 3022 3023 // True when the target operand has to be duplicated because the opcode 3024 // expects a LHS operand. 3025 bool HasLHS; 3026 3027 // List of checks and corresponding opcodes to be used. We try to use the 3028 // smallest possible immediate value when various sizes are available, 3029 // hence we may need to check whether a larger constant fits in a smaller 3030 // immediate. 3031 CheckList Checks; 3032 }; 3033 3034 InstInfo I; 3035 3036 switch (Inst.getOpcode()) { 3037 default: { 3038 switch (getPushSize(Inst)) { 3039 3040 case 2: I = {2, false, {{CHECK8, X86::PUSH16i8}, {NOCHECK, X86::PUSHi16}}}; break; 3041 case 4: I = {4, false, {{CHECK8, X86::PUSH32i8}, {NOCHECK, X86::PUSHi32}}}; break; 3042 case 8: I = {8, false, {{CHECK8, X86::PUSH64i8}, 3043 {CHECK32, X86::PUSH64i32}, 3044 {NOCHECK, Inst.getOpcode()}}}; break; 3045 default: return false; 3046 } 3047 break; 3048 } 3049 3050 // MOV 3051 case X86::MOV8rr: I = {1, false, {{NOCHECK, X86::MOV8ri}}}; break; 3052 case X86::MOV16rr: I = {2, false, {{NOCHECK, X86::MOV16ri}}}; break; 3053 case X86::MOV32rr: I = {4, false, {{NOCHECK, X86::MOV32ri}}}; break; 3054 case X86::MOV64rr: I = {8, false, {{CHECK32, X86::MOV64ri32}, 3055 {NOCHECK, X86::MOV64ri}}}; break; 3056 3057 case X86::MOV8mr: I = {1, false, {{NOCHECK, X86::MOV8mi}}}; break; 3058 case X86::MOV16mr: I = {2, false, {{NOCHECK, X86::MOV16mi}}}; break; 3059 case X86::MOV32mr: I = {4, false, {{NOCHECK, X86::MOV32mi}}}; break; 3060 case X86::MOV64mr: I = {8, false, {{CHECK32, X86::MOV64mi32}, 3061 {NOCHECK, X86::MOV64mr}}}; break; 3062 3063 // MOVZX 3064 case X86::MOVZX16rr8: I = {1, false, {{NOCHECK, X86::MOV16ri}}}; break; 3065 case X86::MOVZX32rr8: I = {1, false, {{NOCHECK, X86::MOV32ri}}}; break; 3066 case X86::MOVZX32rr16: I = {2, false, {{NOCHECK, X86::MOV32ri}}}; break; 3067 3068 // CMP 3069 case X86::CMP8rr: I = {1, false, {{NOCHECK, X86::CMP8ri}}}; break; 3070 case X86::CMP16rr: I = {2, false, {{CHECK8, X86::CMP16ri8}, 3071 {NOCHECK, X86::CMP16ri}}}; break; 3072 case X86::CMP32rr: I = {4, false, {{CHECK8, X86::CMP32ri8}, 3073 {NOCHECK, X86::CMP32ri}}}; break; 3074 case X86::CMP64rr: I = {8, false, {{CHECK8, X86::CMP64ri8}, 3075 {CHECK32, X86::CMP64ri32}, 3076 {NOCHECK, X86::CMP64rr}}}; break; 3077 3078 // TEST 3079 case X86::TEST8rr: I = {1, false, {{NOCHECK, X86::TEST8ri}}}; break; 3080 case X86::TEST16rr: I = {2, false, {{NOCHECK, X86::TEST16ri}}}; break; 3081 case X86::TEST32rr: I = {4, false, {{NOCHECK, X86::TEST32ri}}}; break; 3082 case X86::TEST64rr: I = {8, false, {{CHECK32, X86::TEST64ri32}, 3083 {NOCHECK, X86::TEST64rr}}}; break; 3084 3085 // ADD 3086 case X86::ADD8rr: I = {1, true, {{NOCHECK, X86::ADD8ri}}}; break; 3087 case X86::ADD16rr: I = {2, true, {{CHECK8, X86::ADD16ri8}, 3088 {NOCHECK, X86::ADD16ri}}}; break; 3089 case X86::ADD32rr: I = {4, true, {{CHECK8, X86::ADD32ri8}, 3090 {NOCHECK, X86::ADD32ri}}}; break; 3091 case X86::ADD64rr: I = {8, true, {{CHECK8, X86::ADD64ri8}, 3092 {CHECK32, X86::ADD64ri32}, 3093 {NOCHECK, X86::ADD64rr}}}; break; 3094 3095 // SUB 3096 case X86::SUB8rr: I = {1, true, {{NOCHECK, X86::SUB8ri}}}; break; 3097 case X86::SUB16rr: I = {2, true, {{CHECK8, X86::SUB16ri8}, 3098 {NOCHECK, X86::SUB16ri}}}; break; 3099 case X86::SUB32rr: I = {4, true, {{CHECK8, X86::SUB32ri8}, 3100 {NOCHECK, X86::SUB32ri}}}; break; 3101 case X86::SUB64rr: I = {8, true, {{CHECK8, X86::SUB64ri8}, 3102 {CHECK32, X86::SUB64ri32}, 3103 {NOCHECK, X86::SUB64rr}}}; break; 3104 3105 // AND 3106 case X86::AND8rr: I = {1, true, {{NOCHECK, X86::AND8ri}}}; break; 3107 case X86::AND16rr: I = {2, true, {{CHECK8, X86::AND16ri8}, 3108 {NOCHECK, X86::AND16ri}}}; break; 3109 case X86::AND32rr: I = {4, true, {{CHECK8, X86::AND32ri8}, 3110 {NOCHECK, X86::AND32ri}}}; break; 3111 case X86::AND64rr: I = {8, true, {{CHECK8, X86::AND64ri8}, 3112 {CHECK32, X86::AND64ri32}, 3113 {NOCHECK, X86::AND64rr}}}; break; 3114 3115 // OR 3116 case X86::OR8rr: I = {1, true, {{NOCHECK, X86::OR8ri}}}; break; 3117 case X86::OR16rr: I = {2, true, {{CHECK8, X86::OR16ri8}, 3118 {NOCHECK, X86::OR16ri}}}; break; 3119 case X86::OR32rr: I = {4, true, {{CHECK8, X86::OR32ri8}, 3120 {NOCHECK, X86::OR32ri}}}; break; 3121 case X86::OR64rr: I = {8, true, {{CHECK8, X86::OR64ri8}, 3122 {CHECK32, X86::OR64ri32}, 3123 {NOCHECK, X86::OR64rr}}}; break; 3124 3125 // XOR 3126 case X86::XOR8rr: I = {1, true, {{NOCHECK, X86::XOR8ri}}}; break; 3127 case X86::XOR16rr: I = {2, true, {{CHECK8, X86::XOR16ri8}, 3128 {NOCHECK, X86::XOR16ri}}}; break; 3129 case X86::XOR32rr: I = {4, true, {{CHECK8, X86::XOR32ri8}, 3130 {NOCHECK, X86::XOR32ri}}}; break; 3131 case X86::XOR64rr: I = {8, true, {{CHECK8, X86::XOR64ri8}, 3132 {CHECK32, X86::XOR64ri32}, 3133 {NOCHECK, X86::XOR64rr}}}; break; 3134 } 3135 3136 // Compute the new opcode. 3137 unsigned NewOpcode = 0; 3138 for (const std::pair<CheckSignExt, unsigned> &Check : I.Checks) { 3139 NewOpcode = Check.second; 3140 if (Check.first == NOCHECK) 3141 break; 3142 if (Check.first == CHECK8 && Imm >= std::numeric_limits<int8_t>::min() && 3143 Imm <= std::numeric_limits<int8_t>::max()) 3144 break; 3145 if (Check.first == CHECK32 && 3146 Imm >= std::numeric_limits<int32_t>::min() && 3147 Imm <= std::numeric_limits<int32_t>::max()) 3148 break; 3149 } 3150 if (NewOpcode == Inst.getOpcode()) 3151 return false; 3152 3153 const MCInstrDesc &InstDesc = Info->get(Inst.getOpcode()); 3154 3155 unsigned NumFound = 0; 3156 for (unsigned Index = InstDesc.getNumDefs() + (I.HasLHS ? 1 : 0), 3157 E = InstDesc.getNumOperands(); Index != E; ++Index) 3158 if (Inst.getOperand(Index).isReg() && 3159 Inst.getOperand(Index).getReg() == Register) 3160 NumFound++; 3161 3162 if (NumFound != 1) 3163 return false; 3164 3165 // Iterate backwards to replace the src register before the src/dest 3166 // register as in AND, ADD, and SUB Only iterate through src operands that 3167 // arent also dest operands 3168 for (unsigned Index = InstDesc.getNumOperands() - 1, 3169 E = InstDesc.getNumDefs() + (I.HasLHS ? 0 : -1); 3170 Index != E; --Index) { 3171 if (!Inst.getOperand(Index).isReg() || 3172 Inst.getOperand(Index).getReg() != Register) 3173 continue; 3174 MCOperand NewOperand = MCOperand::createImm(Imm); 3175 Inst.getOperand(Index) = NewOperand; 3176 break; 3177 } 3178 3179 Inst.setOpcode(NewOpcode); 3180 3181 return true; 3182 } 3183 3184 bool replaceRegWithReg(MCInst &Inst, unsigned ToReplace, 3185 unsigned ReplaceWith) const override { 3186 3187 // Get the HasLHS value so that iteration can be done 3188 bool HasLHS; 3189 if (isAND(Inst.getOpcode()) || isADD(Inst.getOpcode()) || isSUB(Inst)) { 3190 HasLHS = true; 3191 } else if (isPop(Inst) || isPush(Inst) || isCMP(Inst.getOpcode()) || 3192 isTEST(Inst.getOpcode())) { 3193 HasLHS = false; 3194 } else { 3195 switch (Inst.getOpcode()) { 3196 case X86::MOV8rr: 3197 case X86::MOV8rm: 3198 case X86::MOV8mr: 3199 case X86::MOV8ri: 3200 case X86::MOV16rr: 3201 case X86::MOV16rm: 3202 case X86::MOV16mr: 3203 case X86::MOV16ri: 3204 case X86::MOV32rr: 3205 case X86::MOV32rm: 3206 case X86::MOV32mr: 3207 case X86::MOV32ri: 3208 case X86::MOV64rr: 3209 case X86::MOV64rm: 3210 case X86::MOV64mr: 3211 case X86::MOV64ri: 3212 case X86::MOVZX16rr8: 3213 case X86::MOVZX32rr8: 3214 case X86::MOVZX32rr16: 3215 case X86::MOVSX32rm8: 3216 case X86::MOVSX32rr8: 3217 case X86::MOVSX64rm32: 3218 case X86::LEA64r: 3219 HasLHS = false; 3220 break; 3221 default: 3222 return false; 3223 } 3224 } 3225 3226 const MCInstrDesc &InstDesc = Info->get(Inst.getOpcode()); 3227 3228 bool FoundOne = false; 3229 3230 // Iterate only through src operands that arent also dest operands 3231 for (unsigned Index = InstDesc.getNumDefs() + (HasLHS ? 1 : 0), 3232 E = InstDesc.getNumOperands(); 3233 Index != E; ++Index) { 3234 BitVector RegAliases = getAliases(ToReplace, true); 3235 if (!Inst.getOperand(Index).isReg() || 3236 !RegAliases.test(Inst.getOperand(Index).getReg())) 3237 continue; 3238 // Resize register if needed 3239 unsigned SizedReplaceWith = getAliasSized( 3240 ReplaceWith, getRegSize(Inst.getOperand(Index).getReg())); 3241 MCOperand NewOperand = MCOperand::createReg(SizedReplaceWith); 3242 Inst.getOperand(Index) = NewOperand; 3243 FoundOne = true; 3244 } 3245 3246 // Return true if at least one operand was replaced 3247 return FoundOne; 3248 } 3249 3250 bool createUncondBranch(MCInst &Inst, const MCSymbol *TBB, 3251 MCContext *Ctx) const override { 3252 Inst.setOpcode(X86::JMP_1); 3253 Inst.addOperand(MCOperand::createExpr( 3254 MCSymbolRefExpr::create(TBB, MCSymbolRefExpr::VK_None, *Ctx))); 3255 return true; 3256 } 3257 3258 bool createCall(MCInst &Inst, const MCSymbol *Target, 3259 MCContext *Ctx) override { 3260 Inst.setOpcode(X86::CALL64pcrel32); 3261 Inst.addOperand(MCOperand::createExpr( 3262 MCSymbolRefExpr::create(Target, MCSymbolRefExpr::VK_None, *Ctx))); 3263 return true; 3264 } 3265 3266 bool createTailCall(MCInst &Inst, const MCSymbol *Target, 3267 MCContext *Ctx) override { 3268 return createDirectCall(Inst, Target, Ctx, /*IsTailCall*/ true); 3269 } 3270 3271 void createLongTailCall(InstructionListType &Seq, const MCSymbol *Target, 3272 MCContext *Ctx) override { 3273 Seq.clear(); 3274 Seq.emplace_back(); 3275 createDirectCall(Seq.back(), Target, Ctx, /*IsTailCall*/ true); 3276 } 3277 3278 bool createTrap(MCInst &Inst) const override { 3279 Inst.clear(); 3280 Inst.setOpcode(X86::TRAP); 3281 return true; 3282 } 3283 3284 bool reverseBranchCondition(MCInst &Inst, const MCSymbol *TBB, 3285 MCContext *Ctx) const override { 3286 unsigned InvCC = getInvertedCondCode(getCondCode(Inst)); 3287 assert(InvCC != X86::COND_INVALID && "invalid branch instruction"); 3288 Inst.getOperand(Info->get(Inst.getOpcode()).NumOperands - 1).setImm(InvCC); 3289 Inst.getOperand(0) = MCOperand::createExpr( 3290 MCSymbolRefExpr::create(TBB, MCSymbolRefExpr::VK_None, *Ctx)); 3291 return true; 3292 } 3293 3294 bool replaceBranchCondition(MCInst &Inst, const MCSymbol *TBB, MCContext *Ctx, 3295 unsigned CC) const override { 3296 if (CC == X86::COND_INVALID) 3297 return false; 3298 Inst.getOperand(Info->get(Inst.getOpcode()).NumOperands - 1).setImm(CC); 3299 Inst.getOperand(0) = MCOperand::createExpr( 3300 MCSymbolRefExpr::create(TBB, MCSymbolRefExpr::VK_None, *Ctx)); 3301 return true; 3302 } 3303 3304 unsigned getCanonicalBranchCondCode(unsigned CC) const override { 3305 switch (CC) { 3306 default: return X86::COND_INVALID; 3307 3308 case X86::COND_E: return X86::COND_E; 3309 case X86::COND_NE: return X86::COND_E; 3310 3311 case X86::COND_L: return X86::COND_L; 3312 case X86::COND_GE: return X86::COND_L; 3313 3314 case X86::COND_LE: return X86::COND_G; 3315 case X86::COND_G: return X86::COND_G; 3316 3317 case X86::COND_B: return X86::COND_B; 3318 case X86::COND_AE: return X86::COND_B; 3319 3320 case X86::COND_BE: return X86::COND_A; 3321 case X86::COND_A: return X86::COND_A; 3322 3323 case X86::COND_S: return X86::COND_S; 3324 case X86::COND_NS: return X86::COND_S; 3325 3326 case X86::COND_P: return X86::COND_P; 3327 case X86::COND_NP: return X86::COND_P; 3328 3329 case X86::COND_O: return X86::COND_O; 3330 case X86::COND_NO: return X86::COND_O; 3331 } 3332 } 3333 3334 bool replaceBranchTarget(MCInst &Inst, const MCSymbol *TBB, 3335 MCContext *Ctx) const override { 3336 assert((isCall(Inst) || isBranch(Inst)) && !isIndirectBranch(Inst) && 3337 "Invalid instruction"); 3338 Inst.getOperand(0) = MCOperand::createExpr( 3339 MCSymbolRefExpr::create(TBB, MCSymbolRefExpr::VK_None, *Ctx)); 3340 return true; 3341 } 3342 3343 MCPhysReg getX86R11() const override { 3344 return X86::R11; 3345 } 3346 3347 MCPhysReg getNoRegister() const override { 3348 return X86::NoRegister; 3349 } 3350 3351 MCPhysReg getIntArgRegister(unsigned ArgNo) const override { 3352 // FIXME: this should depend on the calling convention. 3353 switch (ArgNo) { 3354 case 0: return X86::RDI; 3355 case 1: return X86::RSI; 3356 case 2: return X86::RDX; 3357 case 3: return X86::RCX; 3358 case 4: return X86::R8; 3359 case 5: return X86::R9; 3360 default: return getNoRegister(); 3361 } 3362 } 3363 3364 void createPause(MCInst &Inst) const override { 3365 Inst.clear(); 3366 Inst.setOpcode(X86::PAUSE); 3367 } 3368 3369 void createLfence(MCInst &Inst) const override { 3370 Inst.clear(); 3371 Inst.setOpcode(X86::LFENCE); 3372 } 3373 3374 bool createDirectCall(MCInst &Inst, const MCSymbol *Target, MCContext *Ctx, 3375 bool IsTailCall) override { 3376 Inst.clear(); 3377 Inst.setOpcode(IsTailCall ? X86::JMP_4 : X86::CALL64pcrel32); 3378 Inst.addOperand(MCOperand::createExpr( 3379 MCSymbolRefExpr::create(Target, MCSymbolRefExpr::VK_None, *Ctx))); 3380 if (IsTailCall) 3381 setTailCall(Inst); 3382 return true; 3383 } 3384 3385 void createShortJmp(InstructionListType &Seq, const MCSymbol *Target, 3386 MCContext *Ctx, bool IsTailCall) override { 3387 Seq.clear(); 3388 MCInst Inst; 3389 Inst.setOpcode(X86::JMP_1); 3390 Inst.addOperand(MCOperand::createExpr( 3391 MCSymbolRefExpr::create(Target, MCSymbolRefExpr::VK_None, *Ctx))); 3392 if (IsTailCall) 3393 setTailCall(Inst); 3394 Seq.emplace_back(Inst); 3395 } 3396 3397 bool isConditionalMove(const MCInst &Inst) const override { 3398 unsigned OpCode = Inst.getOpcode(); 3399 return (OpCode == X86::CMOV16rr || OpCode == X86::CMOV32rr || 3400 OpCode == X86::CMOV64rr); 3401 } 3402 3403 bool isBranchOnMem(const MCInst &Inst) const override { 3404 unsigned OpCode = Inst.getOpcode(); 3405 if (OpCode == X86::CALL64m || (OpCode == X86::JMP32m && isTailCall(Inst)) || 3406 OpCode == X86::JMP64m) 3407 return true; 3408 3409 return false; 3410 } 3411 3412 bool isBranchOnReg(const MCInst &Inst) const override { 3413 unsigned OpCode = Inst.getOpcode(); 3414 if (OpCode == X86::CALL64r || (OpCode == X86::JMP32r && isTailCall(Inst)) || 3415 OpCode == X86::JMP64r) 3416 return true; 3417 3418 return false; 3419 } 3420 3421 void createPushRegister(MCInst &Inst, MCPhysReg Reg, 3422 unsigned Size) const override { 3423 Inst.clear(); 3424 unsigned NewOpcode = 0; 3425 if (Reg == X86::EFLAGS) { 3426 switch (Size) { 3427 case 2: NewOpcode = X86::PUSHF16; break; 3428 case 4: NewOpcode = X86::PUSHF32; break; 3429 case 8: NewOpcode = X86::PUSHF64; break; 3430 default: 3431 assert(false); 3432 } 3433 Inst.setOpcode(NewOpcode); 3434 return; 3435 } 3436 switch (Size) { 3437 case 2: NewOpcode = X86::PUSH16r; break; 3438 case 4: NewOpcode = X86::PUSH32r; break; 3439 case 8: NewOpcode = X86::PUSH64r; break; 3440 default: 3441 assert(false); 3442 } 3443 Inst.setOpcode(NewOpcode); 3444 Inst.addOperand(MCOperand::createReg(Reg)); 3445 } 3446 3447 void createPopRegister(MCInst &Inst, MCPhysReg Reg, 3448 unsigned Size) const override { 3449 Inst.clear(); 3450 unsigned NewOpcode = 0; 3451 if (Reg == X86::EFLAGS) { 3452 switch (Size) { 3453 case 2: NewOpcode = X86::POPF16; break; 3454 case 4: NewOpcode = X86::POPF32; break; 3455 case 8: NewOpcode = X86::POPF64; break; 3456 default: 3457 assert(false); 3458 } 3459 Inst.setOpcode(NewOpcode); 3460 return; 3461 } 3462 switch (Size) { 3463 case 2: NewOpcode = X86::POP16r; break; 3464 case 4: NewOpcode = X86::POP32r; break; 3465 case 8: NewOpcode = X86::POP64r; break; 3466 default: 3467 assert(false); 3468 } 3469 Inst.setOpcode(NewOpcode); 3470 Inst.addOperand(MCOperand::createReg(Reg)); 3471 } 3472 3473 void createPushFlags(MCInst &Inst, unsigned Size) const override { 3474 return createPushRegister(Inst, X86::EFLAGS, Size); 3475 } 3476 3477 void createPopFlags(MCInst &Inst, unsigned Size) const override { 3478 return createPopRegister(Inst, X86::EFLAGS, Size); 3479 } 3480 3481 void createAddRegImm(MCInst &Inst, MCPhysReg Reg, int64_t Value, 3482 unsigned Size) const { 3483 unsigned int Opcode; 3484 switch (Size) { 3485 case 1: Opcode = X86::ADD8ri; break; 3486 case 2: Opcode = X86::ADD16ri; break; 3487 case 4: Opcode = X86::ADD32ri; break; 3488 default: 3489 llvm_unreachable("Unexpected size"); 3490 } 3491 Inst.setOpcode(Opcode); 3492 Inst.clear(); 3493 Inst.addOperand(MCOperand::createReg(Reg)); 3494 Inst.addOperand(MCOperand::createReg(Reg)); 3495 Inst.addOperand(MCOperand::createImm(Value)); 3496 } 3497 3498 void createClearRegWithNoEFlagsUpdate(MCInst &Inst, MCPhysReg Reg, 3499 unsigned Size) const { 3500 unsigned int Opcode; 3501 switch (Size) { 3502 case 1: Opcode = X86::MOV8ri; break; 3503 case 2: Opcode = X86::MOV16ri; break; 3504 case 4: Opcode = X86::MOV32ri; break; 3505 case 8: Opcode = X86::MOV64ri; break; 3506 default: 3507 llvm_unreachable("Unexpected size"); 3508 } 3509 Inst.setOpcode(Opcode); 3510 Inst.clear(); 3511 Inst.addOperand(MCOperand::createReg(Reg)); 3512 Inst.addOperand(MCOperand::createImm(0)); 3513 } 3514 3515 void createX86SaveOVFlagToRegister(MCInst &Inst, MCPhysReg Reg) const { 3516 Inst.setOpcode(X86::SETCCr); 3517 Inst.clear(); 3518 Inst.addOperand(MCOperand::createReg(Reg)); 3519 Inst.addOperand(MCOperand::createImm(X86::COND_O)); 3520 } 3521 3522 void createX86Lahf(MCInst &Inst) const { 3523 Inst.setOpcode(X86::LAHF); 3524 Inst.clear(); 3525 } 3526 3527 void createX86Sahf(MCInst &Inst) const { 3528 Inst.setOpcode(X86::SAHF); 3529 Inst.clear(); 3530 } 3531 3532 void createInstrIncMemory(InstructionListType &Instrs, const MCSymbol *Target, 3533 MCContext *Ctx, bool IsLeaf) const override { 3534 unsigned int I = 0; 3535 3536 Instrs.resize(IsLeaf ? 13 : 11); 3537 // Don't clobber application red zone (ABI dependent) 3538 if (IsLeaf) 3539 createStackPointerIncrement(Instrs[I++], 128, 3540 /*NoFlagsClobber=*/true); 3541 3542 // Performance improvements based on the optimization discussed at 3543 // https://reviews.llvm.org/D6629 3544 // LAHF/SAHF are used instead of PUSHF/POPF 3545 // PUSHF 3546 createPushRegister(Instrs[I++], X86::RAX, 8); 3547 createClearRegWithNoEFlagsUpdate(Instrs[I++], X86::RAX, 8); 3548 createX86Lahf(Instrs[I++]); 3549 createPushRegister(Instrs[I++], X86::RAX, 8); 3550 createClearRegWithNoEFlagsUpdate(Instrs[I++], X86::RAX, 8); 3551 createX86SaveOVFlagToRegister(Instrs[I++], X86::AL); 3552 // LOCK INC 3553 createIncMemory(Instrs[I++], Target, Ctx); 3554 // POPF 3555 createAddRegImm(Instrs[I++], X86::AL, 127, 1); 3556 createPopRegister(Instrs[I++], X86::RAX, 8); 3557 createX86Sahf(Instrs[I++]); 3558 createPopRegister(Instrs[I++], X86::RAX, 8); 3559 3560 if (IsLeaf) 3561 createStackPointerDecrement(Instrs[I], 128, 3562 /*NoFlagsClobber=*/true); 3563 } 3564 3565 void createSwap(MCInst &Inst, MCPhysReg Source, MCPhysReg MemBaseReg, 3566 int64_t Disp) const { 3567 Inst.setOpcode(X86::XCHG64rm); 3568 Inst.addOperand(MCOperand::createReg(Source)); 3569 Inst.addOperand(MCOperand::createReg(Source)); 3570 Inst.addOperand(MCOperand::createReg(MemBaseReg)); // BaseReg 3571 Inst.addOperand(MCOperand::createImm(1)); // ScaleAmt 3572 Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // IndexReg 3573 Inst.addOperand(MCOperand::createImm(Disp)); // Displacement 3574 Inst.addOperand(MCOperand::createReg(X86::NoRegister));//AddrSegmentReg 3575 } 3576 3577 void createIndirectBranch(MCInst &Inst, MCPhysReg MemBaseReg, 3578 int64_t Disp) const { 3579 Inst.setOpcode(X86::JMP64m); 3580 Inst.addOperand(MCOperand::createReg(MemBaseReg)); // BaseReg 3581 Inst.addOperand(MCOperand::createImm(1)); // ScaleAmt 3582 Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // IndexReg 3583 Inst.addOperand(MCOperand::createImm(Disp)); // Displacement 3584 Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // AddrSegmentReg 3585 } 3586 3587 InstructionListType createInstrumentedIndirectCall(const MCInst &CallInst, 3588 bool TailCall, 3589 MCSymbol *HandlerFuncAddr, 3590 int CallSiteID, 3591 MCContext *Ctx) override { 3592 // Check if the target address expression used in the original indirect call 3593 // uses the stack pointer, which we are going to clobber. 3594 static BitVector SPAliases(getAliases(X86::RSP)); 3595 bool UsesSP = false; 3596 // Skip defs. 3597 for (unsigned I = Info->get(CallInst.getOpcode()).getNumDefs(), 3598 E = MCPlus::getNumPrimeOperands(CallInst); I != E; ++I) { 3599 const MCOperand &Operand = CallInst.getOperand(I); 3600 if (Operand.isReg() && SPAliases[Operand.getReg()]) { 3601 UsesSP = true; 3602 break; 3603 } 3604 } 3605 3606 InstructionListType Insts; 3607 MCPhysReg TempReg = getIntArgRegister(0); 3608 // Code sequence used to enter indirect call instrumentation helper: 3609 // push %rdi 3610 // add $8, %rsp ;; $rsp may be used in target, so fix it to prev val 3611 // movq target, %rdi ;; via convertIndirectCallTargetToLoad 3612 // sub $8, %rsp ;; restore correct stack value 3613 // push %rdi 3614 // movq $CallSiteID, %rdi 3615 // push %rdi 3616 // callq/jmp HandlerFuncAddr 3617 Insts.emplace_back(); 3618 createPushRegister(Insts.back(), TempReg, 8); 3619 if (UsesSP) { // Only adjust SP if we really need to 3620 Insts.emplace_back(); 3621 createStackPointerDecrement(Insts.back(), 8, /*NoFlagsClobber=*/false); 3622 } 3623 Insts.emplace_back(CallInst); 3624 // Insts.back() and CallInst now share the same annotation instruction. 3625 // Strip it from Insts.back(), only preserving tail call annotation. 3626 stripAnnotations(Insts.back(), /*KeepTC=*/true); 3627 convertIndirectCallToLoad(Insts.back(), TempReg); 3628 if (UsesSP) { 3629 Insts.emplace_back(); 3630 createStackPointerIncrement(Insts.back(), 8, /*NoFlagsClobber=*/false); 3631 } 3632 Insts.emplace_back(); 3633 createPushRegister(Insts.back(), TempReg, 8); 3634 Insts.emplace_back(); 3635 createLoadImmediate(Insts.back(), TempReg, CallSiteID); 3636 Insts.emplace_back(); 3637 createPushRegister(Insts.back(), TempReg, 8); 3638 Insts.emplace_back(); 3639 createDirectCall(Insts.back(), HandlerFuncAddr, Ctx, 3640 /*TailCall=*/TailCall); 3641 // Carry over metadata 3642 for (int I = MCPlus::getNumPrimeOperands(CallInst), 3643 E = CallInst.getNumOperands(); 3644 I != E; ++I) 3645 Insts.back().addOperand(CallInst.getOperand(I)); 3646 3647 return Insts; 3648 } 3649 3650 InstructionListType createInstrumentedIndCallHandlerExitBB() const override { 3651 const MCPhysReg TempReg = getIntArgRegister(0); 3652 // We just need to undo the sequence created for every ind call in 3653 // instrumentIndirectTarget(), which can be accomplished minimally with: 3654 // popfq 3655 // pop %rdi 3656 // add $16, %rsp 3657 // xchg (%rsp), %rdi 3658 // jmp *-8(%rsp) 3659 InstructionListType Insts(5); 3660 createPopFlags(Insts[0], 8); 3661 createPopRegister(Insts[1], TempReg, 8); 3662 createStackPointerDecrement(Insts[2], 16, /*NoFlagsClobber=*/false); 3663 createSwap(Insts[3], TempReg, X86::RSP, 0); 3664 createIndirectBranch(Insts[4], X86::RSP, -8); 3665 return Insts; 3666 } 3667 3668 InstructionListType 3669 createInstrumentedIndTailCallHandlerExitBB() const override { 3670 const MCPhysReg TempReg = getIntArgRegister(0); 3671 // Same thing as above, but for tail calls 3672 // popfq 3673 // add $16, %rsp 3674 // pop %rdi 3675 // jmp *-16(%rsp) 3676 InstructionListType Insts(4); 3677 createPopFlags(Insts[0], 8); 3678 createStackPointerDecrement(Insts[1], 16, /*NoFlagsClobber=*/false); 3679 createPopRegister(Insts[2], TempReg, 8); 3680 createIndirectBranch(Insts[3], X86::RSP, -16); 3681 return Insts; 3682 } 3683 3684 InstructionListType 3685 createInstrumentedIndCallHandlerEntryBB(const MCSymbol *InstrTrampoline, 3686 const MCSymbol *IndCallHandler, 3687 MCContext *Ctx) override { 3688 const MCPhysReg TempReg = getIntArgRegister(0); 3689 // Code sequence used to check whether InstrTampoline was initialized 3690 // and call it if so, returns via IndCallHandler. 3691 // pushfq 3692 // mov InstrTrampoline,%rdi 3693 // cmp $0x0,%rdi 3694 // je IndCallHandler 3695 // callq *%rdi 3696 // jmpq IndCallHandler 3697 InstructionListType Insts; 3698 Insts.emplace_back(); 3699 createPushFlags(Insts.back(), 8); 3700 Insts.emplace_back(); 3701 createMove(Insts.back(), InstrTrampoline, TempReg, Ctx); 3702 InstructionListType cmpJmp = createCmpJE(TempReg, 0, IndCallHandler, Ctx); 3703 Insts.insert(Insts.end(), cmpJmp.begin(), cmpJmp.end()); 3704 Insts.emplace_back(); 3705 Insts.back().setOpcode(X86::CALL64r); 3706 Insts.back().addOperand(MCOperand::createReg(TempReg)); 3707 Insts.emplace_back(); 3708 createDirectCall(Insts.back(), IndCallHandler, Ctx, /*IsTailCall*/ true); 3709 return Insts; 3710 } 3711 3712 InstructionListType createNumCountersGetter(MCContext *Ctx) const override { 3713 InstructionListType Insts(2); 3714 MCSymbol *NumLocs = Ctx->getOrCreateSymbol("__bolt_num_counters"); 3715 createMove(Insts[0], NumLocs, X86::EAX, Ctx); 3716 createReturn(Insts[1]); 3717 return Insts; 3718 } 3719 3720 InstructionListType 3721 createInstrLocationsGetter(MCContext *Ctx) const override { 3722 InstructionListType Insts(2); 3723 MCSymbol *Locs = Ctx->getOrCreateSymbol("__bolt_instr_locations"); 3724 createLea(Insts[0], Locs, X86::EAX, Ctx); 3725 createReturn(Insts[1]); 3726 return Insts; 3727 } 3728 3729 InstructionListType createInstrTablesGetter(MCContext *Ctx) const override { 3730 InstructionListType Insts(2); 3731 MCSymbol *Locs = Ctx->getOrCreateSymbol("__bolt_instr_tables"); 3732 createLea(Insts[0], Locs, X86::EAX, Ctx); 3733 createReturn(Insts[1]); 3734 return Insts; 3735 } 3736 3737 InstructionListType createInstrNumFuncsGetter(MCContext *Ctx) const override { 3738 InstructionListType Insts(2); 3739 MCSymbol *NumFuncs = Ctx->getOrCreateSymbol("__bolt_instr_num_funcs"); 3740 createMove(Insts[0], NumFuncs, X86::EAX, Ctx); 3741 createReturn(Insts[1]); 3742 return Insts; 3743 } 3744 3745 InstructionListType createSymbolTrampoline(const MCSymbol *TgtSym, 3746 MCContext *Ctx) const override { 3747 InstructionListType Insts(1); 3748 createUncondBranch(Insts[0], TgtSym, Ctx); 3749 return Insts; 3750 } 3751 3752 InstructionListType createDummyReturnFunction(MCContext *Ctx) const override { 3753 InstructionListType Insts(1); 3754 createReturn(Insts[0]); 3755 return Insts; 3756 } 3757 3758 BlocksVectorTy indirectCallPromotion( 3759 const MCInst &CallInst, 3760 const std::vector<std::pair<MCSymbol *, uint64_t>> &Targets, 3761 const std::vector<std::pair<MCSymbol *, uint64_t>> &VtableSyms, 3762 const std::vector<MCInst *> &MethodFetchInsns, 3763 const bool MinimizeCodeSize, 3764 MCContext *Ctx 3765 ) override { 3766 const bool IsTailCall = isTailCall(CallInst); 3767 const bool IsJumpTable = getJumpTable(CallInst) != 0; 3768 BlocksVectorTy Results; 3769 3770 // Label for the current code block. 3771 MCSymbol *NextTarget = nullptr; 3772 3773 // The join block which contains all the instructions following CallInst. 3774 // MergeBlock remains null if CallInst is a tail call. 3775 MCSymbol *MergeBlock = nullptr; 3776 3777 unsigned FuncAddrReg = X86::R10; 3778 3779 const bool LoadElim = !VtableSyms.empty(); 3780 assert((!LoadElim || VtableSyms.size() == Targets.size()) && 3781 "There must be a vtable entry for every method " 3782 "in the targets vector."); 3783 3784 if (MinimizeCodeSize && !LoadElim) { 3785 std::set<unsigned> UsedRegs; 3786 3787 for (unsigned int I = 0; I < MCPlus::getNumPrimeOperands(CallInst); ++I) { 3788 const MCOperand &Op = CallInst.getOperand(I); 3789 if (Op.isReg()) 3790 UsedRegs.insert(Op.getReg()); 3791 } 3792 3793 if (UsedRegs.count(X86::R10) == 0) 3794 FuncAddrReg = X86::R10; 3795 else if (UsedRegs.count(X86::R11) == 0) 3796 FuncAddrReg = X86::R11; 3797 else 3798 return Results; 3799 } 3800 3801 const auto jumpToMergeBlock = [&](InstructionListType &NewCall) { 3802 assert(MergeBlock); 3803 NewCall.push_back(CallInst); 3804 MCInst &Merge = NewCall.back(); 3805 Merge.clear(); 3806 createUncondBranch(Merge, MergeBlock, Ctx); 3807 }; 3808 3809 for (unsigned int i = 0; i < Targets.size(); ++i) { 3810 Results.emplace_back(NextTarget, InstructionListType()); 3811 InstructionListType *NewCall = &Results.back().second; 3812 3813 if (MinimizeCodeSize && !LoadElim) { 3814 // Load the call target into FuncAddrReg. 3815 NewCall->push_back(CallInst); // Copy CallInst in order to get SMLoc 3816 MCInst &Target = NewCall->back(); 3817 Target.clear(); 3818 Target.setOpcode(X86::MOV64ri32); 3819 Target.addOperand(MCOperand::createReg(FuncAddrReg)); 3820 if (Targets[i].first) { 3821 // Is this OK? 3822 Target.addOperand( 3823 MCOperand::createExpr( 3824 MCSymbolRefExpr::create(Targets[i].first, 3825 MCSymbolRefExpr::VK_None, 3826 *Ctx))); 3827 } else { 3828 const uint64_t Addr = Targets[i].second; 3829 // Immediate address is out of sign extended 32 bit range. 3830 if (int64_t(Addr) != int64_t(int32_t(Addr))) 3831 return BlocksVectorTy(); 3832 3833 Target.addOperand(MCOperand::createImm(Addr)); 3834 } 3835 3836 // Compare current call target to a specific address. 3837 NewCall->push_back(CallInst); 3838 MCInst &Compare = NewCall->back(); 3839 Compare.clear(); 3840 if (isBranchOnReg(CallInst)) 3841 Compare.setOpcode(X86::CMP64rr); 3842 else if (CallInst.getOpcode() == X86::CALL64pcrel32) 3843 Compare.setOpcode(X86::CMP64ri32); 3844 else 3845 Compare.setOpcode(X86::CMP64rm); 3846 3847 Compare.addOperand(MCOperand::createReg(FuncAddrReg)); 3848 3849 // TODO: Would be preferable to only load this value once. 3850 for (unsigned i = 0; 3851 i < Info->get(CallInst.getOpcode()).getNumOperands(); 3852 ++i) 3853 if (!CallInst.getOperand(i).isInst()) 3854 Compare.addOperand(CallInst.getOperand(i)); 3855 } else { 3856 // Compare current call target to a specific address. 3857 NewCall->push_back(CallInst); 3858 MCInst &Compare = NewCall->back(); 3859 Compare.clear(); 3860 if (isBranchOnReg(CallInst)) 3861 Compare.setOpcode(X86::CMP64ri32); 3862 else 3863 Compare.setOpcode(X86::CMP64mi32); 3864 3865 // Original call address. 3866 for (unsigned i = 0; 3867 i < Info->get(CallInst.getOpcode()).getNumOperands(); 3868 ++i) 3869 if (!CallInst.getOperand(i).isInst()) 3870 Compare.addOperand(CallInst.getOperand(i)); 3871 3872 // Target address. 3873 if (Targets[i].first || LoadElim) { 3874 const MCSymbol *Sym = 3875 LoadElim ? VtableSyms[i].first : Targets[i].first; 3876 const uint64_t Addend = LoadElim ? VtableSyms[i].second : 0; 3877 3878 const MCExpr *Expr = MCSymbolRefExpr::create(Sym, *Ctx); 3879 3880 if (Addend) 3881 Expr = MCBinaryExpr::createAdd(Expr, 3882 MCConstantExpr::create(Addend, *Ctx), 3883 *Ctx); 3884 3885 Compare.addOperand(MCOperand::createExpr(Expr)); 3886 } else { 3887 const uint64_t Addr = Targets[i].second; 3888 // Immediate address is out of sign extended 32 bit range. 3889 if (int64_t(Addr) != int64_t(int32_t(Addr))) 3890 return BlocksVectorTy(); 3891 3892 Compare.addOperand(MCOperand::createImm(Addr)); 3893 } 3894 } 3895 3896 // jump to next target compare. 3897 NextTarget = 3898 Ctx->createNamedTempSymbol(); // generate label for the next block 3899 NewCall->push_back(CallInst); 3900 3901 if (IsJumpTable) { 3902 MCInst &Je = NewCall->back(); 3903 3904 // Jump to next compare if target addresses don't match. 3905 Je.clear(); 3906 Je.setOpcode(X86::JCC_1); 3907 if (Targets[i].first) 3908 Je.addOperand(MCOperand::createExpr( 3909 MCSymbolRefExpr::create(Targets[i].first, 3910 MCSymbolRefExpr::VK_None, 3911 *Ctx))); 3912 else 3913 Je.addOperand(MCOperand::createImm(Targets[i].second)); 3914 3915 Je.addOperand(MCOperand::createImm(X86::COND_E)); 3916 assert(!isInvoke(CallInst)); 3917 } else { 3918 MCInst &Jne = NewCall->back(); 3919 3920 // Jump to next compare if target addresses don't match. 3921 Jne.clear(); 3922 Jne.setOpcode(X86::JCC_1); 3923 Jne.addOperand(MCOperand::createExpr(MCSymbolRefExpr::create( 3924 NextTarget, MCSymbolRefExpr::VK_None, *Ctx))); 3925 Jne.addOperand(MCOperand::createImm(X86::COND_NE)); 3926 3927 // Call specific target directly. 3928 Results.emplace_back(Ctx->createNamedTempSymbol(), 3929 InstructionListType()); 3930 NewCall = &Results.back().second; 3931 NewCall->push_back(CallInst); 3932 MCInst &CallOrJmp = NewCall->back(); 3933 3934 CallOrJmp.clear(); 3935 3936 if (MinimizeCodeSize && !LoadElim) { 3937 CallOrJmp.setOpcode(IsTailCall ? X86::JMP32r : X86::CALL64r); 3938 CallOrJmp.addOperand(MCOperand::createReg(FuncAddrReg)); 3939 } else { 3940 CallOrJmp.setOpcode(IsTailCall ? X86::JMP_4 : X86::CALL64pcrel32); 3941 3942 if (Targets[i].first) 3943 CallOrJmp.addOperand(MCOperand::createExpr(MCSymbolRefExpr::create( 3944 Targets[i].first, MCSymbolRefExpr::VK_None, *Ctx))); 3945 else 3946 CallOrJmp.addOperand(MCOperand::createImm(Targets[i].second)); 3947 } 3948 if (IsTailCall) 3949 setTailCall(CallOrJmp); 3950 3951 if (CallOrJmp.getOpcode() == X86::CALL64r || 3952 CallOrJmp.getOpcode() == X86::CALL64pcrel32) { 3953 if (hasAnnotation(CallInst, "Offset")) 3954 // Annotated as duplicated call 3955 addAnnotation(CallOrJmp, "Offset", 3956 getAnnotationAs<uint32_t>(CallInst, "Offset")); 3957 } 3958 3959 if (isInvoke(CallInst) && !isInvoke(CallOrJmp)) { 3960 // Copy over any EH or GNU args size information from the original 3961 // call. 3962 Optional<MCPlus::MCLandingPad> EHInfo = getEHInfo(CallInst); 3963 if (EHInfo) 3964 addEHInfo(CallOrJmp, *EHInfo); 3965 int64_t GnuArgsSize = getGnuArgsSize(CallInst); 3966 if (GnuArgsSize >= 0) 3967 addGnuArgsSize(CallOrJmp, GnuArgsSize); 3968 } 3969 3970 if (!IsTailCall) { 3971 // The fallthrough block for the most common target should be 3972 // the merge block. 3973 if (i == 0) { 3974 // Fallthrough to merge block. 3975 MergeBlock = Ctx->createNamedTempSymbol(); 3976 } else { 3977 // Insert jump to the merge block if we are not doing a fallthrough. 3978 jumpToMergeBlock(*NewCall); 3979 } 3980 } 3981 } 3982 } 3983 3984 // Cold call block. 3985 Results.emplace_back(NextTarget, InstructionListType()); 3986 InstructionListType &NewCall = Results.back().second; 3987 for (const MCInst *Inst : MethodFetchInsns) 3988 if (Inst != &CallInst) 3989 NewCall.push_back(*Inst); 3990 NewCall.push_back(CallInst); 3991 3992 // Jump to merge block from cold call block 3993 if (!IsTailCall && !IsJumpTable) { 3994 jumpToMergeBlock(NewCall); 3995 3996 // Record merge block 3997 Results.emplace_back(MergeBlock, InstructionListType()); 3998 } 3999 4000 return Results; 4001 } 4002 4003 BlocksVectorTy jumpTablePromotion( 4004 const MCInst &IJmpInst, 4005 const std::vector<std::pair<MCSymbol *,uint64_t>> &Targets, 4006 const std::vector<MCInst *> &TargetFetchInsns, 4007 MCContext *Ctx 4008 ) const override { 4009 assert(getJumpTable(IJmpInst) != 0); 4010 uint16_t IndexReg = getAnnotationAs<uint16_t>(IJmpInst, "JTIndexReg"); 4011 if (IndexReg == 0) 4012 return BlocksVectorTy(); 4013 4014 BlocksVectorTy Results; 4015 4016 // Label for the current code block. 4017 MCSymbol *NextTarget = nullptr; 4018 4019 for (unsigned int i = 0; i < Targets.size(); ++i) { 4020 Results.emplace_back(NextTarget, InstructionListType()); 4021 InstructionListType *CurBB = &Results.back().second; 4022 4023 // Compare current index to a specific index. 4024 CurBB->emplace_back(MCInst()); 4025 MCInst &CompareInst = CurBB->back(); 4026 CompareInst.setLoc(IJmpInst.getLoc()); 4027 CompareInst.setOpcode(X86::CMP64ri32); 4028 CompareInst.addOperand(MCOperand::createReg(IndexReg)); 4029 4030 const uint64_t CaseIdx = Targets[i].second; 4031 // Immediate address is out of sign extended 32 bit range. 4032 if (int64_t(CaseIdx) != int64_t(int32_t(CaseIdx))) 4033 return BlocksVectorTy(); 4034 4035 CompareInst.addOperand(MCOperand::createImm(CaseIdx)); 4036 shortenInstruction(CompareInst); 4037 4038 // jump to next target compare. 4039 NextTarget = 4040 Ctx->createNamedTempSymbol(); // generate label for the next block 4041 CurBB->push_back(MCInst()); 4042 4043 MCInst &JEInst = CurBB->back(); 4044 JEInst.setLoc(IJmpInst.getLoc()); 4045 4046 // Jump to target if indices match 4047 JEInst.setOpcode(X86::JCC_1); 4048 JEInst.addOperand(MCOperand::createExpr(MCSymbolRefExpr::create( 4049 Targets[i].first, MCSymbolRefExpr::VK_None, *Ctx))); 4050 JEInst.addOperand(MCOperand::createImm(X86::COND_E)); 4051 } 4052 4053 // Cold call block. 4054 Results.emplace_back(NextTarget, InstructionListType()); 4055 InstructionListType &CurBB = Results.back().second; 4056 for (const MCInst *Inst : TargetFetchInsns) 4057 if (Inst != &IJmpInst) 4058 CurBB.push_back(*Inst); 4059 4060 CurBB.push_back(IJmpInst); 4061 4062 return Results; 4063 } 4064 4065 private: 4066 4067 bool createMove(MCInst &Inst, const MCSymbol *Src, unsigned Reg, 4068 MCContext *Ctx) const { 4069 Inst.setOpcode(X86::MOV64rm); 4070 Inst.addOperand(MCOperand::createReg(Reg)); 4071 Inst.addOperand(MCOperand::createReg(X86::RIP)); // BaseReg 4072 Inst.addOperand(MCOperand::createImm(1)); // ScaleAmt 4073 Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // IndexReg 4074 Inst.addOperand(MCOperand::createExpr( 4075 MCSymbolRefExpr::create(Src, MCSymbolRefExpr::VK_None, 4076 *Ctx))); // Displacement 4077 Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // AddrSegmentReg 4078 4079 return true; 4080 } 4081 4082 bool createLea(MCInst &Inst, const MCSymbol *Src, unsigned Reg, 4083 MCContext *Ctx) const { 4084 Inst.setOpcode(X86::LEA64r); 4085 Inst.addOperand(MCOperand::createReg(Reg)); 4086 Inst.addOperand(MCOperand::createReg(X86::RIP)); // BaseReg 4087 Inst.addOperand(MCOperand::createImm(1)); // ScaleAmt 4088 Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // IndexReg 4089 Inst.addOperand(MCOperand::createExpr( 4090 MCSymbolRefExpr::create(Src, MCSymbolRefExpr::VK_None, 4091 *Ctx))); // Displacement 4092 Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // AddrSegmentReg 4093 return true; 4094 } 4095 }; 4096 4097 } 4098 4099 namespace llvm { 4100 namespace bolt { 4101 4102 MCPlusBuilder *createX86MCPlusBuilder(const MCInstrAnalysis *Analysis, 4103 const MCInstrInfo *Info, 4104 const MCRegisterInfo *RegInfo) { 4105 return new X86MCPlusBuilder(Analysis, Info, RegInfo); 4106 } 4107 4108 } 4109 } 4110