1 //===- bolt/Core/Relocation.cpp - Object file relocations -----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the Relocation class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "bolt/Core/Relocation.h" 14 #include "llvm/MC/MCContext.h" 15 #include "llvm/MC/MCExpr.h" 16 #include "llvm/MC/MCStreamer.h" 17 #include "llvm/MC/MCSymbol.h" 18 #include "llvm/Object/ELF.h" 19 20 using namespace llvm; 21 using namespace bolt; 22 23 namespace ELFReserved { 24 enum { 25 R_RISCV_TPREL_I = 49, 26 R_RISCV_TPREL_S = 50, 27 }; 28 } // namespace ELFReserved 29 30 Triple::ArchType Relocation::Arch; 31 32 static bool isSupportedX86(uint64_t Type) { 33 switch (Type) { 34 default: 35 return false; 36 case ELF::R_X86_64_8: 37 case ELF::R_X86_64_16: 38 case ELF::R_X86_64_32: 39 case ELF::R_X86_64_32S: 40 case ELF::R_X86_64_64: 41 case ELF::R_X86_64_PC8: 42 case ELF::R_X86_64_PC32: 43 case ELF::R_X86_64_PC64: 44 case ELF::R_X86_64_PLT32: 45 case ELF::R_X86_64_GOTPC64: 46 case ELF::R_X86_64_GOTPCREL: 47 case ELF::R_X86_64_GOTTPOFF: 48 case ELF::R_X86_64_TPOFF32: 49 case ELF::R_X86_64_GOTPCRELX: 50 case ELF::R_X86_64_REX_GOTPCRELX: 51 return true; 52 } 53 } 54 55 static bool isSupportedAArch64(uint64_t Type) { 56 switch (Type) { 57 default: 58 return false; 59 case ELF::R_AARCH64_CALL26: 60 case ELF::R_AARCH64_JUMP26: 61 case ELF::R_AARCH64_TSTBR14: 62 case ELF::R_AARCH64_CONDBR19: 63 case ELF::R_AARCH64_ADR_PREL_LO21: 64 case ELF::R_AARCH64_ADR_PREL_PG_HI21: 65 case ELF::R_AARCH64_ADR_PREL_PG_HI21_NC: 66 case ELF::R_AARCH64_LDST64_ABS_LO12_NC: 67 case ELF::R_AARCH64_ADD_ABS_LO12_NC: 68 case ELF::R_AARCH64_LDST128_ABS_LO12_NC: 69 case ELF::R_AARCH64_LDST32_ABS_LO12_NC: 70 case ELF::R_AARCH64_LDST16_ABS_LO12_NC: 71 case ELF::R_AARCH64_LDST8_ABS_LO12_NC: 72 case ELF::R_AARCH64_ADR_GOT_PAGE: 73 case ELF::R_AARCH64_TLSDESC_ADR_PREL21: 74 case ELF::R_AARCH64_TLSDESC_ADR_PAGE21: 75 case ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: 76 case ELF::R_AARCH64_TLSLE_ADD_TPREL_HI12: 77 case ELF::R_AARCH64_TLSLE_ADD_TPREL_LO12_NC: 78 case ELF::R_AARCH64_LD64_GOT_LO12_NC: 79 case ELF::R_AARCH64_TLSDESC_LD64_LO12: 80 case ELF::R_AARCH64_TLSDESC_ADD_LO12: 81 case ELF::R_AARCH64_TLSDESC_CALL: 82 case ELF::R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: 83 case ELF::R_AARCH64_PREL16: 84 case ELF::R_AARCH64_PREL32: 85 case ELF::R_AARCH64_PREL64: 86 case ELF::R_AARCH64_ABS16: 87 case ELF::R_AARCH64_ABS32: 88 case ELF::R_AARCH64_ABS64: 89 case ELF::R_AARCH64_MOVW_UABS_G0: 90 case ELF::R_AARCH64_MOVW_UABS_G0_NC: 91 case ELF::R_AARCH64_MOVW_UABS_G1: 92 case ELF::R_AARCH64_MOVW_UABS_G1_NC: 93 case ELF::R_AARCH64_MOVW_UABS_G2: 94 case ELF::R_AARCH64_MOVW_UABS_G2_NC: 95 case ELF::R_AARCH64_MOVW_UABS_G3: 96 return true; 97 } 98 } 99 100 static bool isSupportedRISCV(uint64_t Type) { 101 switch (Type) { 102 default: 103 return false; 104 case ELF::R_RISCV_JAL: 105 case ELF::R_RISCV_CALL: 106 case ELF::R_RISCV_CALL_PLT: 107 case ELF::R_RISCV_BRANCH: 108 case ELF::R_RISCV_RELAX: 109 case ELF::R_RISCV_GOT_HI20: 110 case ELF::R_RISCV_PCREL_HI20: 111 case ELF::R_RISCV_PCREL_LO12_I: 112 case ELF::R_RISCV_PCREL_LO12_S: 113 case ELF::R_RISCV_RVC_JUMP: 114 case ELF::R_RISCV_RVC_BRANCH: 115 case ELF::R_RISCV_ADD32: 116 case ELF::R_RISCV_SUB32: 117 case ELF::R_RISCV_HI20: 118 case ELF::R_RISCV_LO12_I: 119 case ELF::R_RISCV_LO12_S: 120 case ELF::R_RISCV_64: 121 case ELF::R_RISCV_TLS_GOT_HI20: 122 case ELF::R_RISCV_TPREL_HI20: 123 case ELF::R_RISCV_TPREL_ADD: 124 case ELF::R_RISCV_TPREL_LO12_I: 125 case ELF::R_RISCV_TPREL_LO12_S: 126 case ELFReserved::R_RISCV_TPREL_I: 127 case ELFReserved::R_RISCV_TPREL_S: 128 return true; 129 } 130 } 131 132 static size_t getSizeForTypeX86(uint64_t Type) { 133 switch (Type) { 134 default: 135 errs() << object::getELFRelocationTypeName(ELF::EM_X86_64, Type) << '\n'; 136 llvm_unreachable("unsupported relocation type"); 137 case ELF::R_X86_64_8: 138 case ELF::R_X86_64_PC8: 139 return 1; 140 case ELF::R_X86_64_16: 141 return 2; 142 case ELF::R_X86_64_PLT32: 143 case ELF::R_X86_64_PC32: 144 case ELF::R_X86_64_32S: 145 case ELF::R_X86_64_32: 146 case ELF::R_X86_64_GOTPCREL: 147 case ELF::R_X86_64_GOTTPOFF: 148 case ELF::R_X86_64_TPOFF32: 149 case ELF::R_X86_64_GOTPCRELX: 150 case ELF::R_X86_64_REX_GOTPCRELX: 151 return 4; 152 case ELF::R_X86_64_PC64: 153 case ELF::R_X86_64_64: 154 case ELF::R_X86_64_GOTPC64: 155 return 8; 156 } 157 } 158 159 static size_t getSizeForTypeAArch64(uint64_t Type) { 160 switch (Type) { 161 default: 162 errs() << object::getELFRelocationTypeName(ELF::EM_AARCH64, Type) << '\n'; 163 llvm_unreachable("unsupported relocation type"); 164 case ELF::R_AARCH64_ABS16: 165 case ELF::R_AARCH64_PREL16: 166 return 2; 167 case ELF::R_AARCH64_CALL26: 168 case ELF::R_AARCH64_JUMP26: 169 case ELF::R_AARCH64_TSTBR14: 170 case ELF::R_AARCH64_CONDBR19: 171 case ELF::R_AARCH64_ADR_PREL_LO21: 172 case ELF::R_AARCH64_ADR_PREL_PG_HI21: 173 case ELF::R_AARCH64_ADR_PREL_PG_HI21_NC: 174 case ELF::R_AARCH64_LDST64_ABS_LO12_NC: 175 case ELF::R_AARCH64_ADD_ABS_LO12_NC: 176 case ELF::R_AARCH64_LDST128_ABS_LO12_NC: 177 case ELF::R_AARCH64_LDST32_ABS_LO12_NC: 178 case ELF::R_AARCH64_LDST16_ABS_LO12_NC: 179 case ELF::R_AARCH64_LDST8_ABS_LO12_NC: 180 case ELF::R_AARCH64_ADR_GOT_PAGE: 181 case ELF::R_AARCH64_TLSDESC_ADR_PREL21: 182 case ELF::R_AARCH64_TLSDESC_ADR_PAGE21: 183 case ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: 184 case ELF::R_AARCH64_TLSLE_ADD_TPREL_HI12: 185 case ELF::R_AARCH64_TLSLE_ADD_TPREL_LO12_NC: 186 case ELF::R_AARCH64_LD64_GOT_LO12_NC: 187 case ELF::R_AARCH64_TLSDESC_LD64_LO12: 188 case ELF::R_AARCH64_TLSDESC_ADD_LO12: 189 case ELF::R_AARCH64_TLSDESC_CALL: 190 case ELF::R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: 191 case ELF::R_AARCH64_PREL32: 192 case ELF::R_AARCH64_MOVW_UABS_G0: 193 case ELF::R_AARCH64_MOVW_UABS_G0_NC: 194 case ELF::R_AARCH64_MOVW_UABS_G1: 195 case ELF::R_AARCH64_MOVW_UABS_G1_NC: 196 case ELF::R_AARCH64_MOVW_UABS_G2: 197 case ELF::R_AARCH64_MOVW_UABS_G2_NC: 198 case ELF::R_AARCH64_MOVW_UABS_G3: 199 case ELF::R_AARCH64_ABS32: 200 return 4; 201 case ELF::R_AARCH64_ABS64: 202 case ELF::R_AARCH64_PREL64: 203 return 8; 204 } 205 } 206 207 static size_t getSizeForTypeRISCV(uint64_t Type) { 208 switch (Type) { 209 default: 210 errs() << object::getELFRelocationTypeName(ELF::EM_RISCV, Type) << '\n'; 211 llvm_unreachable("unsupported relocation type"); 212 case ELF::R_RISCV_RVC_JUMP: 213 case ELF::R_RISCV_RVC_BRANCH: 214 return 2; 215 case ELF::R_RISCV_JAL: 216 case ELF::R_RISCV_BRANCH: 217 case ELF::R_RISCV_PCREL_HI20: 218 case ELF::R_RISCV_PCREL_LO12_I: 219 case ELF::R_RISCV_PCREL_LO12_S: 220 case ELF::R_RISCV_32_PCREL: 221 case ELF::R_RISCV_CALL: 222 case ELF::R_RISCV_CALL_PLT: 223 case ELF::R_RISCV_ADD32: 224 case ELF::R_RISCV_SUB32: 225 case ELF::R_RISCV_HI20: 226 case ELF::R_RISCV_LO12_I: 227 case ELF::R_RISCV_LO12_S: 228 return 4; 229 case ELF::R_RISCV_64: 230 case ELF::R_RISCV_GOT_HI20: 231 case ELF::R_RISCV_TLS_GOT_HI20: 232 // See extractValueRISCV for why this is necessary. 233 return 8; 234 } 235 } 236 237 static bool skipRelocationTypeX86(uint64_t Type) { 238 return Type == ELF::R_X86_64_NONE; 239 } 240 241 static bool skipRelocationTypeAArch64(uint64_t Type) { 242 return Type == ELF::R_AARCH64_NONE || Type == ELF::R_AARCH64_LD_PREL_LO19; 243 } 244 245 static bool skipRelocationTypeRISCV(uint64_t Type) { 246 switch (Type) { 247 default: 248 return false; 249 case ELF::R_RISCV_NONE: 250 case ELF::R_RISCV_RELAX: 251 return true; 252 } 253 } 254 255 static bool skipRelocationProcessX86(uint64_t &Type, uint64_t Contents) { 256 return false; 257 } 258 259 static bool skipRelocationProcessAArch64(uint64_t &Type, uint64_t Contents) { 260 auto IsMov = [](uint64_t Contents) -> bool { 261 // The bits 28-23 are 0b100101 262 return (Contents & 0x1f800000) == 0x12800000; 263 }; 264 265 auto IsB = [](uint64_t Contents) -> bool { 266 // The bits 31-26 are 0b000101 267 return (Contents & 0xfc000000) == 0x14000000; 268 }; 269 270 auto IsAdr = [](uint64_t Contents) -> bool { 271 // The bits 31-24 are 0b0xx10000 272 return (Contents & 0x9f000000) == 0x10000000; 273 }; 274 275 auto IsAddImm = [](uint64_t Contents) -> bool { 276 // The bits 30-23 are 0b00100010 277 return (Contents & 0x7F800000) == 0x11000000; 278 }; 279 280 auto IsNop = [](uint64_t Contents) -> bool { return Contents == 0xd503201f; }; 281 282 // The linker might eliminate the instruction and replace it with NOP, ignore 283 if (IsNop(Contents)) 284 return true; 285 286 // The linker might relax ADRP+LDR instruction sequence for loading symbol 287 // address from GOT table to ADRP+ADD sequence that would point to the 288 // binary-local symbol. Change relocation type in order to process it right. 289 if (Type == ELF::R_AARCH64_LD64_GOT_LO12_NC && IsAddImm(Contents)) { 290 Type = ELF::R_AARCH64_ADD_ABS_LO12_NC; 291 return false; 292 } 293 294 // The linker might perform TLS relocations relaxations, such as 295 // changed TLS access model (e.g. changed global dynamic model 296 // to initial exec), thus changing the instructions. The static 297 // relocations might be invalid at this point and we might no 298 // need to proccess these relocations anymore. 299 // More information could be found by searching 300 // elfNN_aarch64_tls_relax in bfd 301 switch (Type) { 302 default: 303 break; 304 case ELF::R_AARCH64_TLSDESC_LD64_LO12: 305 case ELF::R_AARCH64_TLSDESC_ADR_PAGE21: 306 case ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: 307 case ELF::R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: { 308 if (IsMov(Contents)) 309 return true; 310 } 311 } 312 313 // The linker might replace load/store instruction with jump and 314 // veneer due to errata 843419 315 // https://documentation-service.arm.com/static/5fa29fddb209f547eebd361d 316 // Thus load/store relocations for these instructions must be ignored 317 // NOTE: We only process GOT and TLS relocations this way since the 318 // addend used in load/store instructions won't change after bolt 319 // (it is important since the instruction in veneer won't have relocation) 320 switch (Type) { 321 default: 322 break; 323 case ELF::R_AARCH64_LD64_GOT_LO12_NC: 324 case ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: 325 case ELF::R_AARCH64_TLSDESC_LD64_LO12: { 326 if (IsB(Contents)) 327 return true; 328 } 329 } 330 331 // The linker might relax ADRP+ADD or ADRP+LDR sequences to the ADR+NOP 332 switch (Type) { 333 default: 334 break; 335 case ELF::R_AARCH64_ADR_PREL_PG_HI21: 336 case ELF::R_AARCH64_ADD_ABS_LO12_NC: 337 case ELF::R_AARCH64_ADR_GOT_PAGE: 338 case ELF::R_AARCH64_LD64_GOT_LO12_NC: 339 if (IsAdr(Contents)) 340 return true; 341 } 342 343 return false; 344 } 345 346 static bool skipRelocationProcessRISCV(uint64_t &Type, uint64_t Contents) { 347 return false; 348 } 349 350 static uint64_t encodeValueX86(uint64_t Type, uint64_t Value, uint64_t PC) { 351 switch (Type) { 352 default: 353 llvm_unreachable("unsupported relocation"); 354 case ELF::R_X86_64_64: 355 case ELF::R_X86_64_32: 356 break; 357 case ELF::R_X86_64_PC32: 358 Value -= PC; 359 break; 360 } 361 return Value; 362 } 363 364 static uint64_t encodeValueAArch64(uint64_t Type, uint64_t Value, uint64_t PC) { 365 switch (Type) { 366 default: 367 llvm_unreachable("unsupported relocation"); 368 case ELF::R_AARCH64_ABS32: 369 break; 370 case ELF::R_AARCH64_PREL16: 371 case ELF::R_AARCH64_PREL32: 372 case ELF::R_AARCH64_PREL64: 373 Value -= PC; 374 break; 375 case ELF::R_AARCH64_CALL26: 376 Value -= PC; 377 assert(isInt<28>(Value) && "only PC +/- 128MB is allowed for direct call"); 378 // Immediate goes in bits 25:0 of BL. 379 // OP 1001_01 goes in bits 31:26 of BL. 380 Value = ((Value >> 2) & 0x3ffffff) | 0x94000000ULL; 381 break; 382 } 383 return Value; 384 } 385 386 static uint64_t encodeValueRISCV(uint64_t Type, uint64_t Value, uint64_t PC) { 387 switch (Type) { 388 default: 389 llvm_unreachable("unsupported relocation"); 390 case ELF::R_RISCV_64: 391 break; 392 } 393 return Value; 394 } 395 396 static uint64_t extractValueX86(uint64_t Type, uint64_t Contents, uint64_t PC) { 397 if (Type == ELF::R_X86_64_32S) 398 return SignExtend64<32>(Contents); 399 if (Relocation::isPCRelative(Type)) 400 return SignExtend64(Contents, 8 * Relocation::getSizeForType(Type)); 401 return Contents; 402 } 403 404 static uint64_t extractValueAArch64(uint64_t Type, uint64_t Contents, 405 uint64_t PC) { 406 switch (Type) { 407 default: 408 errs() << object::getELFRelocationTypeName(ELF::EM_AARCH64, Type) << '\n'; 409 llvm_unreachable("unsupported relocation type"); 410 case ELF::R_AARCH64_ABS16: 411 case ELF::R_AARCH64_ABS32: 412 case ELF::R_AARCH64_ABS64: 413 return Contents; 414 case ELF::R_AARCH64_PREL16: 415 return static_cast<int64_t>(PC) + SignExtend64<16>(Contents & 0xffff); 416 case ELF::R_AARCH64_PREL32: 417 return static_cast<int64_t>(PC) + SignExtend64<32>(Contents & 0xffffffff); 418 case ELF::R_AARCH64_PREL64: 419 return static_cast<int64_t>(PC) + Contents; 420 case ELF::R_AARCH64_TLSDESC_CALL: 421 case ELF::R_AARCH64_JUMP26: 422 case ELF::R_AARCH64_CALL26: 423 // Immediate goes in bits 25:0 of B and BL. 424 Contents &= ~0xfffffffffc000000ULL; 425 return static_cast<int64_t>(PC) + SignExtend64<28>(Contents << 2); 426 case ELF::R_AARCH64_TSTBR14: 427 // Immediate:15:2 goes in bits 18:5 of TBZ, TBNZ 428 Contents &= ~0xfffffffffff8001fULL; 429 return static_cast<int64_t>(PC) + SignExtend64<16>(Contents >> 3); 430 case ELF::R_AARCH64_CONDBR19: 431 // Immediate:20:2 goes in bits 23:5 of Bcc, CBZ, CBNZ 432 Contents &= ~0xffffffffff00001fULL; 433 return static_cast<int64_t>(PC) + SignExtend64<21>(Contents >> 3); 434 case ELF::R_AARCH64_ADR_GOT_PAGE: 435 case ELF::R_AARCH64_TLSDESC_ADR_PREL21: 436 case ELF::R_AARCH64_TLSDESC_ADR_PAGE21: 437 case ELF::R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: 438 case ELF::R_AARCH64_ADR_PREL_LO21: 439 case ELF::R_AARCH64_ADR_PREL_PG_HI21: 440 case ELF::R_AARCH64_ADR_PREL_PG_HI21_NC: { 441 // Bits 32:12 of Symbol address goes in bits 30:29 + 23:5 of ADRP 442 // and ADR instructions 443 bool IsAdr = !!(((Contents >> 31) & 0x1) == 0); 444 Contents &= ~0xffffffff9f00001fUll; 445 uint64_t LowBits = (Contents >> 29) & 0x3; 446 uint64_t HighBits = (Contents >> 5) & 0x7ffff; 447 Contents = LowBits | (HighBits << 2); 448 if (IsAdr) 449 return static_cast<int64_t>(PC) + SignExtend64<21>(Contents); 450 451 // ADRP instruction 452 Contents = static_cast<int64_t>(PC) + SignExtend64<33>(Contents << 12); 453 Contents &= ~0xfffUll; 454 return Contents; 455 } 456 case ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: 457 case ELF::R_AARCH64_TLSDESC_LD64_LO12: 458 case ELF::R_AARCH64_LD64_GOT_LO12_NC: 459 case ELF::R_AARCH64_LDST64_ABS_LO12_NC: { 460 // Immediate goes in bits 21:10 of LD/ST instruction, taken 461 // from bits 11:3 of Symbol address 462 Contents &= ~0xffffffffffc003ffU; 463 return Contents >> (10 - 3); 464 } 465 case ELF::R_AARCH64_TLSLE_ADD_TPREL_HI12: 466 case ELF::R_AARCH64_TLSLE_ADD_TPREL_LO12_NC: 467 case ELF::R_AARCH64_TLSDESC_ADD_LO12: 468 case ELF::R_AARCH64_ADD_ABS_LO12_NC: { 469 // Immediate goes in bits 21:10 of ADD instruction 470 Contents &= ~0xffffffffffc003ffU; 471 return Contents >> (10 - 0); 472 } 473 case ELF::R_AARCH64_LDST128_ABS_LO12_NC: { 474 // Immediate goes in bits 21:10 of ADD instruction, taken 475 // from bits 11:4 of Symbol address 476 Contents &= ~0xffffffffffc003ffU; 477 return Contents >> (10 - 4); 478 } 479 case ELF::R_AARCH64_LDST32_ABS_LO12_NC: { 480 // Immediate goes in bits 21:10 of ADD instruction, taken 481 // from bits 11:2 of Symbol address 482 Contents &= ~0xffffffffffc003ffU; 483 return Contents >> (10 - 2); 484 } 485 case ELF::R_AARCH64_LDST16_ABS_LO12_NC: { 486 // Immediate goes in bits 21:10 of ADD instruction, taken 487 // from bits 11:1 of Symbol address 488 Contents &= ~0xffffffffffc003ffU; 489 return Contents >> (10 - 1); 490 } 491 case ELF::R_AARCH64_LDST8_ABS_LO12_NC: { 492 // Immediate goes in bits 21:10 of ADD instruction, taken 493 // from bits 11:0 of Symbol address 494 Contents &= ~0xffffffffffc003ffU; 495 return Contents >> (10 - 0); 496 } 497 case ELF::R_AARCH64_MOVW_UABS_G3: 498 case ELF::R_AARCH64_MOVW_UABS_G2_NC: 499 case ELF::R_AARCH64_MOVW_UABS_G2: 500 case ELF::R_AARCH64_MOVW_UABS_G1_NC: 501 case ELF::R_AARCH64_MOVW_UABS_G1: 502 case ELF::R_AARCH64_MOVW_UABS_G0_NC: 503 case ELF::R_AARCH64_MOVW_UABS_G0: 504 // The shift goest in bits 22:21 of MOV* instructions 505 uint8_t Shift = (Contents >> 21) & 0x3; 506 // Immediate goes in bits 20:5 507 Contents = (Contents >> 5) & 0xffff; 508 return Contents << (16 * Shift); 509 } 510 } 511 512 static uint64_t extractUImmRISCV(uint32_t Contents) { 513 return SignExtend64<32>(Contents & 0xfffff000); 514 } 515 516 static uint64_t extractIImmRISCV(uint32_t Contents) { 517 return SignExtend64<12>(Contents >> 20); 518 } 519 520 static uint64_t extractSImmRISCV(uint32_t Contents) { 521 return SignExtend64<12>(((Contents >> 7) & 0x1f) | ((Contents >> 25) << 5)); 522 } 523 524 static uint64_t extractJImmRISCV(uint32_t Contents) { 525 return SignExtend64<21>( 526 (((Contents >> 21) & 0x3ff) << 1) | (((Contents >> 20) & 0x1) << 11) | 527 (((Contents >> 12) & 0xff) << 12) | (((Contents >> 31) & 0x1) << 20)); 528 } 529 530 static uint64_t extractBImmRISCV(uint32_t Contents) { 531 return SignExtend64<13>( 532 (((Contents >> 8) & 0xf) << 1) | (((Contents >> 25) & 0x3f) << 5) | 533 (((Contents >> 7) & 0x1) << 11) | (((Contents >> 31) & 0x1) << 12)); 534 } 535 536 static uint64_t extractValueRISCV(uint64_t Type, uint64_t Contents, 537 uint64_t PC) { 538 switch (Type) { 539 default: 540 errs() << object::getELFRelocationTypeName(ELF::EM_RISCV, Type) << '\n'; 541 llvm_unreachable("unsupported relocation type"); 542 case ELF::R_RISCV_JAL: 543 return extractJImmRISCV(Contents); 544 case ELF::R_RISCV_CALL: 545 case ELF::R_RISCV_CALL_PLT: 546 return extractUImmRISCV(Contents); 547 case ELF::R_RISCV_BRANCH: 548 return extractBImmRISCV(Contents); 549 case ELF::R_RISCV_GOT_HI20: 550 case ELF::R_RISCV_TLS_GOT_HI20: 551 // We need to know the exact address of the GOT entry so we extract the 552 // value from both the AUIPC and L[D|W]. We cannot rely on the symbol in the 553 // relocation for this since it simply refers to the object that is stored 554 // in the GOT entry, not to the entry itself. 555 return extractUImmRISCV(Contents & 0xffffffff) + 556 extractIImmRISCV(Contents >> 32); 557 case ELF::R_RISCV_PCREL_HI20: 558 case ELF::R_RISCV_HI20: 559 return extractUImmRISCV(Contents); 560 case ELF::R_RISCV_PCREL_LO12_I: 561 case ELF::R_RISCV_LO12_I: 562 return extractIImmRISCV(Contents); 563 case ELF::R_RISCV_PCREL_LO12_S: 564 case ELF::R_RISCV_LO12_S: 565 return extractSImmRISCV(Contents); 566 case ELF::R_RISCV_RVC_JUMP: 567 return SignExtend64<11>(Contents >> 2); 568 case ELF::R_RISCV_RVC_BRANCH: 569 return SignExtend64<8>(((Contents >> 2) & 0x1f) | ((Contents >> 5) & 0xe0)); 570 case ELF::R_RISCV_ADD32: 571 case ELF::R_RISCV_SUB32: 572 case ELF::R_RISCV_64: 573 return Contents; 574 } 575 } 576 577 static bool isGOTX86(uint64_t Type) { 578 switch (Type) { 579 default: 580 return false; 581 case ELF::R_X86_64_GOT32: 582 case ELF::R_X86_64_GOTPCREL: 583 case ELF::R_X86_64_GOTTPOFF: 584 case ELF::R_X86_64_GOTOFF64: 585 case ELF::R_X86_64_GOTPC32: 586 case ELF::R_X86_64_GOT64: 587 case ELF::R_X86_64_GOTPCREL64: 588 case ELF::R_X86_64_GOTPC64: 589 case ELF::R_X86_64_GOTPLT64: 590 case ELF::R_X86_64_GOTPC32_TLSDESC: 591 case ELF::R_X86_64_GOTPCRELX: 592 case ELF::R_X86_64_REX_GOTPCRELX: 593 return true; 594 } 595 } 596 597 static bool isGOTAArch64(uint64_t Type) { 598 switch (Type) { 599 default: 600 return false; 601 case ELF::R_AARCH64_ADR_GOT_PAGE: 602 case ELF::R_AARCH64_LD64_GOT_LO12_NC: 603 case ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: 604 case ELF::R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: 605 case ELF::R_AARCH64_TLSDESC_ADR_PREL21: 606 case ELF::R_AARCH64_TLSDESC_ADR_PAGE21: 607 case ELF::R_AARCH64_TLSDESC_LD64_LO12: 608 case ELF::R_AARCH64_TLSDESC_ADD_LO12: 609 case ELF::R_AARCH64_TLSDESC_CALL: 610 return true; 611 } 612 } 613 614 static bool isGOTRISCV(uint64_t Type) { 615 switch (Type) { 616 default: 617 return false; 618 case ELF::R_RISCV_GOT_HI20: 619 case ELF::R_RISCV_TLS_GOT_HI20: 620 return true; 621 } 622 } 623 624 static bool isTLSX86(uint64_t Type) { 625 switch (Type) { 626 default: 627 return false; 628 case ELF::R_X86_64_TPOFF32: 629 case ELF::R_X86_64_TPOFF64: 630 case ELF::R_X86_64_GOTTPOFF: 631 return true; 632 } 633 } 634 635 static bool isTLSAArch64(uint64_t Type) { 636 switch (Type) { 637 default: 638 return false; 639 case ELF::R_AARCH64_TLSDESC_ADR_PREL21: 640 case ELF::R_AARCH64_TLSDESC_ADR_PAGE21: 641 case ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: 642 case ELF::R_AARCH64_TLSLE_ADD_TPREL_HI12: 643 case ELF::R_AARCH64_TLSLE_ADD_TPREL_LO12_NC: 644 case ELF::R_AARCH64_TLSDESC_LD64_LO12: 645 case ELF::R_AARCH64_TLSDESC_ADD_LO12: 646 case ELF::R_AARCH64_TLSDESC_CALL: 647 case ELF::R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: 648 return true; 649 } 650 } 651 652 static bool isTLSRISCV(uint64_t Type) { 653 switch (Type) { 654 default: 655 return false; 656 case ELF::R_RISCV_TLS_GOT_HI20: 657 case ELF::R_RISCV_TPREL_HI20: 658 case ELF::R_RISCV_TPREL_ADD: 659 case ELF::R_RISCV_TPREL_LO12_I: 660 case ELF::R_RISCV_TPREL_LO12_S: 661 case ELFReserved::R_RISCV_TPREL_I: 662 case ELFReserved::R_RISCV_TPREL_S: 663 return true; 664 } 665 } 666 667 static bool isPCRelativeX86(uint64_t Type) { 668 switch (Type) { 669 default: 670 llvm_unreachable("Unknown relocation type"); 671 case ELF::R_X86_64_64: 672 case ELF::R_X86_64_32: 673 case ELF::R_X86_64_32S: 674 case ELF::R_X86_64_16: 675 case ELF::R_X86_64_8: 676 case ELF::R_X86_64_TPOFF32: 677 return false; 678 case ELF::R_X86_64_PC8: 679 case ELF::R_X86_64_PC32: 680 case ELF::R_X86_64_PC64: 681 case ELF::R_X86_64_GOTPCREL: 682 case ELF::R_X86_64_PLT32: 683 case ELF::R_X86_64_GOTOFF64: 684 case ELF::R_X86_64_GOTPC32: 685 case ELF::R_X86_64_GOTPC64: 686 case ELF::R_X86_64_GOTTPOFF: 687 case ELF::R_X86_64_GOTPCRELX: 688 case ELF::R_X86_64_REX_GOTPCRELX: 689 return true; 690 } 691 } 692 693 static bool isPCRelativeAArch64(uint64_t Type) { 694 switch (Type) { 695 default: 696 llvm_unreachable("Unknown relocation type"); 697 case ELF::R_AARCH64_ABS16: 698 case ELF::R_AARCH64_ABS32: 699 case ELF::R_AARCH64_ABS64: 700 case ELF::R_AARCH64_LDST64_ABS_LO12_NC: 701 case ELF::R_AARCH64_ADD_ABS_LO12_NC: 702 case ELF::R_AARCH64_LDST128_ABS_LO12_NC: 703 case ELF::R_AARCH64_LDST32_ABS_LO12_NC: 704 case ELF::R_AARCH64_LDST16_ABS_LO12_NC: 705 case ELF::R_AARCH64_LDST8_ABS_LO12_NC: 706 case ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: 707 case ELF::R_AARCH64_TLSLE_ADD_TPREL_HI12: 708 case ELF::R_AARCH64_TLSLE_ADD_TPREL_LO12_NC: 709 case ELF::R_AARCH64_LD64_GOT_LO12_NC: 710 case ELF::R_AARCH64_TLSDESC_LD64_LO12: 711 case ELF::R_AARCH64_TLSDESC_ADD_LO12: 712 case ELF::R_AARCH64_MOVW_UABS_G0: 713 case ELF::R_AARCH64_MOVW_UABS_G0_NC: 714 case ELF::R_AARCH64_MOVW_UABS_G1: 715 case ELF::R_AARCH64_MOVW_UABS_G1_NC: 716 case ELF::R_AARCH64_MOVW_UABS_G2: 717 case ELF::R_AARCH64_MOVW_UABS_G2_NC: 718 case ELF::R_AARCH64_MOVW_UABS_G3: 719 return false; 720 case ELF::R_AARCH64_TLSDESC_CALL: 721 case ELF::R_AARCH64_CALL26: 722 case ELF::R_AARCH64_JUMP26: 723 case ELF::R_AARCH64_TSTBR14: 724 case ELF::R_AARCH64_CONDBR19: 725 case ELF::R_AARCH64_ADR_PREL_LO21: 726 case ELF::R_AARCH64_ADR_PREL_PG_HI21: 727 case ELF::R_AARCH64_ADR_PREL_PG_HI21_NC: 728 case ELF::R_AARCH64_ADR_GOT_PAGE: 729 case ELF::R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: 730 case ELF::R_AARCH64_TLSDESC_ADR_PREL21: 731 case ELF::R_AARCH64_TLSDESC_ADR_PAGE21: 732 case ELF::R_AARCH64_PREL16: 733 case ELF::R_AARCH64_PREL32: 734 case ELF::R_AARCH64_PREL64: 735 return true; 736 } 737 } 738 739 static bool isPCRelativeRISCV(uint64_t Type) { 740 switch (Type) { 741 default: 742 llvm_unreachable("Unknown relocation type"); 743 case ELF::R_RISCV_ADD32: 744 case ELF::R_RISCV_SUB32: 745 case ELF::R_RISCV_HI20: 746 case ELF::R_RISCV_LO12_I: 747 case ELF::R_RISCV_LO12_S: 748 case ELF::R_RISCV_64: 749 return false; 750 case ELF::R_RISCV_JAL: 751 case ELF::R_RISCV_CALL: 752 case ELF::R_RISCV_CALL_PLT: 753 case ELF::R_RISCV_BRANCH: 754 case ELF::R_RISCV_GOT_HI20: 755 case ELF::R_RISCV_PCREL_HI20: 756 case ELF::R_RISCV_PCREL_LO12_I: 757 case ELF::R_RISCV_PCREL_LO12_S: 758 case ELF::R_RISCV_RVC_JUMP: 759 case ELF::R_RISCV_RVC_BRANCH: 760 case ELF::R_RISCV_32_PCREL: 761 case ELF::R_RISCV_TLS_GOT_HI20: 762 return true; 763 } 764 } 765 766 bool Relocation::isSupported(uint64_t Type) { 767 if (Arch == Triple::aarch64) 768 return isSupportedAArch64(Type); 769 if (Arch == Triple::riscv64) 770 return isSupportedRISCV(Type); 771 return isSupportedX86(Type); 772 } 773 774 size_t Relocation::getSizeForType(uint64_t Type) { 775 if (Arch == Triple::aarch64) 776 return getSizeForTypeAArch64(Type); 777 if (Arch == Triple::riscv64) 778 return getSizeForTypeRISCV(Type); 779 return getSizeForTypeX86(Type); 780 } 781 782 bool Relocation::skipRelocationType(uint64_t Type) { 783 if (Arch == Triple::aarch64) 784 return skipRelocationTypeAArch64(Type); 785 if (Arch == Triple::riscv64) 786 return skipRelocationTypeRISCV(Type); 787 return skipRelocationTypeX86(Type); 788 } 789 790 bool Relocation::skipRelocationProcess(uint64_t &Type, uint64_t Contents) { 791 if (Arch == Triple::aarch64) 792 return skipRelocationProcessAArch64(Type, Contents); 793 if (Arch == Triple::riscv64) 794 skipRelocationProcessRISCV(Type, Contents); 795 return skipRelocationProcessX86(Type, Contents); 796 } 797 798 uint64_t Relocation::encodeValue(uint64_t Type, uint64_t Value, uint64_t PC) { 799 if (Arch == Triple::aarch64) 800 return encodeValueAArch64(Type, Value, PC); 801 if (Arch == Triple::riscv64) 802 return encodeValueRISCV(Type, Value, PC); 803 return encodeValueX86(Type, Value, PC); 804 } 805 806 uint64_t Relocation::extractValue(uint64_t Type, uint64_t Contents, 807 uint64_t PC) { 808 if (Arch == Triple::aarch64) 809 return extractValueAArch64(Type, Contents, PC); 810 if (Arch == Triple::riscv64) 811 return extractValueRISCV(Type, Contents, PC); 812 return extractValueX86(Type, Contents, PC); 813 } 814 815 bool Relocation::isGOT(uint64_t Type) { 816 if (Arch == Triple::aarch64) 817 return isGOTAArch64(Type); 818 if (Arch == Triple::riscv64) 819 return isGOTRISCV(Type); 820 return isGOTX86(Type); 821 } 822 823 bool Relocation::isX86GOTPCRELX(uint64_t Type) { 824 if (Arch != Triple::x86_64) 825 return false; 826 return Type == ELF::R_X86_64_GOTPCRELX || Type == ELF::R_X86_64_REX_GOTPCRELX; 827 } 828 829 bool Relocation::isX86GOTPC64(uint64_t Type) { 830 if (Arch != Triple::x86_64) 831 return false; 832 return Type == ELF::R_X86_64_GOTPC64; 833 } 834 835 bool Relocation::isNone(uint64_t Type) { return Type == getNone(); } 836 837 bool Relocation::isRelative(uint64_t Type) { 838 if (Arch == Triple::aarch64) 839 return Type == ELF::R_AARCH64_RELATIVE; 840 if (Arch == Triple::riscv64) 841 return Type == ELF::R_RISCV_RELATIVE; 842 return Type == ELF::R_X86_64_RELATIVE; 843 } 844 845 bool Relocation::isIRelative(uint64_t Type) { 846 if (Arch == Triple::aarch64) 847 return Type == ELF::R_AARCH64_IRELATIVE; 848 if (Arch == Triple::riscv64) 849 llvm_unreachable("not implemented"); 850 return Type == ELF::R_X86_64_IRELATIVE; 851 } 852 853 bool Relocation::isTLS(uint64_t Type) { 854 if (Arch == Triple::aarch64) 855 return isTLSAArch64(Type); 856 if (Arch == Triple::riscv64) 857 return isTLSRISCV(Type); 858 return isTLSX86(Type); 859 } 860 861 bool Relocation::isInstructionReference(uint64_t Type) { 862 if (Arch != Triple::riscv64) 863 return false; 864 865 switch (Type) { 866 default: 867 return false; 868 case ELF::R_RISCV_PCREL_LO12_I: 869 case ELF::R_RISCV_PCREL_LO12_S: 870 return true; 871 } 872 } 873 874 uint64_t Relocation::getNone() { 875 if (Arch == Triple::aarch64) 876 return ELF::R_AARCH64_NONE; 877 if (Arch == Triple::riscv64) 878 return ELF::R_RISCV_NONE; 879 return ELF::R_X86_64_NONE; 880 } 881 882 uint64_t Relocation::getPC32() { 883 if (Arch == Triple::aarch64) 884 return ELF::R_AARCH64_PREL32; 885 if (Arch == Triple::riscv64) 886 return ELF::R_RISCV_32_PCREL; 887 return ELF::R_X86_64_PC32; 888 } 889 890 uint64_t Relocation::getPC64() { 891 if (Arch == Triple::aarch64) 892 return ELF::R_AARCH64_PREL64; 893 if (Arch == Triple::riscv64) 894 llvm_unreachable("not implemented"); 895 return ELF::R_X86_64_PC64; 896 } 897 898 bool Relocation::isPCRelative(uint64_t Type) { 899 if (Arch == Triple::aarch64) 900 return isPCRelativeAArch64(Type); 901 if (Arch == Triple::riscv64) 902 return isPCRelativeRISCV(Type); 903 return isPCRelativeX86(Type); 904 } 905 906 uint64_t Relocation::getAbs64() { 907 if (Arch == Triple::aarch64) 908 return ELF::R_AARCH64_ABS64; 909 if (Arch == Triple::riscv64) 910 return ELF::R_RISCV_64; 911 return ELF::R_X86_64_64; 912 } 913 914 uint64_t Relocation::getRelative() { 915 if (Arch == Triple::aarch64) 916 return ELF::R_AARCH64_RELATIVE; 917 return ELF::R_X86_64_RELATIVE; 918 } 919 920 size_t Relocation::emit(MCStreamer *Streamer) const { 921 const size_t Size = getSizeForType(Type); 922 const auto *Value = createExpr(Streamer); 923 Streamer->emitValue(Value, Size); 924 return Size; 925 } 926 927 const MCExpr *Relocation::createExpr(MCStreamer *Streamer) const { 928 MCContext &Ctx = Streamer->getContext(); 929 const MCExpr *Value = nullptr; 930 931 if (Symbol && Addend) { 932 Value = MCBinaryExpr::createAdd(MCSymbolRefExpr::create(Symbol, Ctx), 933 MCConstantExpr::create(Addend, Ctx), Ctx); 934 } else if (Symbol) { 935 Value = MCSymbolRefExpr::create(Symbol, Ctx); 936 } else { 937 Value = MCConstantExpr::create(Addend, Ctx); 938 } 939 940 if (isPCRelative(Type)) { 941 MCSymbol *TempLabel = Ctx.createNamedTempSymbol(); 942 Streamer->emitLabel(TempLabel); 943 Value = MCBinaryExpr::createSub( 944 Value, MCSymbolRefExpr::create(TempLabel, Ctx), Ctx); 945 } 946 947 return Value; 948 } 949 950 const MCExpr *Relocation::createExpr(MCStreamer *Streamer, 951 const MCExpr *RetainedValue) const { 952 const auto *Value = createExpr(Streamer); 953 954 if (RetainedValue) { 955 Value = MCBinaryExpr::create(getComposeOpcodeFor(Type), RetainedValue, 956 Value, Streamer->getContext()); 957 } 958 959 return Value; 960 } 961 962 MCBinaryExpr::Opcode Relocation::getComposeOpcodeFor(uint64_t Type) { 963 assert(Arch == Triple::riscv64 && "only implemented for RISC-V"); 964 965 switch (Type) { 966 default: 967 llvm_unreachable("not implemented"); 968 case ELF::R_RISCV_ADD32: 969 return MCBinaryExpr::Add; 970 case ELF::R_RISCV_SUB32: 971 return MCBinaryExpr::Sub; 972 } 973 } 974 975 #define ELF_RELOC(name, value) #name, 976 977 void Relocation::print(raw_ostream &OS) const { 978 static const char *X86RelocNames[] = { 979 #include "llvm/BinaryFormat/ELFRelocs/x86_64.def" 980 }; 981 static const char *AArch64RelocNames[] = { 982 #include "llvm/BinaryFormat/ELFRelocs/AArch64.def" 983 }; 984 if (Arch == Triple::aarch64) 985 OS << AArch64RelocNames[Type]; 986 else if (Arch == Triple::riscv64) { 987 // RISC-V relocations are not sequentially numbered so we cannot use an 988 // array 989 switch (Type) { 990 default: 991 llvm_unreachable("illegal RISC-V relocation"); 992 #undef ELF_RELOC 993 #define ELF_RELOC(name, value) \ 994 case value: \ 995 OS << #name; \ 996 break; 997 #include "llvm/BinaryFormat/ELFRelocs/RISCV.def" 998 } 999 } else 1000 OS << X86RelocNames[Type]; 1001 OS << ", 0x" << Twine::utohexstr(Offset); 1002 if (Symbol) { 1003 OS << ", " << Symbol->getName(); 1004 } 1005 if (int64_t(Addend) < 0) 1006 OS << ", -0x" << Twine::utohexstr(-int64_t(Addend)); 1007 else 1008 OS << ", 0x" << Twine::utohexstr(Addend); 1009 OS << ", 0x" << Twine::utohexstr(Value); 1010 } 1011