1 //===- bolt/Core/Relocation.cpp - Object file relocations -----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the Relocation class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "bolt/Core/Relocation.h" 14 #include "llvm/MC/MCContext.h" 15 #include "llvm/MC/MCExpr.h" 16 #include "llvm/MC/MCStreamer.h" 17 #include "llvm/MC/MCSymbol.h" 18 #include "llvm/Object/ELF.h" 19 20 using namespace llvm; 21 using namespace bolt; 22 23 Triple::ArchType Relocation::Arch; 24 25 static bool isSupportedX86(uint64_t Type) { 26 switch (Type) { 27 default: 28 return false; 29 case ELF::R_X86_64_8: 30 case ELF::R_X86_64_16: 31 case ELF::R_X86_64_32: 32 case ELF::R_X86_64_32S: 33 case ELF::R_X86_64_64: 34 case ELF::R_X86_64_PC8: 35 case ELF::R_X86_64_PC32: 36 case ELF::R_X86_64_PC64: 37 case ELF::R_X86_64_PLT32: 38 case ELF::R_X86_64_GOTPCREL: 39 case ELF::R_X86_64_GOTTPOFF: 40 case ELF::R_X86_64_TPOFF32: 41 case ELF::R_X86_64_GOTPCRELX: 42 case ELF::R_X86_64_REX_GOTPCRELX: 43 return true; 44 } 45 } 46 47 static bool isSupportedAArch64(uint64_t Type) { 48 switch (Type) { 49 default: 50 return false; 51 case ELF::R_AARCH64_CALL26: 52 case ELF::R_AARCH64_JUMP26: 53 case ELF::R_AARCH64_TSTBR14: 54 case ELF::R_AARCH64_CONDBR19: 55 case ELF::R_AARCH64_ADR_PREL_LO21: 56 case ELF::R_AARCH64_ADR_PREL_PG_HI21: 57 case ELF::R_AARCH64_ADR_PREL_PG_HI21_NC: 58 case ELF::R_AARCH64_LDST64_ABS_LO12_NC: 59 case ELF::R_AARCH64_ADD_ABS_LO12_NC: 60 case ELF::R_AARCH64_LDST128_ABS_LO12_NC: 61 case ELF::R_AARCH64_LDST32_ABS_LO12_NC: 62 case ELF::R_AARCH64_LDST16_ABS_LO12_NC: 63 case ELF::R_AARCH64_LDST8_ABS_LO12_NC: 64 case ELF::R_AARCH64_ADR_GOT_PAGE: 65 case ELF::R_AARCH64_TLSDESC_ADR_PREL21: 66 case ELF::R_AARCH64_TLSDESC_ADR_PAGE21: 67 case ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: 68 case ELF::R_AARCH64_TLSLE_ADD_TPREL_HI12: 69 case ELF::R_AARCH64_TLSLE_ADD_TPREL_LO12_NC: 70 case ELF::R_AARCH64_LD64_GOT_LO12_NC: 71 case ELF::R_AARCH64_TLSDESC_LD64_LO12: 72 case ELF::R_AARCH64_TLSDESC_ADD_LO12: 73 case ELF::R_AARCH64_TLSDESC_CALL: 74 case ELF::R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: 75 case ELF::R_AARCH64_PREL16: 76 case ELF::R_AARCH64_PREL32: 77 case ELF::R_AARCH64_PREL64: 78 case ELF::R_AARCH64_ABS16: 79 case ELF::R_AARCH64_ABS32: 80 case ELF::R_AARCH64_ABS64: 81 case ELF::R_AARCH64_MOVW_UABS_G0: 82 case ELF::R_AARCH64_MOVW_UABS_G0_NC: 83 case ELF::R_AARCH64_MOVW_UABS_G1: 84 case ELF::R_AARCH64_MOVW_UABS_G1_NC: 85 case ELF::R_AARCH64_MOVW_UABS_G2: 86 case ELF::R_AARCH64_MOVW_UABS_G2_NC: 87 case ELF::R_AARCH64_MOVW_UABS_G3: 88 return true; 89 } 90 } 91 92 static bool isSupportedRISCV(uint64_t Type) { 93 switch (Type) { 94 default: 95 return false; 96 case ELF::R_RISCV_JAL: 97 case ELF::R_RISCV_CALL: 98 case ELF::R_RISCV_CALL_PLT: 99 case ELF::R_RISCV_BRANCH: 100 case ELF::R_RISCV_RELAX: 101 case ELF::R_RISCV_GOT_HI20: 102 case ELF::R_RISCV_PCREL_HI20: 103 case ELF::R_RISCV_PCREL_LO12_I: 104 case ELF::R_RISCV_PCREL_LO12_S: 105 case ELF::R_RISCV_RVC_JUMP: 106 case ELF::R_RISCV_RVC_BRANCH: 107 case ELF::R_RISCV_ADD32: 108 case ELF::R_RISCV_SUB32: 109 case ELF::R_RISCV_HI20: 110 case ELF::R_RISCV_LO12_I: 111 case ELF::R_RISCV_LO12_S: 112 case ELF::R_RISCV_64: 113 return true; 114 } 115 } 116 117 static size_t getSizeForTypeX86(uint64_t Type) { 118 switch (Type) { 119 default: 120 errs() << object::getELFRelocationTypeName(ELF::EM_X86_64, Type) << '\n'; 121 llvm_unreachable("unsupported relocation type"); 122 case ELF::R_X86_64_8: 123 case ELF::R_X86_64_PC8: 124 return 1; 125 case ELF::R_X86_64_16: 126 return 2; 127 case ELF::R_X86_64_PLT32: 128 case ELF::R_X86_64_PC32: 129 case ELF::R_X86_64_32S: 130 case ELF::R_X86_64_32: 131 case ELF::R_X86_64_GOTPCREL: 132 case ELF::R_X86_64_GOTTPOFF: 133 case ELF::R_X86_64_TPOFF32: 134 case ELF::R_X86_64_GOTPCRELX: 135 case ELF::R_X86_64_REX_GOTPCRELX: 136 return 4; 137 case ELF::R_X86_64_PC64: 138 case ELF::R_X86_64_64: 139 return 8; 140 } 141 } 142 143 static size_t getSizeForTypeAArch64(uint64_t Type) { 144 switch (Type) { 145 default: 146 errs() << object::getELFRelocationTypeName(ELF::EM_AARCH64, Type) << '\n'; 147 llvm_unreachable("unsupported relocation type"); 148 case ELF::R_AARCH64_ABS16: 149 case ELF::R_AARCH64_PREL16: 150 return 2; 151 case ELF::R_AARCH64_CALL26: 152 case ELF::R_AARCH64_JUMP26: 153 case ELF::R_AARCH64_TSTBR14: 154 case ELF::R_AARCH64_CONDBR19: 155 case ELF::R_AARCH64_ADR_PREL_LO21: 156 case ELF::R_AARCH64_ADR_PREL_PG_HI21: 157 case ELF::R_AARCH64_ADR_PREL_PG_HI21_NC: 158 case ELF::R_AARCH64_LDST64_ABS_LO12_NC: 159 case ELF::R_AARCH64_ADD_ABS_LO12_NC: 160 case ELF::R_AARCH64_LDST128_ABS_LO12_NC: 161 case ELF::R_AARCH64_LDST32_ABS_LO12_NC: 162 case ELF::R_AARCH64_LDST16_ABS_LO12_NC: 163 case ELF::R_AARCH64_LDST8_ABS_LO12_NC: 164 case ELF::R_AARCH64_ADR_GOT_PAGE: 165 case ELF::R_AARCH64_TLSDESC_ADR_PREL21: 166 case ELF::R_AARCH64_TLSDESC_ADR_PAGE21: 167 case ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: 168 case ELF::R_AARCH64_TLSLE_ADD_TPREL_HI12: 169 case ELF::R_AARCH64_TLSLE_ADD_TPREL_LO12_NC: 170 case ELF::R_AARCH64_LD64_GOT_LO12_NC: 171 case ELF::R_AARCH64_TLSDESC_LD64_LO12: 172 case ELF::R_AARCH64_TLSDESC_ADD_LO12: 173 case ELF::R_AARCH64_TLSDESC_CALL: 174 case ELF::R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: 175 case ELF::R_AARCH64_PREL32: 176 case ELF::R_AARCH64_MOVW_UABS_G0: 177 case ELF::R_AARCH64_MOVW_UABS_G0_NC: 178 case ELF::R_AARCH64_MOVW_UABS_G1: 179 case ELF::R_AARCH64_MOVW_UABS_G1_NC: 180 case ELF::R_AARCH64_MOVW_UABS_G2: 181 case ELF::R_AARCH64_MOVW_UABS_G2_NC: 182 case ELF::R_AARCH64_MOVW_UABS_G3: 183 case ELF::R_AARCH64_ABS32: 184 return 4; 185 case ELF::R_AARCH64_ABS64: 186 case ELF::R_AARCH64_PREL64: 187 return 8; 188 } 189 } 190 191 static size_t getSizeForTypeRISCV(uint64_t Type) { 192 switch (Type) { 193 default: 194 errs() << object::getELFRelocationTypeName(ELF::EM_RISCV, Type) << '\n'; 195 llvm_unreachable("unsupported relocation type"); 196 case ELF::R_RISCV_RVC_JUMP: 197 case ELF::R_RISCV_RVC_BRANCH: 198 return 2; 199 case ELF::R_RISCV_JAL: 200 case ELF::R_RISCV_BRANCH: 201 case ELF::R_RISCV_PCREL_HI20: 202 case ELF::R_RISCV_PCREL_LO12_I: 203 case ELF::R_RISCV_PCREL_LO12_S: 204 case ELF::R_RISCV_32_PCREL: 205 case ELF::R_RISCV_CALL: 206 case ELF::R_RISCV_CALL_PLT: 207 case ELF::R_RISCV_ADD32: 208 case ELF::R_RISCV_SUB32: 209 case ELF::R_RISCV_HI20: 210 case ELF::R_RISCV_LO12_I: 211 case ELF::R_RISCV_LO12_S: 212 return 4; 213 case ELF::R_RISCV_64: 214 case ELF::R_RISCV_GOT_HI20: 215 // See extractValueRISCV for why this is necessary. 216 return 8; 217 } 218 } 219 220 static bool skipRelocationTypeX86(uint64_t Type) { 221 return Type == ELF::R_X86_64_NONE; 222 } 223 224 static bool skipRelocationTypeAArch64(uint64_t Type) { 225 return Type == ELF::R_AARCH64_NONE || Type == ELF::R_AARCH64_LD_PREL_LO19; 226 } 227 228 static bool skipRelocationTypeRISCV(uint64_t Type) { 229 switch (Type) { 230 default: 231 return false; 232 case ELF::R_RISCV_NONE: 233 case ELF::R_RISCV_RELAX: 234 return true; 235 } 236 } 237 238 static bool skipRelocationProcessX86(uint64_t &Type, uint64_t Contents) { 239 return false; 240 } 241 242 static bool skipRelocationProcessAArch64(uint64_t &Type, uint64_t Contents) { 243 auto IsMov = [](uint64_t Contents) -> bool { 244 // The bits 28-23 are 0b100101 245 return (Contents & 0x1f800000) == 0x12800000; 246 }; 247 248 auto IsB = [](uint64_t Contents) -> bool { 249 // The bits 31-26 are 0b000101 250 return (Contents & 0xfc000000) == 0x14000000; 251 }; 252 253 auto IsAdr = [](uint64_t Contents) -> bool { 254 // The bits 31-24 are 0b0xx10000 255 return (Contents & 0x9f000000) == 0x10000000; 256 }; 257 258 auto IsAddImm = [](uint64_t Contents) -> bool { 259 // The bits 30-23 are 0b00100010 260 return (Contents & 0x7F800000) == 0x11000000; 261 }; 262 263 auto IsNop = [](uint64_t Contents) -> bool { return Contents == 0xd503201f; }; 264 265 // The linker might eliminate the instruction and replace it with NOP, ignore 266 if (IsNop(Contents)) 267 return true; 268 269 // The linker might relax ADRP+LDR instruction sequence for loading symbol 270 // address from GOT table to ADRP+ADD sequence that would point to the 271 // binary-local symbol. Change relocation type in order to process it right. 272 if (Type == ELF::R_AARCH64_LD64_GOT_LO12_NC && IsAddImm(Contents)) { 273 Type = ELF::R_AARCH64_ADD_ABS_LO12_NC; 274 return false; 275 } 276 277 // The linker might perform TLS relocations relaxations, such as 278 // changed TLS access model (e.g. changed global dynamic model 279 // to initial exec), thus changing the instructions. The static 280 // relocations might be invalid at this point and we might no 281 // need to proccess these relocations anymore. 282 // More information could be found by searching 283 // elfNN_aarch64_tls_relax in bfd 284 switch (Type) { 285 default: 286 break; 287 case ELF::R_AARCH64_TLSDESC_LD64_LO12: 288 case ELF::R_AARCH64_TLSDESC_ADR_PAGE21: 289 case ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: 290 case ELF::R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: { 291 if (IsMov(Contents)) 292 return true; 293 } 294 } 295 296 // The linker might replace load/store instruction with jump and 297 // veneer due to errata 843419 298 // https://documentation-service.arm.com/static/5fa29fddb209f547eebd361d 299 // Thus load/store relocations for these instructions must be ignored 300 // NOTE: We only process GOT and TLS relocations this way since the 301 // addend used in load/store instructions won't change after bolt 302 // (it is important since the instruction in veneer won't have relocation) 303 switch (Type) { 304 default: 305 break; 306 case ELF::R_AARCH64_LD64_GOT_LO12_NC: 307 case ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: 308 case ELF::R_AARCH64_TLSDESC_LD64_LO12: { 309 if (IsB(Contents)) 310 return true; 311 } 312 } 313 314 // The linker might relax ADRP+ADD or ADRP+LDR sequences to the ADR+NOP 315 switch (Type) { 316 default: 317 break; 318 case ELF::R_AARCH64_ADR_PREL_PG_HI21: 319 case ELF::R_AARCH64_ADD_ABS_LO12_NC: 320 case ELF::R_AARCH64_ADR_GOT_PAGE: 321 case ELF::R_AARCH64_LD64_GOT_LO12_NC: 322 if (IsAdr(Contents)) 323 return true; 324 } 325 326 return false; 327 } 328 329 static bool skipRelocationProcessRISCV(uint64_t &Type, uint64_t Contents) { 330 return false; 331 } 332 333 static uint64_t encodeValueX86(uint64_t Type, uint64_t Value, uint64_t PC) { 334 switch (Type) { 335 default: 336 llvm_unreachable("unsupported relocation"); 337 case ELF::R_X86_64_64: 338 case ELF::R_X86_64_32: 339 break; 340 case ELF::R_X86_64_PC32: 341 Value -= PC; 342 break; 343 } 344 return Value; 345 } 346 347 static uint64_t encodeValueAArch64(uint64_t Type, uint64_t Value, uint64_t PC) { 348 switch (Type) { 349 default: 350 llvm_unreachable("unsupported relocation"); 351 case ELF::R_AARCH64_ABS32: 352 break; 353 case ELF::R_AARCH64_PREL16: 354 case ELF::R_AARCH64_PREL32: 355 case ELF::R_AARCH64_PREL64: 356 Value -= PC; 357 break; 358 case ELF::R_AARCH64_CALL26: 359 Value -= PC; 360 assert(isInt<28>(Value) && "only PC +/- 128MB is allowed for direct call"); 361 // Immediate goes in bits 25:0 of BL. 362 // OP 1001_01 goes in bits 31:26 of BL. 363 Value = ((Value >> 2) & 0x3ffffff) | 0x94000000ULL; 364 break; 365 } 366 return Value; 367 } 368 369 static uint64_t encodeValueRISCV(uint64_t Type, uint64_t Value, uint64_t PC) { 370 switch (Type) { 371 default: 372 llvm_unreachable("unsupported relocation"); 373 case ELF::R_RISCV_64: 374 break; 375 } 376 return Value; 377 } 378 379 static uint64_t extractValueX86(uint64_t Type, uint64_t Contents, uint64_t PC) { 380 if (Type == ELF::R_X86_64_32S) 381 return SignExtend64<32>(Contents); 382 if (Relocation::isPCRelative(Type)) 383 return SignExtend64(Contents, 8 * Relocation::getSizeForType(Type)); 384 return Contents; 385 } 386 387 static uint64_t extractValueAArch64(uint64_t Type, uint64_t Contents, 388 uint64_t PC) { 389 switch (Type) { 390 default: 391 errs() << object::getELFRelocationTypeName(ELF::EM_AARCH64, Type) << '\n'; 392 llvm_unreachable("unsupported relocation type"); 393 case ELF::R_AARCH64_ABS16: 394 case ELF::R_AARCH64_ABS32: 395 case ELF::R_AARCH64_ABS64: 396 return Contents; 397 case ELF::R_AARCH64_PREL16: 398 return static_cast<int64_t>(PC) + SignExtend64<16>(Contents & 0xffff); 399 case ELF::R_AARCH64_PREL32: 400 return static_cast<int64_t>(PC) + SignExtend64<32>(Contents & 0xffffffff); 401 case ELF::R_AARCH64_PREL64: 402 return static_cast<int64_t>(PC) + Contents; 403 case ELF::R_AARCH64_TLSDESC_CALL: 404 case ELF::R_AARCH64_JUMP26: 405 case ELF::R_AARCH64_CALL26: 406 // Immediate goes in bits 25:0 of B and BL. 407 Contents &= ~0xfffffffffc000000ULL; 408 return static_cast<int64_t>(PC) + SignExtend64<28>(Contents << 2); 409 case ELF::R_AARCH64_TSTBR14: 410 // Immediate:15:2 goes in bits 18:5 of TBZ, TBNZ 411 Contents &= ~0xfffffffffff8001fULL; 412 return static_cast<int64_t>(PC) + SignExtend64<16>(Contents >> 3); 413 case ELF::R_AARCH64_CONDBR19: 414 // Immediate:20:2 goes in bits 23:5 of Bcc, CBZ, CBNZ 415 Contents &= ~0xffffffffff00001fULL; 416 return static_cast<int64_t>(PC) + SignExtend64<21>(Contents >> 3); 417 case ELF::R_AARCH64_ADR_GOT_PAGE: 418 case ELF::R_AARCH64_TLSDESC_ADR_PREL21: 419 case ELF::R_AARCH64_TLSDESC_ADR_PAGE21: 420 case ELF::R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: 421 case ELF::R_AARCH64_ADR_PREL_LO21: 422 case ELF::R_AARCH64_ADR_PREL_PG_HI21: 423 case ELF::R_AARCH64_ADR_PREL_PG_HI21_NC: { 424 // Bits 32:12 of Symbol address goes in bits 30:29 + 23:5 of ADRP 425 // and ADR instructions 426 bool IsAdr = !!(((Contents >> 31) & 0x1) == 0); 427 Contents &= ~0xffffffff9f00001fUll; 428 uint64_t LowBits = (Contents >> 29) & 0x3; 429 uint64_t HighBits = (Contents >> 5) & 0x7ffff; 430 Contents = LowBits | (HighBits << 2); 431 if (IsAdr) 432 return static_cast<int64_t>(PC) + SignExtend64<21>(Contents); 433 434 // ADRP instruction 435 Contents = static_cast<int64_t>(PC) + SignExtend64<33>(Contents << 12); 436 Contents &= ~0xfffUll; 437 return Contents; 438 } 439 case ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: 440 case ELF::R_AARCH64_TLSDESC_LD64_LO12: 441 case ELF::R_AARCH64_LD64_GOT_LO12_NC: 442 case ELF::R_AARCH64_LDST64_ABS_LO12_NC: { 443 // Immediate goes in bits 21:10 of LD/ST instruction, taken 444 // from bits 11:3 of Symbol address 445 Contents &= ~0xffffffffffc003ffU; 446 return Contents >> (10 - 3); 447 } 448 case ELF::R_AARCH64_TLSLE_ADD_TPREL_HI12: 449 case ELF::R_AARCH64_TLSLE_ADD_TPREL_LO12_NC: 450 case ELF::R_AARCH64_TLSDESC_ADD_LO12: 451 case ELF::R_AARCH64_ADD_ABS_LO12_NC: { 452 // Immediate goes in bits 21:10 of ADD instruction 453 Contents &= ~0xffffffffffc003ffU; 454 return Contents >> (10 - 0); 455 } 456 case ELF::R_AARCH64_LDST128_ABS_LO12_NC: { 457 // Immediate goes in bits 21:10 of ADD instruction, taken 458 // from bits 11:4 of Symbol address 459 Contents &= ~0xffffffffffc003ffU; 460 return Contents >> (10 - 4); 461 } 462 case ELF::R_AARCH64_LDST32_ABS_LO12_NC: { 463 // Immediate goes in bits 21:10 of ADD instruction, taken 464 // from bits 11:2 of Symbol address 465 Contents &= ~0xffffffffffc003ffU; 466 return Contents >> (10 - 2); 467 } 468 case ELF::R_AARCH64_LDST16_ABS_LO12_NC: { 469 // Immediate goes in bits 21:10 of ADD instruction, taken 470 // from bits 11:1 of Symbol address 471 Contents &= ~0xffffffffffc003ffU; 472 return Contents >> (10 - 1); 473 } 474 case ELF::R_AARCH64_LDST8_ABS_LO12_NC: { 475 // Immediate goes in bits 21:10 of ADD instruction, taken 476 // from bits 11:0 of Symbol address 477 Contents &= ~0xffffffffffc003ffU; 478 return Contents >> (10 - 0); 479 } 480 case ELF::R_AARCH64_MOVW_UABS_G3: 481 case ELF::R_AARCH64_MOVW_UABS_G2_NC: 482 case ELF::R_AARCH64_MOVW_UABS_G2: 483 case ELF::R_AARCH64_MOVW_UABS_G1_NC: 484 case ELF::R_AARCH64_MOVW_UABS_G1: 485 case ELF::R_AARCH64_MOVW_UABS_G0_NC: 486 case ELF::R_AARCH64_MOVW_UABS_G0: 487 // The shift goest in bits 22:21 of MOV* instructions 488 uint8_t Shift = (Contents >> 21) & 0x3; 489 // Immediate goes in bits 20:5 490 Contents = (Contents >> 5) & 0xffff; 491 return Contents << (16 * Shift); 492 } 493 } 494 495 static uint64_t extractUImmRISCV(uint32_t Contents) { 496 return SignExtend64<32>(Contents & 0xfffff000); 497 } 498 499 static uint64_t extractIImmRISCV(uint32_t Contents) { 500 return SignExtend64<12>(Contents >> 20); 501 } 502 503 static uint64_t extractSImmRISCV(uint32_t Contents) { 504 return SignExtend64<12>(((Contents >> 7) & 0x1f) | ((Contents >> 25) << 5)); 505 } 506 507 static uint64_t extractJImmRISCV(uint32_t Contents) { 508 return SignExtend64<21>( 509 (((Contents >> 21) & 0x3ff) << 1) | (((Contents >> 20) & 0x1) << 11) | 510 (((Contents >> 12) & 0xff) << 12) | (((Contents >> 31) & 0x1) << 20)); 511 } 512 513 static uint64_t extractBImmRISCV(uint32_t Contents) { 514 return SignExtend64<13>( 515 (((Contents >> 8) & 0xf) << 1) | (((Contents >> 25) & 0x3f) << 5) | 516 (((Contents >> 7) & 0x1) << 11) | (((Contents >> 31) & 0x1) << 12)); 517 } 518 519 static uint64_t extractValueRISCV(uint64_t Type, uint64_t Contents, 520 uint64_t PC) { 521 switch (Type) { 522 default: 523 errs() << object::getELFRelocationTypeName(ELF::EM_RISCV, Type) << '\n'; 524 llvm_unreachable("unsupported relocation type"); 525 case ELF::R_RISCV_JAL: 526 return extractJImmRISCV(Contents); 527 case ELF::R_RISCV_CALL: 528 case ELF::R_RISCV_CALL_PLT: 529 return extractUImmRISCV(Contents); 530 case ELF::R_RISCV_BRANCH: 531 return extractBImmRISCV(Contents); 532 case ELF::R_RISCV_GOT_HI20: 533 // We need to know the exact address of the GOT entry so we extract the 534 // value from both the AUIPC and L[D|W]. We cannot rely on the symbol in the 535 // relocation for this since it simply refers to the object that is stored 536 // in the GOT entry, not to the entry itself. 537 return extractUImmRISCV(Contents & 0xffffffff) + 538 extractIImmRISCV(Contents >> 32); 539 case ELF::R_RISCV_PCREL_HI20: 540 case ELF::R_RISCV_HI20: 541 return extractUImmRISCV(Contents); 542 case ELF::R_RISCV_PCREL_LO12_I: 543 case ELF::R_RISCV_LO12_I: 544 return extractIImmRISCV(Contents); 545 case ELF::R_RISCV_PCREL_LO12_S: 546 case ELF::R_RISCV_LO12_S: 547 return extractSImmRISCV(Contents); 548 case ELF::R_RISCV_RVC_JUMP: 549 return SignExtend64<11>(Contents >> 2); 550 case ELF::R_RISCV_RVC_BRANCH: 551 return SignExtend64<8>(((Contents >> 2) & 0x1f) | ((Contents >> 5) & 0xe0)); 552 case ELF::R_RISCV_ADD32: 553 case ELF::R_RISCV_SUB32: 554 case ELF::R_RISCV_64: 555 return Contents; 556 } 557 } 558 559 static bool isGOTX86(uint64_t Type) { 560 switch (Type) { 561 default: 562 return false; 563 case ELF::R_X86_64_GOT32: 564 case ELF::R_X86_64_GOTPCREL: 565 case ELF::R_X86_64_GOTTPOFF: 566 case ELF::R_X86_64_GOTOFF64: 567 case ELF::R_X86_64_GOTPC32: 568 case ELF::R_X86_64_GOT64: 569 case ELF::R_X86_64_GOTPCREL64: 570 case ELF::R_X86_64_GOTPC64: 571 case ELF::R_X86_64_GOTPLT64: 572 case ELF::R_X86_64_GOTPC32_TLSDESC: 573 case ELF::R_X86_64_GOTPCRELX: 574 case ELF::R_X86_64_REX_GOTPCRELX: 575 return true; 576 } 577 } 578 579 static bool isGOTAArch64(uint64_t Type) { 580 switch (Type) { 581 default: 582 return false; 583 case ELF::R_AARCH64_ADR_GOT_PAGE: 584 case ELF::R_AARCH64_LD64_GOT_LO12_NC: 585 case ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: 586 case ELF::R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: 587 case ELF::R_AARCH64_TLSDESC_ADR_PREL21: 588 case ELF::R_AARCH64_TLSDESC_ADR_PAGE21: 589 case ELF::R_AARCH64_TLSDESC_LD64_LO12: 590 case ELF::R_AARCH64_TLSDESC_ADD_LO12: 591 case ELF::R_AARCH64_TLSDESC_CALL: 592 return true; 593 } 594 } 595 596 static bool isGOTRISCV(uint64_t Type) { 597 switch (Type) { 598 default: 599 return false; 600 case ELF::R_RISCV_GOT_HI20: 601 return true; 602 } 603 } 604 605 static bool isTLSX86(uint64_t Type) { 606 switch (Type) { 607 default: 608 return false; 609 case ELF::R_X86_64_TPOFF32: 610 case ELF::R_X86_64_TPOFF64: 611 case ELF::R_X86_64_GOTTPOFF: 612 return true; 613 } 614 } 615 616 static bool isTLSAArch64(uint64_t Type) { 617 switch (Type) { 618 default: 619 return false; 620 case ELF::R_AARCH64_TLSDESC_ADR_PREL21: 621 case ELF::R_AARCH64_TLSDESC_ADR_PAGE21: 622 case ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: 623 case ELF::R_AARCH64_TLSLE_ADD_TPREL_HI12: 624 case ELF::R_AARCH64_TLSLE_ADD_TPREL_LO12_NC: 625 case ELF::R_AARCH64_TLSDESC_LD64_LO12: 626 case ELF::R_AARCH64_TLSDESC_ADD_LO12: 627 case ELF::R_AARCH64_TLSDESC_CALL: 628 case ELF::R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: 629 return true; 630 } 631 } 632 633 static bool isTLSRISCV(uint64_t Type) { 634 switch (Type) { 635 default: 636 return false; 637 } 638 } 639 640 static bool isPCRelativeX86(uint64_t Type) { 641 switch (Type) { 642 default: 643 llvm_unreachable("Unknown relocation type"); 644 case ELF::R_X86_64_64: 645 case ELF::R_X86_64_32: 646 case ELF::R_X86_64_32S: 647 case ELF::R_X86_64_16: 648 case ELF::R_X86_64_8: 649 case ELF::R_X86_64_TPOFF32: 650 return false; 651 case ELF::R_X86_64_PC8: 652 case ELF::R_X86_64_PC32: 653 case ELF::R_X86_64_PC64: 654 case ELF::R_X86_64_GOTPCREL: 655 case ELF::R_X86_64_PLT32: 656 case ELF::R_X86_64_GOTOFF64: 657 case ELF::R_X86_64_GOTPC32: 658 case ELF::R_X86_64_GOTTPOFF: 659 case ELF::R_X86_64_GOTPCRELX: 660 case ELF::R_X86_64_REX_GOTPCRELX: 661 return true; 662 } 663 } 664 665 static bool isPCRelativeAArch64(uint64_t Type) { 666 switch (Type) { 667 default: 668 llvm_unreachable("Unknown relocation type"); 669 case ELF::R_AARCH64_ABS16: 670 case ELF::R_AARCH64_ABS32: 671 case ELF::R_AARCH64_ABS64: 672 case ELF::R_AARCH64_LDST64_ABS_LO12_NC: 673 case ELF::R_AARCH64_ADD_ABS_LO12_NC: 674 case ELF::R_AARCH64_LDST128_ABS_LO12_NC: 675 case ELF::R_AARCH64_LDST32_ABS_LO12_NC: 676 case ELF::R_AARCH64_LDST16_ABS_LO12_NC: 677 case ELF::R_AARCH64_LDST8_ABS_LO12_NC: 678 case ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: 679 case ELF::R_AARCH64_TLSLE_ADD_TPREL_HI12: 680 case ELF::R_AARCH64_TLSLE_ADD_TPREL_LO12_NC: 681 case ELF::R_AARCH64_LD64_GOT_LO12_NC: 682 case ELF::R_AARCH64_TLSDESC_LD64_LO12: 683 case ELF::R_AARCH64_TLSDESC_ADD_LO12: 684 case ELF::R_AARCH64_MOVW_UABS_G0: 685 case ELF::R_AARCH64_MOVW_UABS_G0_NC: 686 case ELF::R_AARCH64_MOVW_UABS_G1: 687 case ELF::R_AARCH64_MOVW_UABS_G1_NC: 688 case ELF::R_AARCH64_MOVW_UABS_G2: 689 case ELF::R_AARCH64_MOVW_UABS_G2_NC: 690 case ELF::R_AARCH64_MOVW_UABS_G3: 691 return false; 692 case ELF::R_AARCH64_TLSDESC_CALL: 693 case ELF::R_AARCH64_CALL26: 694 case ELF::R_AARCH64_JUMP26: 695 case ELF::R_AARCH64_TSTBR14: 696 case ELF::R_AARCH64_CONDBR19: 697 case ELF::R_AARCH64_ADR_PREL_LO21: 698 case ELF::R_AARCH64_ADR_PREL_PG_HI21: 699 case ELF::R_AARCH64_ADR_PREL_PG_HI21_NC: 700 case ELF::R_AARCH64_ADR_GOT_PAGE: 701 case ELF::R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: 702 case ELF::R_AARCH64_TLSDESC_ADR_PREL21: 703 case ELF::R_AARCH64_TLSDESC_ADR_PAGE21: 704 case ELF::R_AARCH64_PREL16: 705 case ELF::R_AARCH64_PREL32: 706 case ELF::R_AARCH64_PREL64: 707 return true; 708 } 709 } 710 711 static bool isPCRelativeRISCV(uint64_t Type) { 712 switch (Type) { 713 default: 714 llvm_unreachable("Unknown relocation type"); 715 case ELF::R_RISCV_ADD32: 716 case ELF::R_RISCV_SUB32: 717 case ELF::R_RISCV_HI20: 718 case ELF::R_RISCV_LO12_I: 719 case ELF::R_RISCV_LO12_S: 720 case ELF::R_RISCV_64: 721 return false; 722 case ELF::R_RISCV_JAL: 723 case ELF::R_RISCV_CALL: 724 case ELF::R_RISCV_CALL_PLT: 725 case ELF::R_RISCV_BRANCH: 726 case ELF::R_RISCV_GOT_HI20: 727 case ELF::R_RISCV_PCREL_HI20: 728 case ELF::R_RISCV_PCREL_LO12_I: 729 case ELF::R_RISCV_PCREL_LO12_S: 730 case ELF::R_RISCV_RVC_JUMP: 731 case ELF::R_RISCV_RVC_BRANCH: 732 case ELF::R_RISCV_32_PCREL: 733 return true; 734 } 735 } 736 737 bool Relocation::isSupported(uint64_t Type) { 738 if (Arch == Triple::aarch64) 739 return isSupportedAArch64(Type); 740 if (Arch == Triple::riscv64) 741 return isSupportedRISCV(Type); 742 return isSupportedX86(Type); 743 } 744 745 size_t Relocation::getSizeForType(uint64_t Type) { 746 if (Arch == Triple::aarch64) 747 return getSizeForTypeAArch64(Type); 748 if (Arch == Triple::riscv64) 749 return getSizeForTypeRISCV(Type); 750 return getSizeForTypeX86(Type); 751 } 752 753 bool Relocation::skipRelocationType(uint64_t Type) { 754 if (Arch == Triple::aarch64) 755 return skipRelocationTypeAArch64(Type); 756 if (Arch == Triple::riscv64) 757 return skipRelocationTypeRISCV(Type); 758 return skipRelocationTypeX86(Type); 759 } 760 761 bool Relocation::skipRelocationProcess(uint64_t &Type, uint64_t Contents) { 762 if (Arch == Triple::aarch64) 763 return skipRelocationProcessAArch64(Type, Contents); 764 if (Arch == Triple::riscv64) 765 skipRelocationProcessRISCV(Type, Contents); 766 return skipRelocationProcessX86(Type, Contents); 767 } 768 769 uint64_t Relocation::encodeValue(uint64_t Type, uint64_t Value, uint64_t PC) { 770 if (Arch == Triple::aarch64) 771 return encodeValueAArch64(Type, Value, PC); 772 if (Arch == Triple::riscv64) 773 return encodeValueRISCV(Type, Value, PC); 774 return encodeValueX86(Type, Value, PC); 775 } 776 777 uint64_t Relocation::extractValue(uint64_t Type, uint64_t Contents, 778 uint64_t PC) { 779 if (Arch == Triple::aarch64) 780 return extractValueAArch64(Type, Contents, PC); 781 if (Arch == Triple::riscv64) 782 return extractValueRISCV(Type, Contents, PC); 783 return extractValueX86(Type, Contents, PC); 784 } 785 786 bool Relocation::isGOT(uint64_t Type) { 787 if (Arch == Triple::aarch64) 788 return isGOTAArch64(Type); 789 if (Arch == Triple::riscv64) 790 return isGOTRISCV(Type); 791 return isGOTX86(Type); 792 } 793 794 bool Relocation::isX86GOTPCRELX(uint64_t Type) { 795 if (Arch != Triple::x86_64) 796 return false; 797 return Type == ELF::R_X86_64_GOTPCRELX || Type == ELF::R_X86_64_REX_GOTPCRELX; 798 } 799 800 bool Relocation::isNone(uint64_t Type) { return Type == getNone(); } 801 802 bool Relocation::isRelative(uint64_t Type) { 803 if (Arch == Triple::aarch64) 804 return Type == ELF::R_AARCH64_RELATIVE; 805 if (Arch == Triple::riscv64) 806 return Type == ELF::R_RISCV_RELATIVE; 807 return Type == ELF::R_X86_64_RELATIVE; 808 } 809 810 bool Relocation::isIRelative(uint64_t Type) { 811 if (Arch == Triple::aarch64) 812 return Type == ELF::R_AARCH64_IRELATIVE; 813 if (Arch == Triple::riscv64) 814 llvm_unreachable("not implemented"); 815 return Type == ELF::R_X86_64_IRELATIVE; 816 } 817 818 bool Relocation::isTLS(uint64_t Type) { 819 if (Arch == Triple::aarch64) 820 return isTLSAArch64(Type); 821 if (Arch == Triple::riscv64) 822 return isTLSRISCV(Type); 823 return isTLSX86(Type); 824 } 825 826 uint64_t Relocation::getNone() { 827 if (Arch == Triple::aarch64) 828 return ELF::R_AARCH64_NONE; 829 if (Arch == Triple::riscv64) 830 return ELF::R_RISCV_NONE; 831 return ELF::R_X86_64_NONE; 832 } 833 834 uint64_t Relocation::getPC32() { 835 if (Arch == Triple::aarch64) 836 return ELF::R_AARCH64_PREL32; 837 if (Arch == Triple::riscv64) 838 return ELF::R_RISCV_32_PCREL; 839 return ELF::R_X86_64_PC32; 840 } 841 842 uint64_t Relocation::getPC64() { 843 if (Arch == Triple::aarch64) 844 return ELF::R_AARCH64_PREL64; 845 if (Arch == Triple::riscv64) 846 llvm_unreachable("not implemented"); 847 return ELF::R_X86_64_PC64; 848 } 849 850 bool Relocation::isPCRelative(uint64_t Type) { 851 if (Arch == Triple::aarch64) 852 return isPCRelativeAArch64(Type); 853 if (Arch == Triple::riscv64) 854 return isPCRelativeRISCV(Type); 855 return isPCRelativeX86(Type); 856 } 857 858 uint64_t Relocation::getAbs64() { 859 if (Arch == Triple::aarch64) 860 return ELF::R_AARCH64_ABS64; 861 if (Arch == Triple::riscv64) 862 return ELF::R_RISCV_64; 863 return ELF::R_X86_64_64; 864 } 865 866 uint64_t Relocation::getRelative() { 867 if (Arch == Triple::aarch64) 868 return ELF::R_AARCH64_RELATIVE; 869 return ELF::R_X86_64_RELATIVE; 870 } 871 872 size_t Relocation::emit(MCStreamer *Streamer) const { 873 const size_t Size = getSizeForType(Type); 874 const auto *Value = createExpr(Streamer); 875 Streamer->emitValue(Value, Size); 876 return Size; 877 } 878 879 const MCExpr *Relocation::createExpr(MCStreamer *Streamer) const { 880 MCContext &Ctx = Streamer->getContext(); 881 const MCExpr *Value = nullptr; 882 883 if (Symbol && Addend) { 884 Value = MCBinaryExpr::createAdd(MCSymbolRefExpr::create(Symbol, Ctx), 885 MCConstantExpr::create(Addend, Ctx), Ctx); 886 } else if (Symbol) { 887 Value = MCSymbolRefExpr::create(Symbol, Ctx); 888 } else { 889 Value = MCConstantExpr::create(Addend, Ctx); 890 } 891 892 if (isPCRelative(Type)) { 893 MCSymbol *TempLabel = Ctx.createNamedTempSymbol(); 894 Streamer->emitLabel(TempLabel); 895 Value = MCBinaryExpr::createSub( 896 Value, MCSymbolRefExpr::create(TempLabel, Ctx), Ctx); 897 } 898 899 return Value; 900 } 901 902 const MCExpr *Relocation::createExpr(MCStreamer *Streamer, 903 const MCExpr *RetainedValue) const { 904 const auto *Value = createExpr(Streamer); 905 906 if (RetainedValue) { 907 Value = MCBinaryExpr::create(getComposeOpcodeFor(Type), RetainedValue, 908 Value, Streamer->getContext()); 909 } 910 911 return Value; 912 } 913 914 MCBinaryExpr::Opcode Relocation::getComposeOpcodeFor(uint64_t Type) { 915 assert(Arch == Triple::riscv64 && "only implemented for RISC-V"); 916 917 switch (Type) { 918 default: 919 llvm_unreachable("not implemented"); 920 case ELF::R_RISCV_ADD32: 921 return MCBinaryExpr::Add; 922 case ELF::R_RISCV_SUB32: 923 return MCBinaryExpr::Sub; 924 } 925 } 926 927 #define ELF_RELOC(name, value) #name, 928 929 void Relocation::print(raw_ostream &OS) const { 930 static const char *X86RelocNames[] = { 931 #include "llvm/BinaryFormat/ELFRelocs/x86_64.def" 932 }; 933 static const char *AArch64RelocNames[] = { 934 #include "llvm/BinaryFormat/ELFRelocs/AArch64.def" 935 }; 936 if (Arch == Triple::aarch64) 937 OS << AArch64RelocNames[Type]; 938 else if (Arch == Triple::riscv64) { 939 // RISC-V relocations are not sequentially numbered so we cannot use an 940 // array 941 switch (Type) { 942 default: 943 llvm_unreachable("illegal RISC-V relocation"); 944 #undef ELF_RELOC 945 #define ELF_RELOC(name, value) \ 946 case value: \ 947 OS << #name; \ 948 break; 949 #include "llvm/BinaryFormat/ELFRelocs/RISCV.def" 950 } 951 } else 952 OS << X86RelocNames[Type]; 953 OS << ", 0x" << Twine::utohexstr(Offset); 954 if (Symbol) { 955 OS << ", " << Symbol->getName(); 956 } 957 if (int64_t(Addend) < 0) 958 OS << ", -0x" << Twine::utohexstr(-int64_t(Addend)); 959 else 960 OS << ", 0x" << Twine::utohexstr(Addend); 961 OS << ", 0x" << Twine::utohexstr(Value); 962 } 963