1 //===- bolt/Core/Relocation.cpp - Object file relocations -----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the Relocation class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "bolt/Core/Relocation.h" 14 #include "llvm/MC/MCContext.h" 15 #include "llvm/MC/MCExpr.h" 16 #include "llvm/MC/MCStreamer.h" 17 #include "llvm/MC/MCSymbol.h" 18 #include "llvm/Object/ELF.h" 19 20 using namespace llvm; 21 using namespace bolt; 22 23 namespace ELFReserved { 24 enum { 25 R_RISCV_TPREL_I = 49, 26 R_RISCV_TPREL_S = 50, 27 }; 28 } // namespace ELFReserved 29 30 Triple::ArchType Relocation::Arch; 31 32 static bool isSupportedX86(uint64_t Type) { 33 switch (Type) { 34 default: 35 return false; 36 case ELF::R_X86_64_8: 37 case ELF::R_X86_64_16: 38 case ELF::R_X86_64_32: 39 case ELF::R_X86_64_32S: 40 case ELF::R_X86_64_64: 41 case ELF::R_X86_64_PC8: 42 case ELF::R_X86_64_PC32: 43 case ELF::R_X86_64_PC64: 44 case ELF::R_X86_64_PLT32: 45 case ELF::R_X86_64_GOTPC64: 46 case ELF::R_X86_64_GOTPCREL: 47 case ELF::R_X86_64_GOTTPOFF: 48 case ELF::R_X86_64_TPOFF32: 49 case ELF::R_X86_64_GOTPCRELX: 50 case ELF::R_X86_64_REX_GOTPCRELX: 51 return true; 52 } 53 } 54 55 static bool isSupportedAArch64(uint64_t Type) { 56 switch (Type) { 57 default: 58 return false; 59 case ELF::R_AARCH64_CALL26: 60 case ELF::R_AARCH64_JUMP26: 61 case ELF::R_AARCH64_TSTBR14: 62 case ELF::R_AARCH64_CONDBR19: 63 case ELF::R_AARCH64_ADR_PREL_LO21: 64 case ELF::R_AARCH64_ADR_PREL_PG_HI21: 65 case ELF::R_AARCH64_ADR_PREL_PG_HI21_NC: 66 case ELF::R_AARCH64_LDST64_ABS_LO12_NC: 67 case ELF::R_AARCH64_ADD_ABS_LO12_NC: 68 case ELF::R_AARCH64_LDST128_ABS_LO12_NC: 69 case ELF::R_AARCH64_LDST32_ABS_LO12_NC: 70 case ELF::R_AARCH64_LDST16_ABS_LO12_NC: 71 case ELF::R_AARCH64_LDST8_ABS_LO12_NC: 72 case ELF::R_AARCH64_ADR_GOT_PAGE: 73 case ELF::R_AARCH64_TLSDESC_ADR_PREL21: 74 case ELF::R_AARCH64_TLSDESC_ADR_PAGE21: 75 case ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: 76 case ELF::R_AARCH64_TLSLE_ADD_TPREL_HI12: 77 case ELF::R_AARCH64_TLSLE_ADD_TPREL_LO12_NC: 78 case ELF::R_AARCH64_LD64_GOT_LO12_NC: 79 case ELF::R_AARCH64_TLSDESC_LD64_LO12: 80 case ELF::R_AARCH64_TLSDESC_ADD_LO12: 81 case ELF::R_AARCH64_TLSDESC_CALL: 82 case ELF::R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: 83 case ELF::R_AARCH64_PREL16: 84 case ELF::R_AARCH64_PREL32: 85 case ELF::R_AARCH64_PREL64: 86 case ELF::R_AARCH64_ABS16: 87 case ELF::R_AARCH64_ABS32: 88 case ELF::R_AARCH64_ABS64: 89 case ELF::R_AARCH64_MOVW_UABS_G0: 90 case ELF::R_AARCH64_MOVW_UABS_G0_NC: 91 case ELF::R_AARCH64_MOVW_UABS_G1: 92 case ELF::R_AARCH64_MOVW_UABS_G1_NC: 93 case ELF::R_AARCH64_MOVW_UABS_G2: 94 case ELF::R_AARCH64_MOVW_UABS_G2_NC: 95 case ELF::R_AARCH64_MOVW_UABS_G3: 96 return true; 97 } 98 } 99 100 static bool isSupportedRISCV(uint64_t Type) { 101 switch (Type) { 102 default: 103 return false; 104 case ELF::R_RISCV_JAL: 105 case ELF::R_RISCV_CALL: 106 case ELF::R_RISCV_CALL_PLT: 107 case ELF::R_RISCV_BRANCH: 108 case ELF::R_RISCV_RELAX: 109 case ELF::R_RISCV_GOT_HI20: 110 case ELF::R_RISCV_PCREL_HI20: 111 case ELF::R_RISCV_PCREL_LO12_I: 112 case ELF::R_RISCV_PCREL_LO12_S: 113 case ELF::R_RISCV_RVC_JUMP: 114 case ELF::R_RISCV_RVC_BRANCH: 115 case ELF::R_RISCV_ADD32: 116 case ELF::R_RISCV_SUB32: 117 case ELF::R_RISCV_HI20: 118 case ELF::R_RISCV_LO12_I: 119 case ELF::R_RISCV_LO12_S: 120 case ELF::R_RISCV_64: 121 case ELF::R_RISCV_TLS_GOT_HI20: 122 case ELF::R_RISCV_TPREL_HI20: 123 case ELF::R_RISCV_TPREL_ADD: 124 case ELF::R_RISCV_TPREL_LO12_I: 125 case ELF::R_RISCV_TPREL_LO12_S: 126 case ELFReserved::R_RISCV_TPREL_I: 127 case ELFReserved::R_RISCV_TPREL_S: 128 return true; 129 } 130 } 131 132 static size_t getSizeForTypeX86(uint64_t Type) { 133 switch (Type) { 134 default: 135 errs() << object::getELFRelocationTypeName(ELF::EM_X86_64, Type) << '\n'; 136 llvm_unreachable("unsupported relocation type"); 137 case ELF::R_X86_64_8: 138 case ELF::R_X86_64_PC8: 139 return 1; 140 case ELF::R_X86_64_16: 141 return 2; 142 case ELF::R_X86_64_PLT32: 143 case ELF::R_X86_64_PC32: 144 case ELF::R_X86_64_32S: 145 case ELF::R_X86_64_32: 146 case ELF::R_X86_64_GOTPCREL: 147 case ELF::R_X86_64_GOTTPOFF: 148 case ELF::R_X86_64_TPOFF32: 149 case ELF::R_X86_64_GOTPCRELX: 150 case ELF::R_X86_64_REX_GOTPCRELX: 151 return 4; 152 case ELF::R_X86_64_PC64: 153 case ELF::R_X86_64_64: 154 case ELF::R_X86_64_GOTPC64: 155 return 8; 156 } 157 } 158 159 static size_t getSizeForTypeAArch64(uint64_t Type) { 160 switch (Type) { 161 default: 162 errs() << object::getELFRelocationTypeName(ELF::EM_AARCH64, Type) << '\n'; 163 llvm_unreachable("unsupported relocation type"); 164 case ELF::R_AARCH64_ABS16: 165 case ELF::R_AARCH64_PREL16: 166 return 2; 167 case ELF::R_AARCH64_CALL26: 168 case ELF::R_AARCH64_JUMP26: 169 case ELF::R_AARCH64_TSTBR14: 170 case ELF::R_AARCH64_CONDBR19: 171 case ELF::R_AARCH64_ADR_PREL_LO21: 172 case ELF::R_AARCH64_ADR_PREL_PG_HI21: 173 case ELF::R_AARCH64_ADR_PREL_PG_HI21_NC: 174 case ELF::R_AARCH64_LDST64_ABS_LO12_NC: 175 case ELF::R_AARCH64_ADD_ABS_LO12_NC: 176 case ELF::R_AARCH64_LDST128_ABS_LO12_NC: 177 case ELF::R_AARCH64_LDST32_ABS_LO12_NC: 178 case ELF::R_AARCH64_LDST16_ABS_LO12_NC: 179 case ELF::R_AARCH64_LDST8_ABS_LO12_NC: 180 case ELF::R_AARCH64_ADR_GOT_PAGE: 181 case ELF::R_AARCH64_TLSDESC_ADR_PREL21: 182 case ELF::R_AARCH64_TLSDESC_ADR_PAGE21: 183 case ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: 184 case ELF::R_AARCH64_TLSLE_ADD_TPREL_HI12: 185 case ELF::R_AARCH64_TLSLE_ADD_TPREL_LO12_NC: 186 case ELF::R_AARCH64_LD64_GOT_LO12_NC: 187 case ELF::R_AARCH64_TLSDESC_LD64_LO12: 188 case ELF::R_AARCH64_TLSDESC_ADD_LO12: 189 case ELF::R_AARCH64_TLSDESC_CALL: 190 case ELF::R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: 191 case ELF::R_AARCH64_PREL32: 192 case ELF::R_AARCH64_MOVW_UABS_G0: 193 case ELF::R_AARCH64_MOVW_UABS_G0_NC: 194 case ELF::R_AARCH64_MOVW_UABS_G1: 195 case ELF::R_AARCH64_MOVW_UABS_G1_NC: 196 case ELF::R_AARCH64_MOVW_UABS_G2: 197 case ELF::R_AARCH64_MOVW_UABS_G2_NC: 198 case ELF::R_AARCH64_MOVW_UABS_G3: 199 case ELF::R_AARCH64_ABS32: 200 return 4; 201 case ELF::R_AARCH64_ABS64: 202 case ELF::R_AARCH64_PREL64: 203 return 8; 204 } 205 } 206 207 static size_t getSizeForTypeRISCV(uint64_t Type) { 208 switch (Type) { 209 default: 210 errs() << object::getELFRelocationTypeName(ELF::EM_RISCV, Type) << '\n'; 211 llvm_unreachable("unsupported relocation type"); 212 case ELF::R_RISCV_RVC_JUMP: 213 case ELF::R_RISCV_RVC_BRANCH: 214 return 2; 215 case ELF::R_RISCV_JAL: 216 case ELF::R_RISCV_BRANCH: 217 case ELF::R_RISCV_PCREL_HI20: 218 case ELF::R_RISCV_PCREL_LO12_I: 219 case ELF::R_RISCV_PCREL_LO12_S: 220 case ELF::R_RISCV_32_PCREL: 221 case ELF::R_RISCV_CALL: 222 case ELF::R_RISCV_CALL_PLT: 223 case ELF::R_RISCV_ADD32: 224 case ELF::R_RISCV_SUB32: 225 case ELF::R_RISCV_HI20: 226 case ELF::R_RISCV_LO12_I: 227 case ELF::R_RISCV_LO12_S: 228 return 4; 229 case ELF::R_RISCV_64: 230 case ELF::R_RISCV_GOT_HI20: 231 case ELF::R_RISCV_TLS_GOT_HI20: 232 // See extractValueRISCV for why this is necessary. 233 return 8; 234 } 235 } 236 237 static bool skipRelocationTypeX86(uint64_t Type) { 238 return Type == ELF::R_X86_64_NONE; 239 } 240 241 static bool skipRelocationTypeAArch64(uint64_t Type) { 242 return Type == ELF::R_AARCH64_NONE || Type == ELF::R_AARCH64_LD_PREL_LO19; 243 } 244 245 static bool skipRelocationTypeRISCV(uint64_t Type) { 246 switch (Type) { 247 default: 248 return false; 249 case ELF::R_RISCV_NONE: 250 case ELF::R_RISCV_RELAX: 251 return true; 252 } 253 } 254 255 static bool skipRelocationProcessX86(uint64_t &Type, uint64_t Contents) { 256 return false; 257 } 258 259 static bool skipRelocationProcessAArch64(uint64_t &Type, uint64_t Contents) { 260 auto IsMov = [](uint64_t Contents) -> bool { 261 // The bits 28-23 are 0b100101 262 return (Contents & 0x1f800000) == 0x12800000; 263 }; 264 265 auto IsB = [](uint64_t Contents) -> bool { 266 // The bits 31-26 are 0b000101 267 return (Contents & 0xfc000000) == 0x14000000; 268 }; 269 270 auto IsAdr = [](uint64_t Contents) -> bool { 271 // The bits 31-24 are 0b0xx10000 272 return (Contents & 0x9f000000) == 0x10000000; 273 }; 274 275 auto IsAddImm = [](uint64_t Contents) -> bool { 276 // The bits 30-23 are 0b00100010 277 return (Contents & 0x7F800000) == 0x11000000; 278 }; 279 280 auto IsNop = [](uint64_t Contents) -> bool { return Contents == 0xd503201f; }; 281 282 // The linker might eliminate the instruction and replace it with NOP, ignore 283 if (IsNop(Contents)) 284 return true; 285 286 // The linker might relax ADRP+LDR instruction sequence for loading symbol 287 // address from GOT table to ADRP+ADD sequence that would point to the 288 // binary-local symbol. Change relocation type in order to process it right. 289 if (Type == ELF::R_AARCH64_LD64_GOT_LO12_NC && IsAddImm(Contents)) { 290 Type = ELF::R_AARCH64_ADD_ABS_LO12_NC; 291 return false; 292 } 293 294 // The linker might perform TLS relocations relaxations, such as 295 // changed TLS access model (e.g. changed global dynamic model 296 // to initial exec), thus changing the instructions. The static 297 // relocations might be invalid at this point and we might no 298 // need to process these relocations anymore. 299 // More information could be found by searching 300 // elfNN_aarch64_tls_relax in bfd 301 switch (Type) { 302 default: 303 break; 304 case ELF::R_AARCH64_TLSDESC_LD64_LO12: 305 case ELF::R_AARCH64_TLSDESC_ADR_PAGE21: 306 case ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: 307 case ELF::R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: { 308 if (IsMov(Contents)) 309 return true; 310 } 311 } 312 313 // The linker might replace load/store instruction with jump and 314 // veneer due to errata 843419 315 // https://documentation-service.arm.com/static/5fa29fddb209f547eebd361d 316 // Thus load/store relocations for these instructions must be ignored 317 // NOTE: We only process GOT and TLS relocations this way since the 318 // addend used in load/store instructions won't change after bolt 319 // (it is important since the instruction in veneer won't have relocation) 320 switch (Type) { 321 default: 322 break; 323 case ELF::R_AARCH64_LD64_GOT_LO12_NC: 324 case ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: 325 case ELF::R_AARCH64_TLSDESC_LD64_LO12: { 326 if (IsB(Contents)) 327 return true; 328 } 329 } 330 331 // The linker might relax ADRP+ADD or ADRP+LDR sequences to the ADR+NOP 332 switch (Type) { 333 default: 334 break; 335 case ELF::R_AARCH64_ADR_PREL_PG_HI21: 336 case ELF::R_AARCH64_ADD_ABS_LO12_NC: 337 case ELF::R_AARCH64_ADR_GOT_PAGE: 338 case ELF::R_AARCH64_LD64_GOT_LO12_NC: 339 if (IsAdr(Contents)) 340 return true; 341 } 342 343 return false; 344 } 345 346 static bool skipRelocationProcessRISCV(uint64_t &Type, uint64_t Contents) { 347 return false; 348 } 349 350 static uint64_t encodeValueX86(uint64_t Type, uint64_t Value, uint64_t PC) { 351 switch (Type) { 352 default: 353 llvm_unreachable("unsupported relocation"); 354 case ELF::R_X86_64_64: 355 case ELF::R_X86_64_32: 356 break; 357 case ELF::R_X86_64_PC32: 358 Value -= PC; 359 break; 360 } 361 return Value; 362 } 363 364 static uint64_t encodeValueAArch64(uint64_t Type, uint64_t Value, uint64_t PC) { 365 switch (Type) { 366 default: 367 llvm_unreachable("unsupported relocation"); 368 case ELF::R_AARCH64_ABS16: 369 case ELF::R_AARCH64_ABS32: 370 case ELF::R_AARCH64_ABS64: 371 break; 372 case ELF::R_AARCH64_PREL16: 373 case ELF::R_AARCH64_PREL32: 374 case ELF::R_AARCH64_PREL64: 375 Value -= PC; 376 break; 377 case ELF::R_AARCH64_CALL26: 378 Value -= PC; 379 assert(isInt<28>(Value) && "only PC +/- 128MB is allowed for direct call"); 380 // Immediate goes in bits 25:0 of BL. 381 // OP 1001_01 goes in bits 31:26 of BL. 382 Value = ((Value >> 2) & 0x3ffffff) | 0x94000000ULL; 383 break; 384 } 385 return Value; 386 } 387 388 static uint64_t encodeValueRISCV(uint64_t Type, uint64_t Value, uint64_t PC) { 389 switch (Type) { 390 default: 391 llvm_unreachable("unsupported relocation"); 392 case ELF::R_RISCV_64: 393 break; 394 } 395 return Value; 396 } 397 398 static uint64_t extractValueX86(uint64_t Type, uint64_t Contents, uint64_t PC) { 399 if (Type == ELF::R_X86_64_32S) 400 return SignExtend64<32>(Contents); 401 if (Relocation::isPCRelative(Type)) 402 return SignExtend64(Contents, 8 * Relocation::getSizeForType(Type)); 403 return Contents; 404 } 405 406 static uint64_t extractValueAArch64(uint64_t Type, uint64_t Contents, 407 uint64_t PC) { 408 switch (Type) { 409 default: 410 errs() << object::getELFRelocationTypeName(ELF::EM_AARCH64, Type) << '\n'; 411 llvm_unreachable("unsupported relocation type"); 412 case ELF::R_AARCH64_ABS16: 413 case ELF::R_AARCH64_ABS32: 414 case ELF::R_AARCH64_ABS64: 415 return Contents; 416 case ELF::R_AARCH64_PREL16: 417 return static_cast<int64_t>(PC) + SignExtend64<16>(Contents & 0xffff); 418 case ELF::R_AARCH64_PREL32: 419 return static_cast<int64_t>(PC) + SignExtend64<32>(Contents & 0xffffffff); 420 case ELF::R_AARCH64_PREL64: 421 return static_cast<int64_t>(PC) + Contents; 422 case ELF::R_AARCH64_TLSDESC_CALL: 423 case ELF::R_AARCH64_JUMP26: 424 case ELF::R_AARCH64_CALL26: 425 // Immediate goes in bits 25:0 of B and BL. 426 Contents &= ~0xfffffffffc000000ULL; 427 return static_cast<int64_t>(PC) + SignExtend64<28>(Contents << 2); 428 case ELF::R_AARCH64_TSTBR14: 429 // Immediate:15:2 goes in bits 18:5 of TBZ, TBNZ 430 Contents &= ~0xfffffffffff8001fULL; 431 return static_cast<int64_t>(PC) + SignExtend64<16>(Contents >> 3); 432 case ELF::R_AARCH64_CONDBR19: 433 // Immediate:20:2 goes in bits 23:5 of Bcc, CBZ, CBNZ 434 Contents &= ~0xffffffffff00001fULL; 435 return static_cast<int64_t>(PC) + SignExtend64<21>(Contents >> 3); 436 case ELF::R_AARCH64_ADR_GOT_PAGE: 437 case ELF::R_AARCH64_TLSDESC_ADR_PREL21: 438 case ELF::R_AARCH64_TLSDESC_ADR_PAGE21: 439 case ELF::R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: 440 case ELF::R_AARCH64_ADR_PREL_LO21: 441 case ELF::R_AARCH64_ADR_PREL_PG_HI21: 442 case ELF::R_AARCH64_ADR_PREL_PG_HI21_NC: { 443 // Bits 32:12 of Symbol address goes in bits 30:29 + 23:5 of ADRP 444 // and ADR instructions 445 bool IsAdr = !!(((Contents >> 31) & 0x1) == 0); 446 Contents &= ~0xffffffff9f00001fUll; 447 uint64_t LowBits = (Contents >> 29) & 0x3; 448 uint64_t HighBits = (Contents >> 5) & 0x7ffff; 449 Contents = LowBits | (HighBits << 2); 450 if (IsAdr) 451 return static_cast<int64_t>(PC) + SignExtend64<21>(Contents); 452 453 // ADRP instruction 454 Contents = static_cast<int64_t>(PC) + SignExtend64<33>(Contents << 12); 455 Contents &= ~0xfffUll; 456 return Contents; 457 } 458 case ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: 459 case ELF::R_AARCH64_TLSDESC_LD64_LO12: 460 case ELF::R_AARCH64_LD64_GOT_LO12_NC: 461 case ELF::R_AARCH64_LDST64_ABS_LO12_NC: { 462 // Immediate goes in bits 21:10 of LD/ST instruction, taken 463 // from bits 11:3 of Symbol address 464 Contents &= ~0xffffffffffc003ffU; 465 return Contents >> (10 - 3); 466 } 467 case ELF::R_AARCH64_TLSLE_ADD_TPREL_HI12: 468 case ELF::R_AARCH64_TLSLE_ADD_TPREL_LO12_NC: 469 case ELF::R_AARCH64_TLSDESC_ADD_LO12: 470 case ELF::R_AARCH64_ADD_ABS_LO12_NC: { 471 // Immediate goes in bits 21:10 of ADD instruction 472 Contents &= ~0xffffffffffc003ffU; 473 return Contents >> (10 - 0); 474 } 475 case ELF::R_AARCH64_LDST128_ABS_LO12_NC: { 476 // Immediate goes in bits 21:10 of ADD instruction, taken 477 // from bits 11:4 of Symbol address 478 Contents &= ~0xffffffffffc003ffU; 479 return Contents >> (10 - 4); 480 } 481 case ELF::R_AARCH64_LDST32_ABS_LO12_NC: { 482 // Immediate goes in bits 21:10 of ADD instruction, taken 483 // from bits 11:2 of Symbol address 484 Contents &= ~0xffffffffffc003ffU; 485 return Contents >> (10 - 2); 486 } 487 case ELF::R_AARCH64_LDST16_ABS_LO12_NC: { 488 // Immediate goes in bits 21:10 of ADD instruction, taken 489 // from bits 11:1 of Symbol address 490 Contents &= ~0xffffffffffc003ffU; 491 return Contents >> (10 - 1); 492 } 493 case ELF::R_AARCH64_LDST8_ABS_LO12_NC: { 494 // Immediate goes in bits 21:10 of ADD instruction, taken 495 // from bits 11:0 of Symbol address 496 Contents &= ~0xffffffffffc003ffU; 497 return Contents >> (10 - 0); 498 } 499 case ELF::R_AARCH64_MOVW_UABS_G3: 500 case ELF::R_AARCH64_MOVW_UABS_G2_NC: 501 case ELF::R_AARCH64_MOVW_UABS_G2: 502 case ELF::R_AARCH64_MOVW_UABS_G1_NC: 503 case ELF::R_AARCH64_MOVW_UABS_G1: 504 case ELF::R_AARCH64_MOVW_UABS_G0_NC: 505 case ELF::R_AARCH64_MOVW_UABS_G0: 506 // The shift goes in bits 22:21 of MOV* instructions 507 uint8_t Shift = (Contents >> 21) & 0x3; 508 // Immediate goes in bits 20:5 509 Contents = (Contents >> 5) & 0xffff; 510 return Contents << (16 * Shift); 511 } 512 } 513 514 static uint64_t extractUImmRISCV(uint32_t Contents) { 515 return SignExtend64<32>(Contents & 0xfffff000); 516 } 517 518 static uint64_t extractIImmRISCV(uint32_t Contents) { 519 return SignExtend64<12>(Contents >> 20); 520 } 521 522 static uint64_t extractSImmRISCV(uint32_t Contents) { 523 return SignExtend64<12>(((Contents >> 7) & 0x1f) | ((Contents >> 25) << 5)); 524 } 525 526 static uint64_t extractJImmRISCV(uint32_t Contents) { 527 return SignExtend64<21>( 528 (((Contents >> 21) & 0x3ff) << 1) | (((Contents >> 20) & 0x1) << 11) | 529 (((Contents >> 12) & 0xff) << 12) | (((Contents >> 31) & 0x1) << 20)); 530 } 531 532 static uint64_t extractBImmRISCV(uint32_t Contents) { 533 return SignExtend64<13>( 534 (((Contents >> 8) & 0xf) << 1) | (((Contents >> 25) & 0x3f) << 5) | 535 (((Contents >> 7) & 0x1) << 11) | (((Contents >> 31) & 0x1) << 12)); 536 } 537 538 static uint64_t extractValueRISCV(uint64_t Type, uint64_t Contents, 539 uint64_t PC) { 540 switch (Type) { 541 default: 542 errs() << object::getELFRelocationTypeName(ELF::EM_RISCV, Type) << '\n'; 543 llvm_unreachable("unsupported relocation type"); 544 case ELF::R_RISCV_JAL: 545 return extractJImmRISCV(Contents); 546 case ELF::R_RISCV_CALL: 547 case ELF::R_RISCV_CALL_PLT: 548 return extractUImmRISCV(Contents); 549 case ELF::R_RISCV_BRANCH: 550 return extractBImmRISCV(Contents); 551 case ELF::R_RISCV_GOT_HI20: 552 case ELF::R_RISCV_TLS_GOT_HI20: 553 // We need to know the exact address of the GOT entry so we extract the 554 // value from both the AUIPC and L[D|W]. We cannot rely on the symbol in the 555 // relocation for this since it simply refers to the object that is stored 556 // in the GOT entry, not to the entry itself. 557 return extractUImmRISCV(Contents & 0xffffffff) + 558 extractIImmRISCV(Contents >> 32); 559 case ELF::R_RISCV_PCREL_HI20: 560 case ELF::R_RISCV_HI20: 561 return extractUImmRISCV(Contents); 562 case ELF::R_RISCV_PCREL_LO12_I: 563 case ELF::R_RISCV_LO12_I: 564 return extractIImmRISCV(Contents); 565 case ELF::R_RISCV_PCREL_LO12_S: 566 case ELF::R_RISCV_LO12_S: 567 return extractSImmRISCV(Contents); 568 case ELF::R_RISCV_RVC_JUMP: 569 return SignExtend64<11>(Contents >> 2); 570 case ELF::R_RISCV_RVC_BRANCH: 571 return SignExtend64<8>(((Contents >> 2) & 0x1f) | ((Contents >> 5) & 0xe0)); 572 case ELF::R_RISCV_ADD32: 573 case ELF::R_RISCV_SUB32: 574 case ELF::R_RISCV_64: 575 return Contents; 576 } 577 } 578 579 static bool isGOTX86(uint64_t Type) { 580 switch (Type) { 581 default: 582 return false; 583 case ELF::R_X86_64_GOT32: 584 case ELF::R_X86_64_GOTPCREL: 585 case ELF::R_X86_64_GOTTPOFF: 586 case ELF::R_X86_64_GOTOFF64: 587 case ELF::R_X86_64_GOTPC32: 588 case ELF::R_X86_64_GOT64: 589 case ELF::R_X86_64_GOTPCREL64: 590 case ELF::R_X86_64_GOTPC64: 591 case ELF::R_X86_64_GOTPLT64: 592 case ELF::R_X86_64_GOTPC32_TLSDESC: 593 case ELF::R_X86_64_GOTPCRELX: 594 case ELF::R_X86_64_REX_GOTPCRELX: 595 return true; 596 } 597 } 598 599 static bool isGOTAArch64(uint64_t Type) { 600 switch (Type) { 601 default: 602 return false; 603 case ELF::R_AARCH64_ADR_GOT_PAGE: 604 case ELF::R_AARCH64_LD64_GOT_LO12_NC: 605 case ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: 606 case ELF::R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: 607 case ELF::R_AARCH64_TLSDESC_ADR_PREL21: 608 case ELF::R_AARCH64_TLSDESC_ADR_PAGE21: 609 case ELF::R_AARCH64_TLSDESC_LD64_LO12: 610 case ELF::R_AARCH64_TLSDESC_ADD_LO12: 611 case ELF::R_AARCH64_TLSDESC_CALL: 612 return true; 613 } 614 } 615 616 static bool isGOTRISCV(uint64_t Type) { 617 switch (Type) { 618 default: 619 return false; 620 case ELF::R_RISCV_GOT_HI20: 621 case ELF::R_RISCV_TLS_GOT_HI20: 622 return true; 623 } 624 } 625 626 static bool isTLSX86(uint64_t Type) { 627 switch (Type) { 628 default: 629 return false; 630 case ELF::R_X86_64_TPOFF32: 631 case ELF::R_X86_64_TPOFF64: 632 case ELF::R_X86_64_GOTTPOFF: 633 return true; 634 } 635 } 636 637 static bool isTLSAArch64(uint64_t Type) { 638 switch (Type) { 639 default: 640 return false; 641 case ELF::R_AARCH64_TLSDESC_ADR_PREL21: 642 case ELF::R_AARCH64_TLSDESC_ADR_PAGE21: 643 case ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: 644 case ELF::R_AARCH64_TLSLE_ADD_TPREL_HI12: 645 case ELF::R_AARCH64_TLSLE_ADD_TPREL_LO12_NC: 646 case ELF::R_AARCH64_TLSDESC_LD64_LO12: 647 case ELF::R_AARCH64_TLSDESC_ADD_LO12: 648 case ELF::R_AARCH64_TLSDESC_CALL: 649 case ELF::R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: 650 return true; 651 } 652 } 653 654 static bool isTLSRISCV(uint64_t Type) { 655 switch (Type) { 656 default: 657 return false; 658 case ELF::R_RISCV_TLS_GOT_HI20: 659 case ELF::R_RISCV_TPREL_HI20: 660 case ELF::R_RISCV_TPREL_ADD: 661 case ELF::R_RISCV_TPREL_LO12_I: 662 case ELF::R_RISCV_TPREL_LO12_S: 663 case ELFReserved::R_RISCV_TPREL_I: 664 case ELFReserved::R_RISCV_TPREL_S: 665 return true; 666 } 667 } 668 669 static bool isPCRelativeX86(uint64_t Type) { 670 switch (Type) { 671 default: 672 llvm_unreachable("Unknown relocation type"); 673 case ELF::R_X86_64_64: 674 case ELF::R_X86_64_32: 675 case ELF::R_X86_64_32S: 676 case ELF::R_X86_64_16: 677 case ELF::R_X86_64_8: 678 case ELF::R_X86_64_TPOFF32: 679 return false; 680 case ELF::R_X86_64_PC8: 681 case ELF::R_X86_64_PC32: 682 case ELF::R_X86_64_PC64: 683 case ELF::R_X86_64_GOTPCREL: 684 case ELF::R_X86_64_PLT32: 685 case ELF::R_X86_64_GOTOFF64: 686 case ELF::R_X86_64_GOTPC32: 687 case ELF::R_X86_64_GOTPC64: 688 case ELF::R_X86_64_GOTTPOFF: 689 case ELF::R_X86_64_GOTPCRELX: 690 case ELF::R_X86_64_REX_GOTPCRELX: 691 return true; 692 } 693 } 694 695 static bool isPCRelativeAArch64(uint64_t Type) { 696 switch (Type) { 697 default: 698 llvm_unreachable("Unknown relocation type"); 699 case ELF::R_AARCH64_ABS16: 700 case ELF::R_AARCH64_ABS32: 701 case ELF::R_AARCH64_ABS64: 702 case ELF::R_AARCH64_LDST64_ABS_LO12_NC: 703 case ELF::R_AARCH64_ADD_ABS_LO12_NC: 704 case ELF::R_AARCH64_LDST128_ABS_LO12_NC: 705 case ELF::R_AARCH64_LDST32_ABS_LO12_NC: 706 case ELF::R_AARCH64_LDST16_ABS_LO12_NC: 707 case ELF::R_AARCH64_LDST8_ABS_LO12_NC: 708 case ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: 709 case ELF::R_AARCH64_TLSLE_ADD_TPREL_HI12: 710 case ELF::R_AARCH64_TLSLE_ADD_TPREL_LO12_NC: 711 case ELF::R_AARCH64_LD64_GOT_LO12_NC: 712 case ELF::R_AARCH64_TLSDESC_LD64_LO12: 713 case ELF::R_AARCH64_TLSDESC_ADD_LO12: 714 case ELF::R_AARCH64_MOVW_UABS_G0: 715 case ELF::R_AARCH64_MOVW_UABS_G0_NC: 716 case ELF::R_AARCH64_MOVW_UABS_G1: 717 case ELF::R_AARCH64_MOVW_UABS_G1_NC: 718 case ELF::R_AARCH64_MOVW_UABS_G2: 719 case ELF::R_AARCH64_MOVW_UABS_G2_NC: 720 case ELF::R_AARCH64_MOVW_UABS_G3: 721 return false; 722 case ELF::R_AARCH64_TLSDESC_CALL: 723 case ELF::R_AARCH64_CALL26: 724 case ELF::R_AARCH64_JUMP26: 725 case ELF::R_AARCH64_TSTBR14: 726 case ELF::R_AARCH64_CONDBR19: 727 case ELF::R_AARCH64_ADR_PREL_LO21: 728 case ELF::R_AARCH64_ADR_PREL_PG_HI21: 729 case ELF::R_AARCH64_ADR_PREL_PG_HI21_NC: 730 case ELF::R_AARCH64_ADR_GOT_PAGE: 731 case ELF::R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: 732 case ELF::R_AARCH64_TLSDESC_ADR_PREL21: 733 case ELF::R_AARCH64_TLSDESC_ADR_PAGE21: 734 case ELF::R_AARCH64_PREL16: 735 case ELF::R_AARCH64_PREL32: 736 case ELF::R_AARCH64_PREL64: 737 return true; 738 } 739 } 740 741 static bool isPCRelativeRISCV(uint64_t Type) { 742 switch (Type) { 743 default: 744 llvm_unreachable("Unknown relocation type"); 745 case ELF::R_RISCV_ADD32: 746 case ELF::R_RISCV_SUB32: 747 case ELF::R_RISCV_HI20: 748 case ELF::R_RISCV_LO12_I: 749 case ELF::R_RISCV_LO12_S: 750 case ELF::R_RISCV_64: 751 return false; 752 case ELF::R_RISCV_JAL: 753 case ELF::R_RISCV_CALL: 754 case ELF::R_RISCV_CALL_PLT: 755 case ELF::R_RISCV_BRANCH: 756 case ELF::R_RISCV_GOT_HI20: 757 case ELF::R_RISCV_PCREL_HI20: 758 case ELF::R_RISCV_PCREL_LO12_I: 759 case ELF::R_RISCV_PCREL_LO12_S: 760 case ELF::R_RISCV_RVC_JUMP: 761 case ELF::R_RISCV_RVC_BRANCH: 762 case ELF::R_RISCV_32_PCREL: 763 case ELF::R_RISCV_TLS_GOT_HI20: 764 return true; 765 } 766 } 767 768 bool Relocation::isSupported(uint64_t Type) { 769 if (Arch == Triple::aarch64) 770 return isSupportedAArch64(Type); 771 if (Arch == Triple::riscv64) 772 return isSupportedRISCV(Type); 773 return isSupportedX86(Type); 774 } 775 776 size_t Relocation::getSizeForType(uint64_t Type) { 777 if (Arch == Triple::aarch64) 778 return getSizeForTypeAArch64(Type); 779 if (Arch == Triple::riscv64) 780 return getSizeForTypeRISCV(Type); 781 return getSizeForTypeX86(Type); 782 } 783 784 bool Relocation::skipRelocationType(uint64_t Type) { 785 if (Arch == Triple::aarch64) 786 return skipRelocationTypeAArch64(Type); 787 if (Arch == Triple::riscv64) 788 return skipRelocationTypeRISCV(Type); 789 return skipRelocationTypeX86(Type); 790 } 791 792 bool Relocation::skipRelocationProcess(uint64_t &Type, uint64_t Contents) { 793 if (Arch == Triple::aarch64) 794 return skipRelocationProcessAArch64(Type, Contents); 795 if (Arch == Triple::riscv64) 796 skipRelocationProcessRISCV(Type, Contents); 797 return skipRelocationProcessX86(Type, Contents); 798 } 799 800 uint64_t Relocation::encodeValue(uint64_t Type, uint64_t Value, uint64_t PC) { 801 if (Arch == Triple::aarch64) 802 return encodeValueAArch64(Type, Value, PC); 803 if (Arch == Triple::riscv64) 804 return encodeValueRISCV(Type, Value, PC); 805 return encodeValueX86(Type, Value, PC); 806 } 807 808 uint64_t Relocation::extractValue(uint64_t Type, uint64_t Contents, 809 uint64_t PC) { 810 if (Arch == Triple::aarch64) 811 return extractValueAArch64(Type, Contents, PC); 812 if (Arch == Triple::riscv64) 813 return extractValueRISCV(Type, Contents, PC); 814 return extractValueX86(Type, Contents, PC); 815 } 816 817 bool Relocation::isGOT(uint64_t Type) { 818 if (Arch == Triple::aarch64) 819 return isGOTAArch64(Type); 820 if (Arch == Triple::riscv64) 821 return isGOTRISCV(Type); 822 return isGOTX86(Type); 823 } 824 825 bool Relocation::isX86GOTPCRELX(uint64_t Type) { 826 if (Arch != Triple::x86_64) 827 return false; 828 return Type == ELF::R_X86_64_GOTPCRELX || Type == ELF::R_X86_64_REX_GOTPCRELX; 829 } 830 831 bool Relocation::isX86GOTPC64(uint64_t Type) { 832 if (Arch != Triple::x86_64) 833 return false; 834 return Type == ELF::R_X86_64_GOTPC64; 835 } 836 837 bool Relocation::isNone(uint64_t Type) { return Type == getNone(); } 838 839 bool Relocation::isRelative(uint64_t Type) { 840 if (Arch == Triple::aarch64) 841 return Type == ELF::R_AARCH64_RELATIVE; 842 if (Arch == Triple::riscv64) 843 return Type == ELF::R_RISCV_RELATIVE; 844 return Type == ELF::R_X86_64_RELATIVE; 845 } 846 847 bool Relocation::isIRelative(uint64_t Type) { 848 if (Arch == Triple::aarch64) 849 return Type == ELF::R_AARCH64_IRELATIVE; 850 if (Arch == Triple::riscv64) 851 llvm_unreachable("not implemented"); 852 return Type == ELF::R_X86_64_IRELATIVE; 853 } 854 855 bool Relocation::isTLS(uint64_t Type) { 856 if (Arch == Triple::aarch64) 857 return isTLSAArch64(Type); 858 if (Arch == Triple::riscv64) 859 return isTLSRISCV(Type); 860 return isTLSX86(Type); 861 } 862 863 bool Relocation::isInstructionReference(uint64_t Type) { 864 if (Arch != Triple::riscv64) 865 return false; 866 867 switch (Type) { 868 default: 869 return false; 870 case ELF::R_RISCV_PCREL_LO12_I: 871 case ELF::R_RISCV_PCREL_LO12_S: 872 return true; 873 } 874 } 875 876 uint64_t Relocation::getNone() { 877 if (Arch == Triple::aarch64) 878 return ELF::R_AARCH64_NONE; 879 if (Arch == Triple::riscv64) 880 return ELF::R_RISCV_NONE; 881 return ELF::R_X86_64_NONE; 882 } 883 884 uint64_t Relocation::getPC32() { 885 if (Arch == Triple::aarch64) 886 return ELF::R_AARCH64_PREL32; 887 if (Arch == Triple::riscv64) 888 return ELF::R_RISCV_32_PCREL; 889 return ELF::R_X86_64_PC32; 890 } 891 892 uint64_t Relocation::getPC64() { 893 if (Arch == Triple::aarch64) 894 return ELF::R_AARCH64_PREL64; 895 if (Arch == Triple::riscv64) 896 llvm_unreachable("not implemented"); 897 return ELF::R_X86_64_PC64; 898 } 899 900 bool Relocation::isPCRelative(uint64_t Type) { 901 if (Arch == Triple::aarch64) 902 return isPCRelativeAArch64(Type); 903 if (Arch == Triple::riscv64) 904 return isPCRelativeRISCV(Type); 905 return isPCRelativeX86(Type); 906 } 907 908 uint64_t Relocation::getAbs64() { 909 if (Arch == Triple::aarch64) 910 return ELF::R_AARCH64_ABS64; 911 if (Arch == Triple::riscv64) 912 return ELF::R_RISCV_64; 913 return ELF::R_X86_64_64; 914 } 915 916 uint64_t Relocation::getRelative() { 917 if (Arch == Triple::aarch64) 918 return ELF::R_AARCH64_RELATIVE; 919 return ELF::R_X86_64_RELATIVE; 920 } 921 922 size_t Relocation::emit(MCStreamer *Streamer) const { 923 const size_t Size = getSizeForType(Type); 924 const auto *Value = createExpr(Streamer); 925 Streamer->emitValue(Value, Size); 926 return Size; 927 } 928 929 const MCExpr *Relocation::createExpr(MCStreamer *Streamer) const { 930 MCContext &Ctx = Streamer->getContext(); 931 const MCExpr *Value = nullptr; 932 933 if (Symbol && Addend) { 934 Value = MCBinaryExpr::createAdd(MCSymbolRefExpr::create(Symbol, Ctx), 935 MCConstantExpr::create(Addend, Ctx), Ctx); 936 } else if (Symbol) { 937 Value = MCSymbolRefExpr::create(Symbol, Ctx); 938 } else { 939 Value = MCConstantExpr::create(Addend, Ctx); 940 } 941 942 if (isPCRelative(Type)) { 943 MCSymbol *TempLabel = Ctx.createNamedTempSymbol(); 944 Streamer->emitLabel(TempLabel); 945 Value = MCBinaryExpr::createSub( 946 Value, MCSymbolRefExpr::create(TempLabel, Ctx), Ctx); 947 } 948 949 return Value; 950 } 951 952 const MCExpr *Relocation::createExpr(MCStreamer *Streamer, 953 const MCExpr *RetainedValue) const { 954 const auto *Value = createExpr(Streamer); 955 956 if (RetainedValue) { 957 Value = MCBinaryExpr::create(getComposeOpcodeFor(Type), RetainedValue, 958 Value, Streamer->getContext()); 959 } 960 961 return Value; 962 } 963 964 MCBinaryExpr::Opcode Relocation::getComposeOpcodeFor(uint64_t Type) { 965 assert(Arch == Triple::riscv64 && "only implemented for RISC-V"); 966 967 switch (Type) { 968 default: 969 llvm_unreachable("not implemented"); 970 case ELF::R_RISCV_ADD32: 971 return MCBinaryExpr::Add; 972 case ELF::R_RISCV_SUB32: 973 return MCBinaryExpr::Sub; 974 } 975 } 976 977 #define ELF_RELOC(name, value) #name, 978 979 void Relocation::print(raw_ostream &OS) const { 980 static const char *X86RelocNames[] = { 981 #include "llvm/BinaryFormat/ELFRelocs/x86_64.def" 982 }; 983 static const char *AArch64RelocNames[] = { 984 #include "llvm/BinaryFormat/ELFRelocs/AArch64.def" 985 }; 986 if (Arch == Triple::aarch64) 987 OS << AArch64RelocNames[Type]; 988 else if (Arch == Triple::riscv64) { 989 // RISC-V relocations are not sequentially numbered so we cannot use an 990 // array 991 switch (Type) { 992 default: 993 llvm_unreachable("illegal RISC-V relocation"); 994 #undef ELF_RELOC 995 #define ELF_RELOC(name, value) \ 996 case value: \ 997 OS << #name; \ 998 break; 999 #include "llvm/BinaryFormat/ELFRelocs/RISCV.def" 1000 } 1001 } else 1002 OS << X86RelocNames[Type]; 1003 OS << ", 0x" << Twine::utohexstr(Offset); 1004 if (Symbol) { 1005 OS << ", " << Symbol->getName(); 1006 } 1007 if (int64_t(Addend) < 0) 1008 OS << ", -0x" << Twine::utohexstr(-int64_t(Addend)); 1009 else 1010 OS << ", 0x" << Twine::utohexstr(Addend); 1011 OS << ", 0x" << Twine::utohexstr(Value); 1012 } 1013