1e3f7d4fbSUlrich Weigand /********************************************************************** 2e3f7d4fbSUlrich Weigand Copyright(c) 2011-2016 Intel Corporation All rights reserved. 3e3f7d4fbSUlrich Weigand 4e3f7d4fbSUlrich Weigand Redistribution and use in source and binary forms, with or without 5e3f7d4fbSUlrich Weigand modification, are permitted provided that the following conditions 6e3f7d4fbSUlrich Weigand are met: 7e3f7d4fbSUlrich Weigand * Redistributions of source code must retain the above copyright 8e3f7d4fbSUlrich Weigand notice, this list of conditions and the following disclaimer. 9e3f7d4fbSUlrich Weigand * Redistributions in binary form must reproduce the above copyright 10e3f7d4fbSUlrich Weigand notice, this list of conditions and the following disclaimer in 11e3f7d4fbSUlrich Weigand the documentation and/or other materials provided with the 12e3f7d4fbSUlrich Weigand distribution. 13e3f7d4fbSUlrich Weigand * Neither the name of Intel Corporation nor the names of its 14e3f7d4fbSUlrich Weigand contributors may be used to endorse or promote products derived 15e3f7d4fbSUlrich Weigand from this software without specific prior written permission. 16e3f7d4fbSUlrich Weigand 17e3f7d4fbSUlrich Weigand THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18e3f7d4fbSUlrich Weigand "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19e3f7d4fbSUlrich Weigand LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20e3f7d4fbSUlrich Weigand A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21e3f7d4fbSUlrich Weigand OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22e3f7d4fbSUlrich Weigand SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23e3f7d4fbSUlrich Weigand LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24e3f7d4fbSUlrich Weigand DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25e3f7d4fbSUlrich Weigand THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26e3f7d4fbSUlrich Weigand (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27e3f7d4fbSUlrich Weigand OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28e3f7d4fbSUlrich Weigand **********************************************************************/ 29e3f7d4fbSUlrich Weigand 30e3f7d4fbSUlrich Weigand #ifndef _ENDIAN_HELPER_H_ 31e3f7d4fbSUlrich Weigand #define _ENDIAN_HELPER_H_ 32e3f7d4fbSUlrich Weigand 33e3f7d4fbSUlrich Weigand /** 34e3f7d4fbSUlrich Weigand * @file endian_helper.h 35e3f7d4fbSUlrich Weigand * @brief Byte order helper routines 36e3f7d4fbSUlrich Weigand * 37e3f7d4fbSUlrich Weigand */ 38e3f7d4fbSUlrich Weigand 39e3f7d4fbSUlrich Weigand #ifdef __cplusplus 40e3f7d4fbSUlrich Weigand extern "C" { 41e3f7d4fbSUlrich Weigand #endif 42e3f7d4fbSUlrich Weigand 43e3f7d4fbSUlrich Weigand #if defined(__ICC) 44e3f7d4fbSUlrich Weigand #define byteswap32(x) _bswap(x) 45e3f7d4fbSUlrich Weigand #define byteswap64(x) _bswap64(x) 46e3f7d4fbSUlrich Weigand #elif defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 3)) 47e3f7d4fbSUlrich Weigand #define byteswap32(x) __builtin_bswap32(x) 48e3f7d4fbSUlrich Weigand #define byteswap64(x) __builtin_bswap64(x) 49e3f7d4fbSUlrich Weigand #else 50*1de5344dSMarcel Cornu #define byteswap32(x) (((x) << 24) | (((x) & 0xff00) << 8) | (((x) & 0xff0000) >> 8) | ((x) >> 24)) 51*1de5344dSMarcel Cornu #define byteswap64(x) \ 52*1de5344dSMarcel Cornu ((((x) & (0xffull << 0)) << 56) | (((x) & (0xffull << 8)) << 40) | \ 53*1de5344dSMarcel Cornu (((x) & (0xffull << 16)) << 24) | (((x) & (0xffull << 24)) << 8) | \ 54*1de5344dSMarcel Cornu (((x) & (0xffull << 32)) >> 8) | (((x) & (0xffull << 40)) >> 24) | \ 55*1de5344dSMarcel Cornu (((x) & (0xffull << 48)) >> 40) | (((x) & (0xffull << 56)) >> 56)) 56e3f7d4fbSUlrich Weigand #endif 57e3f7d4fbSUlrich Weigand 58e3f7d4fbSUlrich Weigand // This check works when using GCC (or LLVM). Assume little-endian 59e3f7d4fbSUlrich Weigand // if any other compiler is being used. 60*1de5344dSMarcel Cornu #if defined(__BYTE_ORDER__) && defined(__ORDER_BIG_ENDIAN__) && \ 61*1de5344dSMarcel Cornu __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ 62e3f7d4fbSUlrich Weigand #define to_le32(x) byteswap32(x) 63e3f7d4fbSUlrich Weigand #define to_le64(x) byteswap64(x) 64e3f7d4fbSUlrich Weigand #define to_be32(x) (x) 65e3f7d4fbSUlrich Weigand #define to_be64(x) (x) 66e3f7d4fbSUlrich Weigand #else 67e3f7d4fbSUlrich Weigand #define to_le32(x) (x) 68e3f7d4fbSUlrich Weigand #define to_le64(x) (x) 69e3f7d4fbSUlrich Weigand #define to_be32(x) byteswap32(x) 70e3f7d4fbSUlrich Weigand #define to_be64(x) byteswap64(x) 71e3f7d4fbSUlrich Weigand #endif 72e3f7d4fbSUlrich Weigand 73e3f7d4fbSUlrich Weigand #ifdef __cplusplus 74e3f7d4fbSUlrich Weigand } 75e3f7d4fbSUlrich Weigand #endif 76e3f7d4fbSUlrich Weigand 77e3f7d4fbSUlrich Weigand #endif // _ISA_HELPER_H_ 78