1*b1c45175SGreg Tucker;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 2*b1c45175SGreg Tucker; Copyright(c) 2011-2018 Intel Corporation All rights reserved. 3*b1c45175SGreg Tucker; 4*b1c45175SGreg Tucker; Redistribution and use in source and binary forms, with or without 5*b1c45175SGreg Tucker; modification, are permitted provided that the following conditions 6*b1c45175SGreg Tucker; are met: 7*b1c45175SGreg Tucker; * Redistributions of source code must retain the above copyright 8*b1c45175SGreg Tucker; notice, this list of conditions and the following disclaimer. 9*b1c45175SGreg Tucker; * Redistributions in binary form must reproduce the above copyright 10*b1c45175SGreg Tucker; notice, this list of conditions and the following disclaimer in 11*b1c45175SGreg Tucker; the documentation and/or other materials provided with the 12*b1c45175SGreg Tucker; distribution. 13*b1c45175SGreg Tucker; * Neither the name of Intel Corporation nor the names of its 14*b1c45175SGreg Tucker; contributors may be used to endorse or promote products derived 15*b1c45175SGreg Tucker; from this software without specific prior written permission. 16*b1c45175SGreg Tucker; 17*b1c45175SGreg Tucker; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18*b1c45175SGreg Tucker; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19*b1c45175SGreg Tucker; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20*b1c45175SGreg Tucker; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21*b1c45175SGreg Tucker; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22*b1c45175SGreg Tucker; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23*b1c45175SGreg Tucker; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24*b1c45175SGreg Tucker; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25*b1c45175SGreg Tucker; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26*b1c45175SGreg Tucker; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27*b1c45175SGreg Tucker; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28*b1c45175SGreg Tucker;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 29*b1c45175SGreg Tucker 3001dfbcc4SRoy Oursler; heapify heap, heap_size, i, child, tmp1, tmp2, tmpd 3101dfbcc4SRoy Oursler%macro heapify2 7 3201dfbcc4SRoy Oursler%define %%heap %1 ; qword ptr 3301dfbcc4SRoy Oursler%define %%heap_size %2 ; dword 3401dfbcc4SRoy Oursler%define %%i %3 ; dword 3501dfbcc4SRoy Oursler%define %%child %4 ; dword 3601dfbcc4SRoy Oursler%define %%tmp1 %5 ; qword 3701dfbcc4SRoy Oursler%define %%tmp2 %6 ; qword 3801dfbcc4SRoy Oursler%define %%tmpd %7 ; dword 3901dfbcc4SRoy Oursler align 16 4001dfbcc4SRoy Oursler%%heapify1: 4101dfbcc4SRoy Oursler lea %%child, [%%i + %%i] 4201dfbcc4SRoy Oursler cmp %%child, %%heap_size 4301dfbcc4SRoy Oursler ja %%end_heapify1 4401dfbcc4SRoy Oursler mov %%tmp1, [%%heap + %%child] 4501dfbcc4SRoy Oursler mov %%tmpd, %%child 4601dfbcc4SRoy Oursler mov %%tmp2, [%%heap + %%child) + 8] 4701dfbcc4SRoy Oursler lea %%child, [%%child + 1] 4801dfbcc4SRoy Oursler cmove %%tmp2, %%tmp1 4901dfbcc4SRoy Oursler cmp %%tmp1, %%tmp2 5001dfbcc4SRoy Oursler cmovbe %%child, %%tmpd 5101dfbcc4SRoy Oursler cmovbe %%tmp2, %%tmp1 5201dfbcc4SRoy Oursler ; child is correct, %%tmp2 = heap[child] 5301dfbcc4SRoy Oursler mov %%tmp1, [%%heap + %%i] 5401dfbcc4SRoy Oursler cmp %%tmp1, %%tmp2 5501dfbcc4SRoy Oursler jbe %%end_heapify1 5601dfbcc4SRoy Oursler mov [%%heap + %%i], %%tmp2 5701dfbcc4SRoy Oursler mov [%%heap + %%child], %%tmp1 5801dfbcc4SRoy Oursler mov %%i, %%child 5901dfbcc4SRoy Oursler jmp %%heapify1 6001dfbcc4SRoy Oursler%%end_heapify1 6101dfbcc4SRoy Oursler%endm 6201dfbcc4SRoy Oursler 6301dfbcc4SRoy Oursler; heapify heap, heap_size, i, child, tmp1, tmp2, tmpd, tmp3 6401dfbcc4SRoy Oursler%macro heapify 8 6501dfbcc4SRoy Oursler%define %%heap %1 ; qword ptr 6601dfbcc4SRoy Oursler%define %%heap_size %2 ; qword 6701dfbcc4SRoy Oursler%define %%i %3 ; qword 6801dfbcc4SRoy Oursler%define %%child %4 ; qword 6901dfbcc4SRoy Oursler%define %%tmp1 %5 ; qword 7001dfbcc4SRoy Oursler%define %%tmp2 %6 ; qword 7101dfbcc4SRoy Oursler%define %%tmpd %7 ; qword 7201dfbcc4SRoy Oursler%define %%tmp3 %8 7301dfbcc4SRoy Oursler align 16 7401dfbcc4SRoy Oursler%%heapify1: 7501dfbcc4SRoy Oursler lea %%child, [%%i + %%i] 7601dfbcc4SRoy Oursler; mov %%child, %%i 7701dfbcc4SRoy Oursler; add %%child, %%child 7801dfbcc4SRoy Oursler cmp %%child, %%heap_size 7901dfbcc4SRoy Oursler ja %%end_heapify1 8001dfbcc4SRoy Oursler mov %%tmp1, [%%heap + %%child*8] 8101dfbcc4SRoy Oursler mov %%tmp2, [%%heap + %%child*8 + 8] 8201dfbcc4SRoy Oursler mov %%tmp3, [%%heap + %%i*8] 8301dfbcc4SRoy Oursler mov %%tmpd, %%child 8401dfbcc4SRoy Oursler add %%tmpd, 1 8501dfbcc4SRoy Oursler 8601dfbcc4SRoy Oursler cmp %%tmp2, %%tmp1 8701dfbcc4SRoy Oursler cmovb %%child, %%tmpd 8801dfbcc4SRoy Oursler cmovb %%tmp1, %%tmp2 8901dfbcc4SRoy Oursler ; child is correct, tmp1 = heap[child] 9001dfbcc4SRoy Oursler cmp %%tmp3, %%tmp1 9101dfbcc4SRoy Oursler jbe %%end_heapify1 9201dfbcc4SRoy Oursler ; swap i and child 9301dfbcc4SRoy Oursler mov [%%heap + %%i*8], %%tmp1 9401dfbcc4SRoy Oursler mov [%%heap + %%child*8], %%tmp3 9501dfbcc4SRoy Oursler mov %%i, %%child 9601dfbcc4SRoy Oursler jmp %%heapify1 9701dfbcc4SRoy Oursler%%end_heapify1: 9801dfbcc4SRoy Oursler%endm 99