xref: /isa-l/igzip/bitbuf2.asm (revision e1470f70f6d996a4ed995fc6b378e563c795128a)
1;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2;  Copyright(c) 2011-2016 Intel Corporation All rights reserved.
3;
4;  Redistribution and use in source and binary forms, with or without
5;  modification, are permitted provided that the following conditions
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7;    * Redistributions of source code must retain the above copyright
8;      notice, this list of conditions and the following disclaimer.
9;    * Redistributions in binary form must reproduce the above copyright
10;      notice, this list of conditions and the following disclaimer in
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12;      distribution.
13;    * Neither the name of Intel Corporation nor the names of its
14;      contributors may be used to endorse or promote products derived
15;      from this software without specific prior written permission.
16;
17;  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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19;  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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28;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
29
30%include "options.asm"
31
32; Assumes m_out_buf is a register
33; Clobbers RCX
34; code is clobbered
35; write_bits_always	m_bits, m_bit_count, code, count, m_out_buf
36%macro write_bits 5
37%define %%m_bits	%1
38%define %%m_bit_count	%2
39%define %%code		%3
40%define %%count		%4
41%define %%m_out_buf	%5
42
43%ifdef USE_HSWNI
44	shlx	%%code, %%code, %%m_bit_count
45%else
46	mov	rcx, %%m_bit_count
47	shl	%%code, cl
48%endif
49	or	%%m_bits, %%code
50	add	%%m_bit_count, %%count
51
52	mov	[%%m_out_buf], %%m_bits
53	mov	rcx, %%m_bit_count
54	shr	rcx, 3			; rcx = bytes
55	add	%%m_out_buf, rcx
56	shl	rcx, 3			; rcx = bits
57	sub	%%m_bit_count, rcx
58%ifdef USE_HSWNI
59	shrx	%%m_bits, %%m_bits, rcx
60%else
61	shr	%%m_bits, cl
62%endif
63%endm
64
65%macro write_dword 2
66%define %%data %1d
67%define %%addr %2
68	mov	[%%addr], %%data
69	add	%%addr, 4
70%endm
71