1/********************************************************************** 2 Copyright(c) 2019 Arm Corporation All rights reserved. 3 4 Redistribution and use in source and binary forms, with or without 5 modification, are permitted provided that the following conditions 6 are met: 7 * Redistributions of source code must retain the above copyright 8 notice, this list of conditions and the following disclaimer. 9 * Redistributions in binary form must reproduce the above copyright 10 notice, this list of conditions and the following disclaimer in 11 the documentation and/or other materials provided with the 12 distribution. 13 * Neither the name of Arm Corporation nor the names of its 14 contributors may be used to endorse or promote products derived 15 from this software without specific prior written permission. 16 17 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20 A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21 OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23 LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28**********************************************************************/ 29 .arch armv8-a 30 .text 31 .align 2 32 33#include "lz0a_const_aarch64.h" 34#include "data_struct_aarch64.h" 35#include "huffman_aarch64.h" 36#include "bitbuf2_aarch64.h" 37#include "stdmac_aarch64.h" 38 39/* 40declare Macros 41*/ 42 43.macro declare_generic_reg name:req,reg:req,default:req 44 \name .req \default\reg 45 w_\name .req w\reg 46 x_\name .req x\reg 47.endm 48 49 .text 50 .align 2 51 .global set_long_icf_fg_aarch64 52 .type set_long_icf_fg_aarch64, %function 53 54/* 55void set_long_icf_fg_aarch64(uint8_t * next_in, uint64_t processed, uint64_t input_size, 56 struct deflate_icf *match_lookup) 57*/ 58 59 /* arguments */ 60 declare_generic_reg next_in_param, 0,x 61 declare_generic_reg processed_param, 1,x 62 declare_generic_reg input_size_param, 2,x 63 declare_generic_reg match_lookup_param, 3,x 64 65 declare_generic_reg param0, 0,x 66 declare_generic_reg param1, 1,x 67 declare_generic_reg param2, 2,x 68 69 /* local variable */ 70 declare_generic_reg len, 7,w 71 declare_generic_reg dist_code, 8,w 72 declare_generic_reg shortest_match_len 9,w 73 declare_generic_reg len_max, 10,w 74 declare_generic_reg dist_extra, 11,w 75 declare_generic_reg const_8, 13,x 76 declare_generic_reg next_in, 20,x 77 declare_generic_reg dist_start, 21,x 78 declare_generic_reg end_processed, 22,x 79 declare_generic_reg end_in, 23,x 80 declare_generic_reg match_lookup, 19,x 81 82 declare_generic_reg match_length, 4,w 83 declare_generic_reg tmp0, 5,w 84 declare_generic_reg tmp1, 6,w 85 86/* constant */ 87.equ DIST_START_SIZE, 128 88.equ ISAL_LOOK_AHEAD, 288 89.equ LEN_OFFSET, 254 90.equ SHORTEST_MATCH, 4 91.equ LEN_MAX_CONST, 512 92 93set_long_icf_fg_aarch64: 94 stp x29, x30, [sp, -192]! 95 add x29, sp, 0 96 stp x21, x22, [sp, 32] 97 add x21, x29, 64 98 stp x19, x20, [sp, 16] 99 str x23, [sp, 48] 100 101 add end_processed, next_in_param, processed_param 102 mov next_in, next_in_param 103 add end_in, next_in_param, input_size_param 104 mov match_lookup, match_lookup_param 105 106 adrp x1, .data_dist_start 107 mov x2, DIST_START_SIZE // 128 108 add x1, x1, :lo12:.data_dist_start 109 mov x0, dist_start 110 bl memcpy 111 112 add x_tmp0, end_processed, ISAL_LOOK_AHEAD // 288 113 cmp end_in, x_tmp0 114 csel end_in, end_in, x_tmp0, cc 115 cmp next_in, end_processed 116 bcs .done 117 118 mov const_8, 8 119 mov len_max, LEN_MAX_CONST // 512 120 mov shortest_match_len, (LEN_OFFSET + SHORTEST_MATCH - 1) 121 b .while_outer_loop 122 123 .align 2 124.while_outer_check: 125 add next_in, next_in, 1 126 add match_lookup, match_lookup, 4 127 cmp end_processed, next_in 128 bls .done 129 130.while_outer_loop: 131 ldrh len, [match_lookup] 132 and len, len, LIT_LEN_MASK // 1023 133 cmp len, (LEN_OFFSET + 8 - 1) // 261 134 bls .while_outer_check 135 136 ldr dist_code, [match_lookup] 137 add x1, next_in, 8 138 ldrh dist_extra, [match_lookup, 2] 139 sub w2, w_end_in, w1 140 ubfx x_dist_code, x_dist_code, 10, 9 141 ubfx x_dist_extra, x_dist_extra, 3, 13 142 uxtw x0, dist_code 143 ldr w0, [dist_start, x0, lsl 2] 144 add w0, dist_extra, w0 145 sub x0, const_8, x0 146 add x0, next_in, x0 147 148 compare_aarch64 param0,param1,param2,match_length,tmp0,tmp1 149 mov w0, w_match_length 150 151 add w0, w0, (LEN_OFFSET + 8) // 262 152 cmp w0, len 153 bls .while_outer_check 154 155 lsl w2, dist_extra, 19 156 orr w2, w2, dist_code, lsl 10 157 158 .align 3 159.while_inner_loop: 160 cmp w0, LEN_MAX_CONST // 512 161 add next_in, next_in, 1 162 csel w1, w0, len_max, ls 163 sub w0, w0, #1 164 orr w1, w1, w2 165 str w1, [match_lookup] 166 ldrh w1, [match_lookup, 4]! 167 168 and w1, w1, LIT_LEN_MASK // 1023 169 cmp w1, (LEN_OFFSET + SHORTEST_MATCH - 1) // 257 170 csel w1, w1, shortest_match_len, cs 171 cmp w1, w0 172 bcc .while_inner_loop 173 174 add next_in, next_in, 1 175 add match_lookup, match_lookup, 4 176 cmp end_processed, next_in 177 bhi .while_outer_loop 178 179.done: 180 ldp x19, x20, [sp, 16] 181 ldp x21, x22, [sp, 32] 182 ldr x23, [sp, 48] 183 ldp x29, x30, [sp], 192 184 ret 185 .size set_long_icf_fg_aarch64, .-set_long_icf_fg_aarch64 186 187 .section .rodata 188 .align 3 189 .set .data_dist_start,. + 0 190.real_data_dist_start: 191 .word 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0007, 0x0009, 0x000d 192 .word 0x0011, 0x0019, 0x0021, 0x0031, 0x0041, 0x0061, 0x0081, 0x00c1 193 .word 0x0101, 0x0181, 0x0201, 0x0301, 0x0401, 0x0601, 0x0801, 0x0c01 194 .word 0x1001, 0x1801, 0x2001, 0x3001, 0x4001, 0x6001, 0x0000, 0x0000 195