1 /* 2 * PowerPC definition 3 * forsyth@terzarima.net 4 */ 5 #include <lib9.h> 6 #include <bio.h> 7 #include "uregq.h" 8 #include "mach.h" 9 10 11 #define REGOFF(x) (ulong) (&((struct Ureg *) 0)->x) 12 13 #define SP REGOFF(sp) 14 #define PC REGOFF(pc) 15 #define R3 REGOFF(r3) /* return reg */ 16 #define LR REGOFF(lr) 17 #define R31 REGOFF(r31) 18 #define FP_REG(x) (R31+4+8*(x)) 19 20 #define REGSIZE sizeof(struct Ureg) 21 #define FPREGSIZE (8*33) 22 23 Reglist powerreglist[] = { 24 {"CAUSE", REGOFF(cause), RINT|RRDONLY, 'X'}, 25 {"SRR1", REGOFF(status), RINT|RRDONLY, 'X'}, 26 {"PC", REGOFF(pc), RINT, 'X'}, 27 {"LR", REGOFF(lr), RINT, 'X'}, 28 {"CR", REGOFF(cr), RINT, 'X'}, 29 {"XER", REGOFF(xer), RINT, 'X'}, 30 {"CTR", REGOFF(ctr), RINT, 'X'}, 31 {"PC", PC, RINT, 'X'}, 32 {"SP", SP, RINT, 'X'}, 33 {"R0", REGOFF(r0), RINT, 'X'}, 34 /* R1 is SP */ 35 {"R2", REGOFF(r2), RINT, 'X'}, 36 {"R3", REGOFF(r3), RINT, 'X'}, 37 {"R4", REGOFF(r4), RINT, 'X'}, 38 {"R5", REGOFF(r5), RINT, 'X'}, 39 {"R6", REGOFF(r6), RINT, 'X'}, 40 {"R7", REGOFF(r7), RINT, 'X'}, 41 {"R8", REGOFF(r8), RINT, 'X'}, 42 {"R9", REGOFF(r9), RINT, 'X'}, 43 {"R10", REGOFF(r10), RINT, 'X'}, 44 {"R11", REGOFF(r11), RINT, 'X'}, 45 {"R12", REGOFF(r12), RINT, 'X'}, 46 {"R13", REGOFF(r13), RINT, 'X'}, 47 {"R14", REGOFF(r14), RINT, 'X'}, 48 {"R15", REGOFF(r15), RINT, 'X'}, 49 {"R16", REGOFF(r16), RINT, 'X'}, 50 {"R17", REGOFF(r17), RINT, 'X'}, 51 {"R18", REGOFF(r18), RINT, 'X'}, 52 {"R19", REGOFF(r19), RINT, 'X'}, 53 {"R20", REGOFF(r20), RINT, 'X'}, 54 {"R21", REGOFF(r21), RINT, 'X'}, 55 {"R22", REGOFF(r22), RINT, 'X'}, 56 {"R23", REGOFF(r23), RINT, 'X'}, 57 {"R24", REGOFF(r24), RINT, 'X'}, 58 {"R25", REGOFF(r25), RINT, 'X'}, 59 {"R26", REGOFF(r26), RINT, 'X'}, 60 {"R27", REGOFF(r27), RINT, 'X'}, 61 {"R28", REGOFF(r28), RINT, 'X'}, 62 {"R29", REGOFF(r29), RINT, 'X'}, 63 {"R30", REGOFF(r30), RINT, 'X'}, 64 {"R31", REGOFF(r31), RINT, 'X'}, 65 {"F0", FP_REG(0), RFLT, 'D'}, 66 {"F1", FP_REG(1), RFLT, 'D'}, 67 {"F2", FP_REG(2), RFLT, 'D'}, 68 {"F3", FP_REG(3), RFLT, 'D'}, 69 {"F4", FP_REG(4), RFLT, 'D'}, 70 {"F5", FP_REG(5), RFLT, 'D'}, 71 {"F6", FP_REG(6), RFLT, 'D'}, 72 {"F7", FP_REG(7), RFLT, 'D'}, 73 {"F8", FP_REG(8), RFLT, 'D'}, 74 {"F9", FP_REG(9), RFLT, 'D'}, 75 {"F10", FP_REG(10), RFLT, 'D'}, 76 {"F11", FP_REG(11), RFLT, 'D'}, 77 {"F12", FP_REG(12), RFLT, 'D'}, 78 {"F13", FP_REG(13), RFLT, 'D'}, 79 {"F14", FP_REG(14), RFLT, 'D'}, 80 {"F15", FP_REG(15), RFLT, 'D'}, 81 {"F16", FP_REG(16), RFLT, 'D'}, 82 {"F17", FP_REG(17), RFLT, 'D'}, 83 {"F18", FP_REG(18), RFLT, 'D'}, 84 {"F19", FP_REG(19), RFLT, 'D'}, 85 {"F20", FP_REG(20), RFLT, 'D'}, 86 {"F21", FP_REG(21), RFLT, 'D'}, 87 {"F22", FP_REG(22), RFLT, 'D'}, 88 {"F23", FP_REG(23), RFLT, 'D'}, 89 {"F24", FP_REG(24), RFLT, 'D'}, 90 {"F25", FP_REG(25), RFLT, 'D'}, 91 {"F26", FP_REG(26), RFLT, 'D'}, 92 {"F27", FP_REG(27), RFLT, 'D'}, 93 {"F28", FP_REG(28), RFLT, 'D'}, 94 {"F29", FP_REG(29), RFLT, 'D'}, 95 {"F30", FP_REG(30), RFLT, 'D'}, 96 {"F31", FP_REG(31), RFLT, 'D'}, 97 {"FPSCR", FP_REG(32)+4, RFLT, 'X'}, 98 { 0 } 99 }; 100 101 /* the machine description */ 102 Mach mpower = 103 { 104 "power", 105 MPOWER, /* machine type */ 106 powerreglist, /* register set */ 107 REGSIZE, /* register set size in bytes */ 108 FPREGSIZE, /* floating point register size in bytes */ 109 "PC", /* name of PC */ 110 "SP", /* name of SP */ 111 "LR", /* name of link register */ 112 "setSB", /* static base register name */ 113 0, /* value */ 114 0x1000, /* page size */ 115 0x20000000, /* kernel base */ 116 0, /* kernel text mask */ 117 4, /* quantization of pc */ 118 4, /* szaddr */ 119 4, /* szreg */ 120 4, /* szfloat */ 121 8, /* szdouble */ 122 }; 123