1 /* 2 * amd64 definition 3 */ 4 #include <lib9.h> 5 #include <bio.h> 6 #include "ureg6.h" 7 #include "mach.h" 8 9 #define REGOFF(x) offsetof(struct Ureg, x) 10 11 #define REGSIZE sizeof(struct Ureg) 12 #define FP_CTLS(x) (REGSIZE+2*(x)) 13 #define FP_CTL(x) (REGSIZE+4*(x)) 14 #define FP_REG(x) (FP_CTL(8)+16*(x)) 15 #define XM_REG(x) (FP_CTL(8)+8*16+16*(x)) 16 17 #define FPREGSIZE 512 /* TO DO? currently only 0x1A0 used */ 18 19 Reglist amd64reglist[] = { 20 {"AX", REGOFF(ax), RINT, 'Y'}, 21 {"BX", REGOFF(bx), RINT, 'Y'}, 22 {"CX", REGOFF(cx), RINT, 'Y'}, 23 {"DX", REGOFF(dx), RINT, 'Y'}, 24 {"SI", REGOFF(si), RINT, 'Y'}, 25 {"DI", REGOFF(di), RINT, 'Y'}, 26 {"BP", REGOFF(bp), RINT, 'Y'}, 27 {"R8", REGOFF(r8), RINT, 'Y'}, 28 {"R9", REGOFF(r9), RINT, 'Y'}, 29 {"R10", REGOFF(r10), RINT, 'Y'}, 30 {"R11", REGOFF(r11), RINT, 'Y'}, 31 {"R12", REGOFF(r12), RINT, 'Y'}, 32 {"R13", REGOFF(r13), RINT, 'Y'}, 33 {"R14", REGOFF(r14), RINT, 'Y'}, 34 {"R15", REGOFF(r15), RINT, 'Y'}, 35 {"DS", REGOFF(ds), RINT, 'x'}, 36 {"ES", REGOFF(es), RINT, 'x'}, 37 {"FS", REGOFF(fs), RINT, 'x'}, 38 {"GS", REGOFF(gs), RINT, 'x'}, 39 {"TYPE", REGOFF(type), RINT, 'Y'}, 40 {"TRAP", REGOFF(type), RINT, 'Y'}, /* alias for acid */ 41 {"ERROR", REGOFF(error), RINT, 'Y'}, 42 {"IP", REGOFF(ip), RINT, 'Y'}, 43 {"PC", REGOFF(ip), RINT, 'Y'}, /* alias for acid */ 44 {"CS", REGOFF(cs), RINT, 'Y'}, 45 {"FLAGS", REGOFF(flags), RINT, 'Y'}, 46 {"SP", REGOFF(sp), RINT, 'Y'}, 47 {"SS", REGOFF(ss), RINT, 'Y'}, 48 49 {"FCW", FP_CTLS(0), RFLT, 'x'}, 50 {"FSW", FP_CTLS(1), RFLT, 'x'}, 51 {"FTW", FP_CTLS(2), RFLT, 'b'}, 52 {"FOP", FP_CTLS(3), RFLT, 'x'}, 53 {"RIP", FP_CTL(2), RFLT, 'Y'}, 54 {"RDP", FP_CTL(4), RFLT, 'Y'}, 55 {"MXCSR", FP_CTL(6), RFLT, 'X'}, 56 {"MXCSRMASK", FP_CTL(7), RFLT, 'X'}, 57 {"M0", FP_REG(0), RFLT, 'F'}, /* assumes double */ 58 {"M1", FP_REG(1), RFLT, 'F'}, 59 {"M2", FP_REG(2), RFLT, 'F'}, 60 {"M3", FP_REG(3), RFLT, 'F'}, 61 {"M4", FP_REG(4), RFLT, 'F'}, 62 {"M5", FP_REG(5), RFLT, 'F'}, 63 {"M6", FP_REG(6), RFLT, 'F'}, 64 {"M7", FP_REG(7), RFLT, 'F'}, 65 {"X0", XM_REG(0), RFLT, 'F'}, /* assumes double */ 66 {"X1", XM_REG(1), RFLT, 'F'}, 67 {"X2", XM_REG(2), RFLT, 'F'}, 68 {"X3", XM_REG(3), RFLT, 'F'}, 69 {"X4", XM_REG(4), RFLT, 'F'}, 70 {"X5", XM_REG(5), RFLT, 'F'}, 71 {"X6", XM_REG(6), RFLT, 'F'}, 72 {"X7", XM_REG(7), RFLT, 'F'}, 73 {"X8", XM_REG(8), RFLT, 'F'}, 74 {"X9", XM_REG(9), RFLT, 'F'}, 75 {"X10", XM_REG(10), RFLT, 'F'}, 76 {"X11", XM_REG(11), RFLT, 'F'}, 77 {"X12", XM_REG(12), RFLT, 'F'}, 78 {"X13", XM_REG(13), RFLT, 'F'}, 79 {"X14", XM_REG(14), RFLT, 'F'}, 80 {"X15", XM_REG(15), RFLT, 'F'}, 81 {"X16", XM_REG(16), RFLT, 'F'}, 82 /* 83 {"F0", FP_REG(7), RFLT, '3'}, 84 {"F1", FP_REG(6), RFLT, '3'}, 85 {"F2", FP_REG(5), RFLT, '3'}, 86 {"F3", FP_REG(4), RFLT, '3'}, 87 {"F4", FP_REG(3), RFLT, '3'}, 88 {"F5", FP_REG(2), RFLT, '3'}, 89 {"F6", FP_REG(1), RFLT, '3'}, 90 {"F7", FP_REG(0), RFLT, '3'}, 91 */ 92 { 0 } 93 }; 94 95 Mach mamd64= 96 { 97 "amd64", 98 MAMD64, /* machine type */ 99 amd64reglist, /* register list */ 100 REGSIZE, /* size of registers in bytes */ 101 FPREGSIZE, /* size of fp registers in bytes */ 102 "PC", /* name of PC */ 103 "SP", /* name of SP */ 104 0, /* link register */ 105 "setSB", /* static base register name (bogus anyways) */ 106 0, /* static base register value */ 107 0x200000, /* page size */ 108 0xFFFFFFFFF0110000U, /* kernel base */ 109 0xFFFF800000000000U, /* kernel text mask */ 110 0x00007FFFFFFFF000U, /* user stack top */ 111 1, /* quantization of pc */ 112 8, /* szaddr */ 113 4, /* szreg */ 114 4, /* szfloat */ 115 8, /* szdouble */ 116 }; 117