1 /* 2 * x86-amd64 definition 3 */ 4 #include <lib9.h> 5 #include <bio.h> 6 #include "ureg6.h" 7 #include "mach.h" 8 9 #define REGOFF(x) (uvlong)(&((struct Ureg *) 0)->x) 10 11 #define PC REGOFF(pc) 12 #define SP REGOFF(sp) 13 #define AX REGOFF(ax) 14 15 #define REGSIZE sizeof(struct Ureg) 16 #define FP_CTLS(x) (REGSIZE+2*(x)) 17 #define FP_CTL(x) (REGSIZE+4*(x)) 18 #define FP_REG(x) (FP_CTL(8)+16*(x)) 19 #define XM_REG(x) (FP_CTL(8)+8*16+16*(x)) 20 21 #define FPREGSIZE 512 /* TO DO? currently only 0x1A0 used */ 22 23 Reglist amd64reglist[] = { 24 {"R15", REGOFF(r15), RINT, 'Y'}, 25 {"R14", REGOFF(r14), RINT, 'Y'}, 26 {"R13", REGOFF(r13), RINT, 'Y'}, 27 {"R12", REGOFF(r12), RINT, 'Y'}, 28 {"R11", REGOFF(r11), RINT, 'Y'}, 29 {"R10", REGOFF(r10), RINT, 'Y'}, 30 {"R9", REGOFF(r9), RINT, 'Y'}, 31 {"R8", REGOFF(r8), RINT, 'Y'}, 32 {"DI", REGOFF(di), RINT, 'X'}, 33 {"SI", REGOFF(si), RINT, 'Y'}, 34 {"BP", REGOFF(bp), RINT, 'Y'}, 35 {"BX", REGOFF(bx), RINT, 'Y'}, 36 {"DX", REGOFF(dx), RINT, 'Y'}, 37 {"CX", REGOFF(cx), RINT, 'Y'}, 38 {"AX", REGOFF(ax), RINT, 'Y'}, 39 {"GS", REGOFF(gs), RINT, 'Y'}, 40 {"FS", REGOFF(fs), RINT, 'Y'}, 41 {"ES", REGOFF(es), RINT, 'Y'}, 42 {"DS", REGOFF(ds), RINT, 'Y'}, 43 {"TRAP", REGOFF(trap), RINT, 'Y'}, 44 {"ECODE", REGOFF(ecode), RINT, 'Y'}, 45 {"PC", PC, RINT, 'Y'}, 46 {"CS", REGOFF(cs), RINT, 'Y'}, 47 {"EFLAGS", REGOFF(flags), RINT, 'Y'}, 48 {"SP", SP, RINT, 'Y'}, 49 {"SS", REGOFF(ss), RINT, 'Y'}, 50 51 {"FCW", FP_CTLS(0), RFLT, 'x'}, 52 {"FSW", FP_CTLS(1), RFLT, 'x'}, 53 {"FTW", FP_CTLS(2), RFLT, 'x'}, 54 {"FOP", FP_CTLS(3), RFLT, 'x'}, 55 {"FPC", FP_CTL(2), RFLT, 'Y'}, 56 {"RDP", FP_CTL(4), RFLT, 'Y'}, 57 {"MXCSR", FP_CTL(6), RFLT, 'X'}, 58 {"MXCSRMSK", FP_CTL(7), RFLT, 'X'}, 59 {"M0", FP_REG(0), RFLT, 'F'}, /* assumes double */ 60 {"M1", FP_REG(1), RFLT, 'F'}, 61 {"M2", FP_REG(2), RFLT, 'F'}, 62 {"M3", FP_REG(3), RFLT, 'F'}, 63 {"M4", FP_REG(4), RFLT, 'F'}, 64 {"M5", FP_REG(5), RFLT, 'F'}, 65 {"M6", FP_REG(6), RFLT, 'F'}, 66 {"M7", FP_REG(7), RFLT, 'F'}, 67 {"X0", XM_REG(0), RFLT, 'F'}, /* assumes double */ 68 {"X1", XM_REG(1), RFLT, 'F'}, 69 {"X2", XM_REG(2), RFLT, 'F'}, 70 {"X3", XM_REG(3), RFLT, 'F'}, 71 {"X4", XM_REG(4), RFLT, 'F'}, 72 {"X5", XM_REG(5), RFLT, 'F'}, 73 {"X6", XM_REG(6), RFLT, 'F'}, 74 {"X7", XM_REG(7), RFLT, 'F'}, 75 {"X8", XM_REG(8), RFLT, 'F'}, 76 {"X9", XM_REG(9), RFLT, 'F'}, 77 {"X10", XM_REG(10), RFLT, 'F'}, 78 {"X11", XM_REG(11), RFLT, 'F'}, 79 {"X12", XM_REG(12), RFLT, 'F'}, 80 {"X13", XM_REG(13), RFLT, 'F'}, 81 {"X14", XM_REG(14), RFLT, 'F'}, 82 {"X15", XM_REG(15), RFLT, 'F'}, 83 {"X16", XM_REG(16), RFLT, 'F'}, 84 /* 85 {"F0", FP_REG(7), RFLT, '3'}, 86 {"F1", FP_REG(6), RFLT, '3'}, 87 {"F2", FP_REG(5), RFLT, '3'}, 88 {"F3", FP_REG(4), RFLT, '3'}, 89 {"F4", FP_REG(3), RFLT, '3'}, 90 {"F5", FP_REG(2), RFLT, '3'}, 91 {"F6", FP_REG(1), RFLT, '3'}, 92 {"F7", FP_REG(0), RFLT, '3'}, 93 */ 94 { 0 } 95 }; 96 97 Mach mamd64= 98 { 99 "amd64", 100 MI386, /* machine type */ /* TO DO */ 101 amd64reglist, /* register list */ 102 REGSIZE, /* size of registers in bytes */ 103 FPREGSIZE, /* size of fp registers in bytes */ 104 "PC", /* name of PC */ 105 "SP", /* name of SP */ 106 0, /* link register */ 107 "setSB", /* static base register name (bogus anyways) */ 108 0, /* static base register value */ 109 0x1000, /* page size */ 110 0x80100000, /* kernel base */ /* TO DO: uvlong or vlong */ 111 0, /* kernel text mask */ 112 1, /* quantization of pc */ 113 8, /* szaddr */ 114 4, /* szreg */ 115 4, /* szfloat */ 116 8, /* szdouble */ 117 }; 118