1 /* 2 * Memory and machine-specific definitions. Used in C and assembler. 3 */ 4 5 /* 6 * Sizes 7 */ 8 9 #define BI2BY 8 /* bits per byte */ 10 #define BI2WD 32 /* bits per word */ 11 #define BY2WD 4 /* bytes per word */ 12 #define BY2V 8 /* bytes per double word */ 13 #define BY2PG 4096 /* bytes per page */ 14 #define WD2PG (BY2PG/BY2WD) /* words per page */ 15 #define PGSHIFT 12 /* log(BY2PG) */ 16 #define ROUND(s, sz) (((s)+(sz-1))&~(sz-1)) 17 #define PGROUND(s) ROUND(s,BY2PG) 18 19 #define MAXMACH 1 /* max # cpus system can run */ 20 21 /* 22 * Time 23 */ 24 #define HZ 50 /* clock frequency */ 25 #define MS2HZ (1000/HZ) /* millisec per clock tick */ 26 #define TK2SEC(t) ((t)/HZ) /* ticks to seconds */ 27 #define MS2TK(t) ((((ulong)(t))*HZ)/1000) /* milliseconds to ticks */ 28 29 /* 30 * PSR bits 31 */ 32 #define PSREC 0x00002000 33 #define PSREF 0x00001000 34 #define PSRSUPER 0x00000080 35 #define PSRPSUPER 0x00000040 36 #define PSRET 0x00000020 37 #define SPL(n) (n<<8) 38 39 /* 40 * Magic registers 41 */ 42 43 #define MACH 6 /* R6 is m-> */ 44 #define USER 5 /* R5 is u-> */ 45 46 /* 47 * Fundamental addresses 48 */ 49 50 #define USERADDR 0xE0000000 51 #define UREGADDR (USERADDR+BY2PG-((32+6)*BY2WD)) 52 #define BOOTSTACK (KTZERO-0*BY2PG) 53 #define TRAPS (KTZERO-2*BY2PG) 54 55 /* 56 * Reference MMU registers (ASI 4) 57 */ 58 #define PCR 0x000 59 #define CTPR 0x100 60 #define CXR 0x200 61 #define SFSR 0x300 62 #define SFAR 0x400 63 64 /* 65 * Processor Control Register 66 */ 67 #define ITBRDISABLE (1<<16) 68 #define BOOTMODE (1<<14) /* `must be cleared for normal operation' */ 69 #define MEMPCHECK (1<<12) /* check parity */ 70 #define ENABCACHE (3<<8) /* I & D caches */ 71 #define NOFAULT (1<<1) /* no fault */ 72 73 /* 74 * special MMU regions 75 * DMA segment for SBus DMA mapping via I/O MMU (hardware fixes location) 76 * the frame buffer is mapped as one MMU region (16 Mbytes) 77 * IO segments for device register pages etc. 78 */ 79 #define DMARANGE 0 80 #define DMASEGSIZE ((16*MB)<<DMARANGE) 81 #define DMASEGBASE (0 - DMASEGSIZE) 82 #define FBSEGSIZE (1*(16*MB)) /* multiples of 16*MB */ 83 #define FBSEGBASE (DMASEGBASE - DMASEGSIZE) 84 #define IOSEGSIZE (16*MB) 85 #define IOSEGBASE (FBSEGBASE - IOSEGSIZE) 86 87 /* 88 * MMU entries 89 */ 90 #define PTPVALID 1 /* page table pointer */ 91 #define PTEVALID 2 /* page table entry */ 92 #define PTERONLY (2<<2) /* read/execute */ 93 #define PTEWRITE (3<<2) /* read/write/execute */ 94 #define PTEKERNEL (4<<2) /* execute only */ 95 #define PTENOCACHE (0<<7) 96 #define PTECACHE (1<<7) 97 #define PTEACCESS (1<<5) 98 #define PTEMODIFY (1<<6) 99 #define PTEMAINMEM 0 100 #define PTEIO 0 101 #define PTEPROBEMEM (PTEVALID|PTEKERNEL|PTENOCACHE|PTEWRITE|PTEMAINMEM) 102 #define PTEUNCACHED PTEACCESS /* use as software flag for putmmu */ 103 104 #define NTLBPID 64 /* limited by microsparc hardware contexts */ 105 106 #define PTEMAPMEM (1024*1024) 107 #define PTEPERTAB (PTEMAPMEM/BY2PG) 108 #define SEGMAPSIZE 128 109 110 #define INVALIDPTE 0 111 #define PPN(pa) (((ulong)(pa)>>4)&0x7FFFFF0) 112 #define PPT(pn) ((ulong*)KADDR((((ulong)(pn)&~0xF)<<4))) 113 114 /* 115 * Virtual addresses 116 */ 117 #define VTAG(va) ((va>>22)&0x03F) 118 #define VPN(va) ((va>>13)&0x1FF) 119 120 /* 121 * Address spaces 122 */ 123 #define KZERO 0xE0000000 /* base of kernel address space */ 124 #define KTZERO (KZERO+4*BY2PG) /* first address in kernel text */ 125 #define KSTACK 8192 /* size of kernel stack */ 126 127 #define MACHSIZE 4096 128 129 /* 130 * control registers in physical address space (ASI 20) 131 */ 132 #define IOCR 0x10000000 /* IO MMU control register */ 133 #define IBAR 0x10000004 /* IO MMU page table base address */ 134 #define AFR 0x10000018 /* address flush register */ 135 #define AFSR 0x10001000 /* asynch fault status */ 136 #define AFAR 0x10001004 /* asynch fault address */ 137 #define SSCR(i) (0x10001010+(i)*4) /* Sbus slot i config register */ 138 #define MFSR 0x10001020 /* memory fault status register */ 139 #define MFAR 0x10001024 /* memory fault address register */ 140 #define MID 0x10002000 /* sbus arbitration enable */ 141 142 #define SYSCTL 0x71F00000 /* system control & reset register */ 143 #define PROCINTCLR 0x71E00004 /* clear pending processor interrupts */ 144 145 /* 146 * IO MMU page table entry 147 */ 148 #define IOPTEVALID (1<<1) 149 #define IOPTEWRITE (1<<2) 150