1 /* 2 * most device registers are memory mapped, but 3 * a few things are accessed using putphys/getphys 4 */ 5 #define SBUS(n) (0x30000000+(n)*0x10000000) 6 #define FRAMEBUF(n) SBUS(n) 7 #define FRAMEBUFID(n) (SBUS(n)+0x000000) 8 #define DISPLAYRAM(n) (SBUS(n)+0x800000) 9 #define CLOCK 0x71D00000 10 #define CLOCKFREQ 1000000 /* one microsecond increments */ 11 12 #define SUPERIO_PHYS_PAGE 0x71300000 13 #define SUPERIO_INDEX_OFFSET 0x398 14 #define SUPERIO_DATA_OFFSET 0x399 15 #define SUPERIO_MOUSE_KBD_DATA_PORT 0x60 16 #define SUPERIO_MOUSE_KBD_CTL_PORT 0x64 17 18 #define AUDIO_PHYS_PAGE 0x66666666 19 #define AUDIO_INDEX_OFFSET 0x830 20 21 enum 22 { 23 Mousevec = 13, 24 Kbdvec = 13 25 }; 26 27 #define NVR_CKSUM_PHYS 0x71200000 /* non-volatile RAM cksum page */ 28 #define NVR_PHYS 0x71201000 /* non-volatile RAM */ 29 #define DMA 0x78400000 /* SCSI and Ether DMA registers */ 30 #define SCSI 0x78800000 /* NCR53C90 registers */ 31 #define ETHER 0x78C00000 /* RDP, RAP */ 32 #define FLOPPY 0x71400000 33 #define SYSINTR 0x71E10000 /* system interrupt control registers */ 34 35 #define TIMECONFIG 0x71D10010 /* timer configuration register (phys) */ 36 #define AUXIO1 0x71900000 37 #define AUXIO2 0x71910000 38 39 typedef struct Sysint Sysint; 40 struct Sysint 41 { 42 ulong pending; 43 ulong mask; 44 ulong maskclr; 45 ulong maskset; 46 ulong target; 47 }; 48 49 enum { 50 MaskAllIntr = 1<<31, 51 MEIntr = 1<<30, 52 MSIIntr = 1<<29, 53 EMCIntr = 1<<28, 54 VideoIntr = 1<<20, /* supersparc only */ 55 Timer10 = 1<<19, 56 EtherIntr = 1<<16, 57 SCCIntr = 1<<15, 58 KbdIntr = 1<<13, 59 /* bits 7 to 13 are SBUS levels 1 to 7 */ 60 }; 61 #define SBUSINTR(x) (1<<((x)+6)) 62 63 typedef struct SCCdev SCCdev; 64 struct SCCdev 65 { 66 uchar ptrb; 67 uchar dummy1; 68 uchar datab; 69 uchar dummy2; 70 uchar ptra; 71 uchar dummy3; 72 uchar dataa; 73 uchar dummy4; 74 }; 75 76 /* 77 * non-volatile ram 78 */ 79 #define NVREAD (4096-32) /* minus RTC */ 80 #define NVWRITE (0x800) /* */ 81 #define IDOFF (4096-8-32) 82 83 /* 84 * real-time clock 85 */ 86 typedef struct RTCdev RTCdev; 87 struct RTCdev 88 { 89 uchar control; /* read or write the device */ 90 uchar sec; 91 uchar min; 92 uchar hour; 93 uchar wday; 94 uchar mday; 95 uchar mon; 96 uchar year; 97 }; 98 #define RTCOFF 0xFF8 99 #define RTCREAD (0x40) 100 #define RTCWRITE (0x80) 101 102 /* 103 * dma 104 */ 105 typedef struct DMAdev DMAdev; 106 struct DMAdev { 107 /* ESP/SCSI DMA */ 108 ulong csr; /* Control/Status */ 109 ulong addr; /* address in 16Mb segment */ 110 ulong count; /* transfer byte count */ 111 ulong diag; 112 113 /* Ether DMA */ 114 ulong ecsr; /* Control/Status */ 115 ulong ediag; 116 ulong cache; /* cache valid bits */ 117 uchar base; /* base address (16Mb segment) */ 118 }; 119 120 enum { 121 Int_pend = 0x00000001, /* interrupt pending */ 122 Err_pend = 0x00000002, /* error pending */ 123 Pack_cnt = 0x0000000C, /* pack count (mask) */ 124 Int_en = 0x00000010, /* interrupt enable */ 125 Dma_Flush = 0x00000020, /* flush pack end error */ 126 Drain = 0x00000040, /* drain pack to memory */ 127 Dma_Reset = 0x00000080, /* hardware reset (sticky) */ 128 Write = 0x00000100, /* set for device to memory (!) */ 129 En_dma = 0x00000200, /* enable DMA */ 130 Req_pend = 0x00000400, /* request pending */ 131 Byte_addr = 0x00001800, /* next byte addr (mask) */ 132 En_cnt = 0x00002000, /* enable count */ 133 Tc = 0x00004000, /* terminal count */ 134 Ilacc = 0x00008000, /* which ether chip */ 135 Dev_id = 0xF0000000, /* device ID */ 136 }; 137 138 /* 139 * NCR53C90 SCSI controller (every 4th location) 140 */ 141 typedef struct SCSIdev SCSIdev; 142 struct SCSIdev { 143 uchar countlo; /* byte count, low bits */ 144 uchar pad1[3]; 145 uchar countmi; /* byte count, middle bits */ 146 uchar pad2[3]; 147 uchar fifo; /* data fifo */ 148 uchar pad3[3]; 149 uchar cmd; /* command byte */ 150 uchar pad4[3]; 151 union { 152 struct { /* read only... */ 153 uchar status; /* status */ 154 uchar pad05[3]; 155 uchar intr; /* interrupt status */ 156 uchar pad06[3]; 157 uchar step; /* sequence step */ 158 uchar pad07[3]; 159 uchar fflags; /* fifo flags */ 160 uchar pad08[3]; 161 uchar config; /* RW: configuration */ 162 uchar pad09[3]; 163 uchar Reserved1; 164 uchar pad0A[3]; 165 uchar Reserved2; 166 uchar pad0B[3]; 167 uchar conf2; /* RW: configuration */ 168 uchar pad0C[3]; 169 uchar conf3; /* RW: configuration */ 170 uchar pad0D[3]; 171 uchar partid; /* unique part id */ 172 uchar pad0E[3]; 173 uchar fbottom; /* RW: fifo bottom */ 174 uchar pad0F[3]; 175 }; 176 struct { /* write only... */ 177 uchar destid; /* destination id */ 178 uchar pad15[3]; 179 uchar timeout; /* during selection */ 180 uchar pad16[3]; 181 uchar syncperiod; /* synchronous xfr period */ 182 uchar pad17[3]; 183 uchar syncoffset; /* synchronous xfr offset */ 184 uchar pad18[3]; 185 uchar RW0; 186 uchar pad19[3]; 187 uchar clkconf; 188 uchar pad1A[3]; 189 uchar test; 190 uchar pad1B[3]; 191 uchar RW1; 192 uchar pad1C[3]; 193 uchar RW2; 194 uchar pad1D[3]; 195 uchar counthi; /* byte count, hi bits */ 196 uchar pad1E[3]; 197 uchar RW3; 198 uchar pad1F[3]; 199 }; 200 }; 201 }; 202 203 /* 204 * DMA2 ENET 205 */ 206 enum { 207 E_Int_pend = 0x00000001, /* interrupt pending */ 208 E_Err_pend = 0x00000002, /* error pending */ 209 E_draining = 0x0000000C, /* E-cache draining */ 210 E_Int_en = 0x00000010, /* interrupt enable */ 211 E_Invalidate = 0x00000020, /* mark E-cache invalid */ 212 E_Slave_err = 0x00000040, /* slave access size error (sticky) */ 213 E_Reset = 0x00000080, /* invalidate cache & reset interface (sticky) */ 214 E_Drain = 0x00000400, /* force draining of E-cache to memory */ 215 E_Dsbl_wr_drn = 0x00000800, /* disable E-cache drain on descriptor writes from ENET */ 216 E_Dsbl_rd_drn = 0x00001000, /* disable E-cache drain on slave reads to ENET */ 217 E_Ilacc = 0x00008000, /* `modifies ENET DMA cycle' */ 218 E_Dsbl_buf_wr = 0x00010000, /* disable buffering of slave writes to ENET */ 219 E_Dsbl_wr_inval = 0x00020000, /* do not invalidate E-cache on slave writes */ 220 E_Burst_size = 0x000C0000, /* DMA burst size */ 221 E_Loop_test = 0x00200000, /* loop back mode */ 222 E_TP_select = 0x00400000, /* zero for AUI mode */ 223 E_Dev_id = 0xF0000000, /* device ID */ 224 }; 225