1*74a4d8c2SCharles.Forsyth typedef struct Conf Conf; 2*74a4d8c2SCharles.Forsyth typedef struct FPenv FPenv; 3*74a4d8c2SCharles.Forsyth typedef struct FPU FPU; 4*74a4d8c2SCharles.Forsyth typedef struct Label Label; 5*74a4d8c2SCharles.Forsyth typedef struct Lock Lock; 6*74a4d8c2SCharles.Forsyth typedef struct Mach Mach; 7*74a4d8c2SCharles.Forsyth typedef struct Ureg Ureg; 8*74a4d8c2SCharles.Forsyth typedef struct Lance Lance; 9*74a4d8c2SCharles.Forsyth typedef struct Lancemem Lancemem; 10*74a4d8c2SCharles.Forsyth typedef struct Etherpkt Etherpkt; 11*74a4d8c2SCharles.Forsyth typedef struct Lancepkt Lancepkt; 12*74a4d8c2SCharles.Forsyth 13*74a4d8c2SCharles.Forsyth typedef ulong Instr; 14*74a4d8c2SCharles.Forsyth 15*74a4d8c2SCharles.Forsyth struct Conf 16*74a4d8c2SCharles.Forsyth { 17*74a4d8c2SCharles.Forsyth int nmach; /* processors */ 18*74a4d8c2SCharles.Forsyth int nproc; /* processes */ 19*74a4d8c2SCharles.Forsyth ulong monitor; /* graphics monitor id; 0 for none */ 20*74a4d8c2SCharles.Forsyth char ss2; /* is a sparcstation 2 */ 21*74a4d8c2SCharles.Forsyth char ss2cachebug; /* has sparcstation2 cache bug */ 22*74a4d8c2SCharles.Forsyth int ncontext; /* in mmu */ 23*74a4d8c2SCharles.Forsyth int vacsize; /* size of virtual address cache, in bytes */ 24*74a4d8c2SCharles.Forsyth int vaclinesize; /* size of cache line */ 25*74a4d8c2SCharles.Forsyth ulong npage0; /* total physical pages of memory, bank 0 */ 26*74a4d8c2SCharles.Forsyth ulong npage1; /* total physical pages of memory, bank 1 */ 27*74a4d8c2SCharles.Forsyth ulong base0; /* base of bank 0 */ 28*74a4d8c2SCharles.Forsyth ulong base1; /* base of bank 1 */ 29*74a4d8c2SCharles.Forsyth ulong ialloc; /* max interrupt time allocation in bytes */ 30*74a4d8c2SCharles.Forsyth ulong npage; /* total physical pages of memory */ 31*74a4d8c2SCharles.Forsyth int copymode; /* 0 is copy on write, 1 is copy on reference */ 32*74a4d8c2SCharles.Forsyth ulong ipif; /* Ip protocol interfaces */ 33*74a4d8c2SCharles.Forsyth ulong ip; /* Ip conversations per interface */ 34*74a4d8c2SCharles.Forsyth ulong arp; /* Arp table size */ 35*74a4d8c2SCharles.Forsyth ulong frag; /* Ip fragment assemble queue size */ 36*74a4d8c2SCharles.Forsyth }; 37*74a4d8c2SCharles.Forsyth 38*74a4d8c2SCharles.Forsyth 39*74a4d8c2SCharles.Forsyth /* 40*74a4d8c2SCharles.Forsyth * FPenv.status 41*74a4d8c2SCharles.Forsyth */ 42*74a4d8c2SCharles.Forsyth enum 43*74a4d8c2SCharles.Forsyth { 44*74a4d8c2SCharles.Forsyth FPINIT, 45*74a4d8c2SCharles.Forsyth FPACTIVE, 46*74a4d8c2SCharles.Forsyth FPINACTIVE, 47*74a4d8c2SCharles.Forsyth }; 48*74a4d8c2SCharles.Forsyth 49*74a4d8c2SCharles.Forsyth struct FPenv 50*74a4d8c2SCharles.Forsyth { 51*74a4d8c2SCharles.Forsyth ulong status; 52*74a4d8c2SCharles.Forsyth ulong pad; 53*74a4d8c2SCharles.Forsyth }; 54*74a4d8c2SCharles.Forsyth 55*74a4d8c2SCharles.Forsyth /* 56*74a4d8c2SCharles.Forsyth * This structure must agree with fpsave and fprestore asm routines 57*74a4d8c2SCharles.Forsyth */ 58*74a4d8c2SCharles.Forsyth struct FPU 59*74a4d8c2SCharles.Forsyth { 60*74a4d8c2SCharles.Forsyth 61*74a4d8c2SCharles.Forsyth double regs[17]; /* floating point registers */ 62*74a4d8c2SCharles.Forsyth FPenv env; 63*74a4d8c2SCharles.Forsyth }; 64*74a4d8c2SCharles.Forsyth 65*74a4d8c2SCharles.Forsyth /* 66*74a4d8c2SCharles.Forsyth * machine dependent definitions used by ../port/dat.h 67*74a4d8c2SCharles.Forsyth */ 68*74a4d8c2SCharles.Forsyth 69*74a4d8c2SCharles.Forsyth struct Label 70*74a4d8c2SCharles.Forsyth { 71*74a4d8c2SCharles.Forsyth ulong sp; 72*74a4d8c2SCharles.Forsyth ulong pc; 73*74a4d8c2SCharles.Forsyth }; 74*74a4d8c2SCharles.Forsyth 75*74a4d8c2SCharles.Forsyth struct Lock 76*74a4d8c2SCharles.Forsyth { 77*74a4d8c2SCharles.Forsyth ulong key; 78*74a4d8c2SCharles.Forsyth ulong pc; 79*74a4d8c2SCharles.Forsyth ulong sr; 80*74a4d8c2SCharles.Forsyth int pri; 81*74a4d8c2SCharles.Forsyth }; 82*74a4d8c2SCharles.Forsyth 83*74a4d8c2SCharles.Forsyth #include "../port/portdat.h" 84*74a4d8c2SCharles.Forsyth 85*74a4d8c2SCharles.Forsyth /* 86*74a4d8c2SCharles.Forsyth * machine dependent definitions not used by ../port/dat.h 87*74a4d8c2SCharles.Forsyth */ 88*74a4d8c2SCharles.Forsyth 89*74a4d8c2SCharles.Forsyth struct Mach 90*74a4d8c2SCharles.Forsyth { 91*74a4d8c2SCharles.Forsyth ulong ticks; /* of the clock since boot time */ 92*74a4d8c2SCharles.Forsyth int machno; /* physical id of this processor */ 93*74a4d8c2SCharles.Forsyth Proc *proc; /* current process on this processor */ 94*74a4d8c2SCharles.Forsyth Label sched; /* scheduler wakeup */ 95*74a4d8c2SCharles.Forsyth Lock alarmlock; /* access to alarm list */ 96*74a4d8c2SCharles.Forsyth void *alarm; /* alarms bound to this clock */ 97*74a4d8c2SCharles.Forsyth ulong *contexts; /* hardware context table */ 98*74a4d8c2SCharles.Forsyth ulong *ctx; /* the context */ 99*74a4d8c2SCharles.Forsyth int fptrap; /* FP trap occurred while unsave */ 100*74a4d8c2SCharles.Forsyth 101*74a4d8c2SCharles.Forsyth int nrdy; 102*74a4d8c2SCharles.Forsyth 103*74a4d8c2SCharles.Forsyth int stack[1]; 104*74a4d8c2SCharles.Forsyth }; 105*74a4d8c2SCharles.Forsyth 106*74a4d8c2SCharles.Forsyth /* 107*74a4d8c2SCharles.Forsyth * XXX - Eric: It just works.... 108*74a4d8c2SCharles.Forsyth */ 109*74a4d8c2SCharles.Forsyth 110*74a4d8c2SCharles.Forsyth /* 111*74a4d8c2SCharles.Forsyth * LANCE CSR3 (bus control bits) 112*74a4d8c2SCharles.Forsyth */ 113*74a4d8c2SCharles.Forsyth #define BSWP 0x4 114*74a4d8c2SCharles.Forsyth #define ACON 0x2 115*74a4d8c2SCharles.Forsyth #define BCON 0x1 116*74a4d8c2SCharles.Forsyth 117*74a4d8c2SCharles.Forsyth struct Lancepkt 118*74a4d8c2SCharles.Forsyth { 119*74a4d8c2SCharles.Forsyth uchar d[6]; 120*74a4d8c2SCharles.Forsyth uchar s[6]; 121*74a4d8c2SCharles.Forsyth uchar type[2]; 122*74a4d8c2SCharles.Forsyth uchar data[1500]; 123*74a4d8c2SCharles.Forsyth uchar crc[4]; 124*74a4d8c2SCharles.Forsyth }; 125*74a4d8c2SCharles.Forsyth 126*74a4d8c2SCharles.Forsyth /* 127*74a4d8c2SCharles.Forsyth * system dependent lance stuff 128*74a4d8c2SCharles.Forsyth * filled by lancesetup() 129*74a4d8c2SCharles.Forsyth */ 130*74a4d8c2SCharles.Forsyth struct Lance 131*74a4d8c2SCharles.Forsyth { 132*74a4d8c2SCharles.Forsyth ushort lognrrb; /* log2 number of receive ring buffers */ 133*74a4d8c2SCharles.Forsyth ushort logntrb; /* log2 number of xmit ring buffers */ 134*74a4d8c2SCharles.Forsyth ushort nrrb; /* number of receive ring buffers */ 135*74a4d8c2SCharles.Forsyth ushort ntrb; /* number of xmit ring buffers */ 136*74a4d8c2SCharles.Forsyth ushort *rap; /* lance address register */ 137*74a4d8c2SCharles.Forsyth ushort *rdp; /* lance data register */ 138*74a4d8c2SCharles.Forsyth ushort busctl; /* bus control bits */ 139*74a4d8c2SCharles.Forsyth uchar ea[6]; /* our ether addr */ 140*74a4d8c2SCharles.Forsyth int sep; /* separation between shorts in lance ram 141*74a4d8c2SCharles.Forsyth as seen by host */ 142*74a4d8c2SCharles.Forsyth ushort *lanceram; /* start of lance ram as seen by host */ 143*74a4d8c2SCharles.Forsyth Lancemem *lm; /* start of lance ram as seen by lance */ 144*74a4d8c2SCharles.Forsyth Lancepkt *rp; /* receive buffers (host address) */ 145*74a4d8c2SCharles.Forsyth Lancepkt *tp; /* transmit buffers (host address) */ 146*74a4d8c2SCharles.Forsyth Lancepkt *lrp; /* receive buffers (lance address) */ 147*74a4d8c2SCharles.Forsyth Lancepkt *ltp; /* transmit buffers (lance address) */ 148*74a4d8c2SCharles.Forsyth }; 149*74a4d8c2SCharles.Forsyth 150*74a4d8c2SCharles.Forsyth /* 151*74a4d8c2SCharles.Forsyth * Fake kmap 152*74a4d8c2SCharles.Forsyth */ 153*74a4d8c2SCharles.Forsyth typedef void KMap; 154*74a4d8c2SCharles.Forsyth #define VA(k) ((ulong)(k)) 155*74a4d8c2SCharles.Forsyth #define kmap(p) (KMap*)((p)->pa|KZERO) 156*74a4d8c2SCharles.Forsyth #define kunmap(k) 157*74a4d8c2SCharles.Forsyth #define MACHP(n) (n==0? &mach0 : *(Mach**)0) 158*74a4d8c2SCharles.Forsyth 159*74a4d8c2SCharles.Forsyth extern Mach *m; 160*74a4d8c2SCharles.Forsyth extern Proc *up; 161*74a4d8c2SCharles.Forsyth extern Mach mach0; 162*74a4d8c2SCharles.Forsyth 163*74a4d8c2SCharles.Forsyth #define swcursor 1 164